CN114362726A - Fault signal latch circuit - Google Patents
Fault signal latch circuit Download PDFInfo
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- CN114362726A CN114362726A CN202111657196.8A CN202111657196A CN114362726A CN 114362726 A CN114362726 A CN 114362726A CN 202111657196 A CN202111657196 A CN 202111657196A CN 114362726 A CN114362726 A CN 114362726A
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Abstract
The invention discloses a fault signal latch circuit. The fail signal latch circuit includes: the device comprises a fault signal end, a reset signal end, a latch fault signal end, a logic element, a feedback resistor and a diode; the fault signal terminal is used for receiving a fault signal; a reset signal terminal for receiving a reset signal; the latch fault signal end is used for outputting a latch fault signal; the fault signal end is electrically connected with the first input end of the logic element; the reset signal end is electrically connected with the first end of the diode; the second end of the diode is electrically connected with the second input end of the logic element; the output end of the logic element is electrically connected with the latch fault signal end; the output end of the logic element is electrically connected with the first end of the feedback resistor, and the second end of the feedback resistor is electrically connected with the second end of the diode. The scheme realizes the effect of detecting and maintaining the fault signal and simultaneously realizes the design of the latch circuit with simple structure, low cost, stability and reliability.
Description
Technical Field
The embodiment of the invention relates to a latch circuit technology, in particular to a fault signal latch circuit.
Background
The fault hardware latch circuit is a circuit for detecting and maintaining a fault signal when a system has a fault, and can avoid that the fault cannot be detected due to disappearance of an input low-level fault signal or the fault state of the system enters a disordered state due to frequent switching of the fault state caused by frequent jumping between high and low levels of the fault signal.
In the prior art, a fault latch circuit can complete a fault latch method by using an AND gate and an OR gate, and has a fault clearing function, but at least two chips are required to complete the function in actual use due to the adoption of two different gate circuits, so that the complexity and the cost of a system are increased.
Disclosure of Invention
The invention provides a fault signal latch circuit, which is designed to be simple in structure, low in cost, stable, reliable and easy to implement.
The embodiment of the invention provides a fault signal latch circuit, which comprises: the device comprises a fault signal end, a reset signal end, a latch fault signal end, a logic element, a feedback resistor and a diode;
the fault signal terminal is used for receiving a fault signal; the reset signal terminal is used for receiving a reset signal; the latch fault signal end is used for outputting a latch fault signal;
the fault signal terminal is electrically connected with the first input terminal of the logic element; the reset signal end is electrically connected with the first end of the diode; a second terminal of the diode is electrically connected with a second input terminal of the logic element; the output end of the logic element is electrically connected with the latch fault signal end;
the output end of the logic element is electrically connected with the first end of the feedback resistor, and the second end of the feedback resistor is electrically connected with the second end of the diode.
Optionally, the logic element includes an and gate module;
the first input end of the AND gate module is electrically connected with the fault signal end; the second input end of the AND gate module is electrically connected with the second end of the feedback resistor; and the output end of the AND gate module is electrically connected with the latch fault signal end.
Optionally, the diode comprises a first unidirectional diode;
the output end of the first unidirectional diode is electrically connected with the second input end of the AND gate module; the input end of the first unidirectional diode is electrically connected with the reset signal end.
Optionally, the logic element comprises an or gate module;
the first input end of the OR gate module is electrically connected with the fault signal end; the second input end of the OR gate module is electrically connected with the second end of the feedback resistor; and the output end of the OR gate module is electrically connected with the latch fault signal end.
Optionally, the diode comprises a second unidirectional diode;
the output end of the second unidirectional diode is electrically connected with the second input end of the OR gate module; and the input end of the second unidirectional diode is electrically connected with the reset signal end.
Optionally, the value range of the resistance R of the feedback resistor satisfies: 103Ω≤R≤105Ω。
Optionally, the logic element further comprises at least one third input terminal;
at least one of the third input terminals is electrically connected to the fault signal terminal.
Optionally, the logic element includes a first logic unit, a second logic unit, a third logic unit.
The first input end of the first logic unit is electrically connected with the reset signal end; the second input end of the first logic unit is the first input end of the logic element;
the output end of the first logic unit is electrically connected with the second input end of the second logic unit, and the first input end of the second logic unit is the second input end of the logic element;
the output end of the second logic unit is electrically connected with the second input end of the third logic unit, and the first input end of the third logic unit is electrically connected with the third input end of the logic element;
…
the output end of the third logic unit is electrically connected with the second input end of the Nth latch unit, and the first input end of the Nth logic unit is the Nth input end of the logic element;
wherein N is greater than or equal to 3.
In the embodiment of the invention, the fault signal end is electrically connected with the first input end of the logic element; the reset signal end is electrically connected with the first end of the diode; the second end of the diode is electrically connected with the second input end of the logic element; the output end of the logic element is electrically connected with the latch fault signal end; the output end of the logic element is electrically connected with the first end of the feedback resistor, and the second end of the feedback resistor is electrically connected with the second end of the diode, so that the effect of detecting and maintaining the fault signal is realized, and meanwhile, the design of the latch circuit with simple structure, low cost, stability and reliability is realized.
Drawings
Fig. 1 is a schematic structural diagram of a fault signal latch circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another exemplary embodiment of a fault signal latch circuit;
FIG. 3 is a schematic diagram of another exemplary embodiment of a fault signal latch circuit;
FIG. 4 is a schematic structural diagram of a fault signal latch circuit according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of another fault signal latch circuit according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic structural diagram of a fault signal latch circuit according to an embodiment of the present invention, as shown in fig. 1, the fault signal latch circuit includes a fault signal terminal, a reset signal terminal, a latch fault signal terminal, a logic element U1, a feedback resistor R, and a diode D; the fault signal terminal is used for receiving a fault signal; a reset signal terminal for receiving a reset signal; the latch fault signal end is used for outputting a latch fault signal; the fault signal terminal is electrically connected with a first input terminal of the logic element U1; the reset signal end is electrically connected with the first end of the diode D; a second terminal of the diode D is electrically connected to a second input terminal of the logic element U1; the output end of the logic element U1 is electrically connected with the latch fault signal end; an output terminal of the logic element U1 is electrically connected to a first terminal of a feedback resistor R, and a second terminal of the feedback resistor R is electrically connected to a second terminal of the diode D.
In practice, the fault signal terminal can receive a fault signal output by the system; the single chip microcomputer can be used for detecting a latch fault signal output by the latch fault signal end and providing a reset signal through the reset signal end; the logic element U1 may include an and gate or an or gate. According to the technical scheme, the function of latching the fault signal is achieved through the logic element U1 and the feedback resistor R together, the diode D provides a channel of a reset signal, and the function of eliminating the fault signal is achieved through the diode D, the logic element U1 and the feedback resistor R; therefore, the fault signal latch circuit can keep and detect the fault signals with effective high level and effective low level; meanwhile, the design of simple structure, low cost, stability, reliability and easy realization of the latch circuit is realized.
Optionally, fig. 2 is a schematic structural diagram of another fault signal latch circuit provided in the embodiment of the present invention, and as shown in fig. 2, the logic element U1 includes an and gate module 01; a first input end of the AND gate module 01 is electrically connected with a fault signal end; a second input end of the AND gate module 01 is electrically connected with a second end of the feedback resistor R; and the output end of the AND gate module 01 is electrically connected with the latch fault signal end.
Optionally, as shown in fig. 2, the diode D includes a first unidirectional diode D1; the output end of the first unidirectional diode D1 is electrically connected with the second input end of the AND gate module 01; the input terminal of the first unidirectional diode D1 is electrically connected to the reset signal terminal.
After the system is powered on and finishes initialization operation, because signals are unstable in the initialization process, a fault signal end is a low level signal, a reset signal end is a low level signal, the output end of the AND gate module 01 outputs a latched fault signal which is a low level, and the system is in a fault state; at this time, even if the fault signal end jumps from a low level signal to a high level signal, since the low level signal at the output end of the and gate module 01 is fed back to the second input end of the and gate module 01 through the feedback resistor R, and the second input end of the and gate module 01 is a low level signal, the output end of the and gate module 01 latches the low level fault signal;
in order to eliminate the fault state of the system, the fault signal end outputs a fault-free high-level state, the single chip microcomputer outputs a high-level signal through the reset signal end, the first one-way diode D1 is conducted, the output end of the AND gate module 01 outputs a high-level signal, the output end of the AND gate module 01 is changed from a low-level fault signal into a high-level signal, and the latch circuit completes the reset function;
under normal operation, the reset signal end outputs a low level signal, the first diode D1 is cut off in the reverse direction, and a high level signal at the output end of the and gate module 01 is fed back to the second input end of the and gate module 01 through the feedback resistor R to maintain the high level state of the second input end;
when a system fails, the fault signal end jumps from a high level signal to a low level signal, the output end of the AND gate module 01 changes from the high level signal to a low level signal, the low level signal at the output end of the AND gate module 01 is fed back to the second input end of the AND gate module 01 through the feedback resistor R, so that the second input end is the low level signal, and even if the fault signal jumps from the low level signal to the high level signal, the output latch fault signal at the output end of the AND gate module 01 is at a low level, and the latch of the fault signal with effective low level is achieved.
Optionally, the resistance value range of the feedback resistor R satisfies: 103Ω≤R≤105Ω。
If the resistance value of the feedback resistor R is too small, the current passing through the feedback resistor R is large and easily exceeds the driving capability of the single chip microcomputer, so that the voltage at one end of the feedback resistor R connected with the output end of the diode D is pulled down, and if the resistance value of the feedback resistor R is too large, a signal at the output end of the logic element U1 cannot be fed back to the second input end of the logic element U1, and the capability of feeding back the signal cannot be achieved; the value range of the feedback resistor R is selected as follows: 103Ω≤R≤105Within omega, the problem that the latch circuit cannot reset can be avoided, and certain feedback signal capability of the feedback resistor is ensured.
Optionally, fig. 3 is a schematic structural diagram of another fault signal latch circuit provided in the embodiment of the present invention, and as shown in fig. 3, the logic element U1 includes an or gate module 02; a first input end of the or gate module 02 is electrically connected with a fault signal end; a second input end of the or gate module 02 is electrically connected with a second end of the feedback resistor R; the output end of the or gate module 02 is electrically connected with the latch fault signal end.
Optionally, as shown in fig. 3, the diode D includes a second unidirectional diode D2; the output end of the second unidirectional diode D2 is electrically connected with the second input end of the OR gate module 02; the input terminal of the second unidirectional diode D2 is electrically connected to the reset signal terminal.
After the system is powered on and finishes initialization operation, due to instability of signals in the initialization process, a fault signal end is a low-level signal, a reset signal end is a low-level signal, or an output end of the gate module 02 outputs a latching fault signal which is a low-level signal;
when the fault signal end jumps from a low level to a high level signal, the system is in a fault state, or the level of the output end of the gate module 02 jumps from the low level to the high level, the high level signal of the output end of the and gate module 02 is fed back to the second input end of the or gate module 02 through the feedback resistor R, or the second input end of the gate module 02 is a high level signal, even if the fault signal end changes from the high level to the low level signal, or the output end of the gate module 02 latches the fault signal at the high level, so that the latch of the fault signal with high level effectiveness is achieved.
In order to eliminate the fault state of the system, the fault signal end outputs a fault-free low level state, the single chip microcomputer outputs a low level signal through the reset signal end, the second diode D2 is conducted, the output end of the OR gate module 02 outputs a low level signal, or the output end of the OR gate module 02 is changed from a high level fault signal into a low level signal, and the latch circuit completes the reset function;
under normal operation, the reset signal end outputs a high level signal, the second diode D2 is cut off in the reverse direction, and a low level signal at the output end of the or gate module 02 is fed back to the second input end of the or gate module 02 through the feedback resistor R to maintain the low level state of the second input end;
when the system fails again, the fault signal end jumps to a high level signal from a low level signal, or the output end of the gate module 02 changes from a low level to a high level, or the high level of the output end of the gate module 02 is fed back to the second input end of the gate module 02 through the feedback resistor R, so that the second input end is a high level signal, even if the fault signal jumps to the low level signal from the high level, or the output latch fault signal of the output end of the gate module 02 is a high level signal, and the latch of the high level effective fault signal is achieved.
Optionally, fig. 4 is a schematic structural diagram of another fault signal latch circuit provided in the embodiment of the present invention, and as shown in fig. 4, the logic element U1 further includes at least one third input terminal; and the at least one third input end is electrically connected with the fault signal end.
The logic element U1 further includes a plurality of third input terminals, each of which is electrically connected to the fault signal terminal, and the fault signal terminal outputs different fault signals, so that the logic element U1 and the feedback resistor R can latch a plurality of fault signals; and the elimination of the plurality of fault signals is realized by the logic element U1, the feedback resistor R and the diode D.
Optionally, fig. 5 is a schematic structural diagram of another fault signal latch circuit according to an embodiment of the present invention, and as shown in fig. 5, the logic element U1 includes a first logic unit U11, a second logic unit U12, a third logic unit U13.. and an nth logic unit U1N;
a first input end of the first logic unit U11 is electrically connected with a reset signal end; the second input of the first logic unit U11 is the first input of logic element U1;
the output end of the first logic unit U11 is electrically connected with the second input end of the second logic unit U12, and the first input end of the second logic unit U12 is the second input end of the logic element U1;
the output terminal of the second logic unit U12 is electrically connected to the second input terminal of the third logic unit U13, the first input terminal of the third logic unit U13 is electrically connected to the third input terminal of the logic element U1;
…
the output end of the third logic unit U13 is electrically connected to the second input end of the Nth latch unit U1N, and the first input end of the Nth logic unit U1N is the Nth input end of the logic element U1;
wherein N is greater than or equal to 3.
The input of a plurality of fault signals is realized in a mode of cascading a plurality of logic units, so that the latch function of the plurality of fault signals and the fault elimination function of the plurality of fault signals are realized; it is understood that each logic unit in the logic element U1 may also implement input of multiple fault signals in other cascading manners, and the embodiment does not specifically limit the cascading manner of multiple logic units.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (8)
1. A fault signal latch circuit, comprising: the device comprises a fault signal end, a reset signal end, a latch fault signal end, a logic element, a feedback resistor and a diode;
the fault signal terminal is used for receiving a fault signal; the reset signal terminal is used for receiving a reset signal; the latch fault signal end is used for outputting a latch fault signal;
the fault signal terminal is electrically connected with the first input terminal of the logic element; the reset signal end is electrically connected with the first end of the diode; a second terminal of the diode is electrically connected with a second input terminal of the logic element; the output end of the logic element is electrically connected with the latch fault signal end;
the output end of the logic element is electrically connected with the first end of the feedback resistor, and the second end of the feedback resistor is electrically connected with the second end of the diode.
2. The fault signal latching circuit according to claim 1, wherein the logic element comprises an and gate block;
the first input end of the AND gate module is electrically connected with the fault signal end; the second input end of the AND gate module is electrically connected with the second end of the feedback resistor; and the output end of the AND gate module is electrically connected with the latch fault signal end.
3. The fault signal latch circuit according to claim 2, wherein the diode includes a first unidirectional diode;
the output end of the first unidirectional diode is electrically connected with the second input end of the AND gate module; the input end of the first unidirectional diode is electrically connected with the reset signal end.
4. The fail signal latch circuit of claim 1, wherein the logic element comprises an or gate module;
the first input end of the OR gate module is electrically connected with the fault signal end; the second input end of the OR gate module is electrically connected with the second end of the feedback resistor; and the output end of the OR gate module is electrically connected with the latch fault signal end.
5. The fault signal latch circuit according to claim 4, wherein the diode includes a second unidirectional diode;
the output end of the second unidirectional diode is electrically connected with the second input end of the OR gate module; and the input end of the second unidirectional diode is electrically connected with the reset signal end.
6. The fault signal latch circuit according to claim 1, wherein a resistance R of the feedback resistor has a value range satisfying: 103Ω≤R≤105Ω。
7. The fail signal latch circuit of claim 1, wherein the logic element further comprises at least one third input terminal;
at least one of the third input terminals is electrically connected to the fault signal terminal.
8. The fail signal latch circuit according to claim 7, wherein the logic elements include a first logic unit, a second logic unit, a third logic unit, and an nth logic unit;
the first input end of the first logic unit is electrically connected with the reset signal end; the second input end of the first logic unit is the first input end of the logic element;
the output end of the first logic unit is electrically connected with the second input end of the second logic unit, and the first input end of the second logic unit is the second input end of the logic element;
the output end of the second logic unit is electrically connected with the second input end of the third logic unit, and the first input end of the third logic unit is electrically connected with the third input end of the logic element;
…
the output end of the third logic unit is electrically connected with the second input end of the Nth latch unit, and the first input end of the Nth logic unit is the Nth input end of the logic element;
wherein N is greater than or equal to 3.
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|---|---|---|---|
| CN202111657196.8A CN114362726A (en) | 2021-12-31 | 2021-12-31 | Fault signal latch circuit |
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| CN202111657196.8A CN114362726A (en) | 2021-12-31 | 2021-12-31 | Fault signal latch circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116560347A (en) * | 2023-06-27 | 2023-08-08 | 江铃汽车股份有限公司 | New energy automobile fault management method and system |
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2021
- 2021-12-31 CN CN202111657196.8A patent/CN114362726A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116560347A (en) * | 2023-06-27 | 2023-08-08 | 江铃汽车股份有限公司 | New energy automobile fault management method and system |
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