CN113764333A - 移除抗蚀剂层的方法及制造半导体结构的方法 - Google Patents
移除抗蚀剂层的方法及制造半导体结构的方法 Download PDFInfo
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- CN113764333A CN113764333A CN202110173149.XA CN202110173149A CN113764333A CN 113764333 A CN113764333 A CN 113764333A CN 202110173149 A CN202110173149 A CN 202110173149A CN 113764333 A CN113764333 A CN 113764333A
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Abstract
提供一种包括以下步骤的移除抗蚀剂层的方法。在材料层上形成图案化抗蚀剂层。对图案化抗蚀剂层施加剥除溶液以溶解图案化抗蚀剂层而不溶解材料层,其中剥除溶液包含非二甲亚砜溶剂及碱性化合物,非二甲亚砜溶剂包含非质子溶剂及质子溶剂。
Description
技术领域
本发明的实施例涉及移除抗蚀剂层的方法及制造半导体结构的方法。
背景技术
随着半导体技术的发展,需要将更多的功能集成到半导体管芯中。因此,半导体管芯需要将越来越大数目的输入/输出(I/O)接垫包装至更小的面积中,且输入/输出接垫的密度随着时间迅速上升。因此,对半导体管芯的封装变得更困难,此会不利地影响封装的良率(yield)。目前,集成扇出型封装变得越来越流行,这是因为管芯上的输入/输出接垫可被重布到比管芯大的面积,且因此包装在管芯的表面上的输入/输出接垫的数目可增加。这种封装技术的另一个有利特征是“已知良好的管芯”被封装,而有缺陷的管芯被丢弃,且因此成本及努力不会浪费在有缺陷的管芯上。
发明内容
本发明实施例提供一种移除抗蚀剂层的方法,其至少包括以下步骤。在材料层上形成图案化抗蚀剂层。对所述图案化抗蚀剂层施加剥除溶液以溶解所述图案化抗蚀剂层而不溶解所述材料层,其中所述剥除溶液包含非二甲亚砜溶剂及碱性化合物,所述非二甲亚砜溶剂包含非质子溶剂及质子溶剂。
本发明实施例提供一种制造半导体结构的方法,其至少包括以下步骤。形成晶种层。在所述晶种层上形成图案化掩模层,其中所述图案化掩模层具有暴露出所述晶种层的多个开口。在所述多个开口中形成多个金属图案。通过施加剥除溶液以使所述图案化掩模层断裂成碎片并将所述图案化掩模层的所述碎片溶解在所述剥除溶液中,对所述图案化掩模层执行剥除工艺,其中所述剥除溶液包含非二甲亚砜溶剂及碱性化合物,所述非二甲亚砜溶剂包含非质子溶剂及质子溶剂。
本发明实施例提供一种制造半导体结构的方法,其至少包括以下步骤。在载体上形成多个导电穿孔。在所述载体上设置管芯。用包封体在侧向上包封所述管芯及所述多个导电穿孔,其中在所述载体上形成所述多个导电穿孔包括:在所述载体上依序形成晶种层及抗蚀剂层;对所述抗蚀剂层进行图案化以形成暴露出所述晶种层的多个开口;在所述多个开口中形成多个金属图案;以及用剥除溶液执行剥除工艺以移除经图案化的所述抗蚀剂层,其中所述剥除溶液包含非二甲亚砜溶剂及碱性化合物,所述非二甲亚砜溶剂包含非质子溶剂及质子溶剂。
附图说明
接合附图阅读以下详细说明,会最好地理解本公开的各个方面。应注意,根据本行业中的标准惯例,各种特征并非按比例绘制。事实上,为论述清晰起见,可任意增大或减小各种特征的尺寸。
图1A到图1L是根据本公开一些实施例的制造封装结构的方法中的各个阶段的示意性剖视图。
图2A是示出根据本公开一些实施例的图1E的阶段中的结构的一部分的示意性俯视图。
图2B是示出根据本公开一些实施例的图1F的阶段中的结构的一部分的示意性俯视图。
图3A到图3E是根据本公开一些实施例的图1D中的图案化抗蚀剂层的剥除工艺中的各个步骤的示意性剖视图。
图4是根据本公开一些替代实施例的封装结构的示意性剖视图。
图5是根据本公开一些替代实施例的封装结构的示意性剖视图。
图6是根据本公开一些替代实施例的封装结构的示意性剖视图。
图7是根据本公开一些替代实施例的封装结构的示意性剖视图。
图8是根据本公开一些替代实施例的封装结构的示意性剖视图。
图9是根据本公开一些替代实施例的封装结构的示意性剖视图。
图10是根据本公开一些替代实施例的封装结构的示意性剖视图。
图11是根据本公开一些替代实施例的封装结构的示意性剖视图。
[符号的说明]
10、30、40、50、60、70、80、90:封装结构
20:叠层封装(PoP)结构
100、720、840、920、954:导电穿孔
102:金属图案
104:晶种层图案
110、700、900:管芯
111、701、811、821、901、952:半导体衬底
112、140、208、212、302、702、812、822、956、990:导电接垫
113、703、813、823:钝化层
114、704、814、824:后钝化层
115、400、705、825、905:导电柱
116、706、826、906:保护层
120、120’、210、710、830、910、970:包封体
130、600、930、980:重布线层
132、602、816、932:介电层
134、604、734、815、934:导电层
142、214、992:导电元件
200:第二封装
202:衬底
204:半导体管芯
206:接合线
216、960:底部填充胶
300:封装组件
730:内连层
732:层间介电层
800、P:封装
810:第一管芯
820:第二管芯
940:导电端子
942:凸块
944:金属顶盖
950:载体管芯
A:穿孔密集区
B:穿孔稀疏区
BL:缓冲层
C:载体
D、D1、D2、D3、D4、D5、D6:接合膜
DB:剥离层
DL:切分线
F:框架
H1、H2、H3、Hc:高度
O:开口
P1、Pc:节距
PR:抗蚀剂层
PR’:图案化抗蚀剂层
SL:晶种层
T:胶带
T1、T2、T3、T4:层级结构
W1、W2、W3、Wc:宽度
X、Z:方向
具体实施方式
以下公开内容提供用于实施所提供主题的不同特征的许多不同的实施例或实例。以下阐述组件及布置的具体实例以简化本公开。当然,这些仅为实例而非旨在进行限制。举例来说,在以下说明中,在第二特征之上或第二特征上形成第一特征可包括其中第一特征与第二特征被形成为直接接触的实施例,且也可包括其中第一特征与第二特征之间可形成附加特征从而使得第一特征与第二特征可不直接接触的实施例。另外,本公开在各种实例中可重复使用参考编号和/或字母。此种重复使用是为了简明及清晰起见,且自身并不表示所论述的各个实施例和/或配置之间的关系。
此外,为易于说明,本文中可能使用例如“在...之下”、“在...下方”、“下部的”、“在...上方”、“上部的”等空间相对性用语来阐述图中所示一个元件或特征与另一(其他)元件或特征的关系。所述空间相对性用语旨在除图中所绘示的取向外还囊括装置在使用或操作中的不同取向。设备可另外取向(旋转90度或处于其他取向),且本文中所用的空间相对性描述语可同样相应地进行解释。
另外,为易于说明,本文中可使用例如“第一”、“第二”、“第三”、“第四”等用语来阐述图中所示相似或不同的元件或特征,且可依据存在的次序或说明的上下文而互换地使用。
也可包括其他特征及工艺。举例来说,可包括测试结构,以帮助对三维(three-dimensional,3D)封装或三维集成电路(three-dimensional integrated circuit,3DIC)装置进行验证测试。所述测试结构可例如包括在重布线层中或在衬底上形成的测试接垫,以使得能够对三维封装或三维集成电路进行测试、对探针和/或探针卡(probe card)进行使用等。可对中间结构以及最终结构执行验证测试。另外,本文中所公开的结构及方法可接合包括对已知良好管芯进行中间验证的测试方法来使用,以提高良率并降低成本。
图1A到图1L是根据本公开一些实施例的制造封装结构的方法中的各个阶段的示意性剖视图。
参考图1A,提供载体C,载体C上形成有剥离层DB及缓冲层BL。在一些实施例中,载体C可为玻璃载体或任何适用于为封装结构的制造方法承载半导体晶片或重构晶片(reconstituted wafer)的载体。在一些实施例中,载体C可具有圆形俯视形状,且可具有硅晶片的大小。
在一些实施例中,剥离层DB与载体C的图示顶表面物理接触,且可通过例如涂布、叠层(lamination)或沉积等合适的制作技术来形成。在一些实施例中,剥离层DB的材料可为适用于将载体C从上方的层或设置在其上的任何晶片接合及剥离的任何材料。在一些实施例中,剥离层DB可包括由介电材料制成的介电材料层,所述介电材料包括任何合适的聚合物系介电材料(例如苯并环丁烯(benzocyclobutene,BCB)、聚苯并恶唑(polybenzoxazole,PBO))。在替代实施例中,剥离层DB可包括介电材料层,所述介电材料层是由在受热时会失去其粘合性质的环氧系热释放材料(例如光热转换(light-to-heat-conversion,LTHC)释放涂膜)制成。在另一个替代实施例中,剥离层DB可包括介电材料层,所述介电材料层是由在暴露于紫外(ultra-violet,UV)光时会失去其粘合性质的紫外(UV)胶制成。在某些实施例中,剥离层DB可作为液体进行分配dispensed)并进行固化,或者可为被叠层到载体C上的叠层体膜(laminate film),或者可为类似物。在一些实施例中,剥离层DB的与接触载体C的图示底表面相对的图示顶表面可被整平,且可具有高平面度(degreeof planarity),但是本公开不限于此。在某些实施例中,剥离层DB例如是具有良好耐化学性(chemical resistance)的LTHC释放层,且这种层能够通过施加激光辐射来在室温下从载体C剥离,然而本公开不限于此。
在一些实施例中,缓冲层BL与剥离层DB的图示顶表面物理接触,且剥离层DB位于载体C与缓冲层BL之间。在一些实施例中,缓冲层BL可通过例如涂布、叠层或沉积等合适的制作技术来形成。在一些实施例中,缓冲层BL例如是例如聚酰亚胺、BCB、PBO等聚合物。在一些替代实施例中,缓冲层BL可包括非有机介电材料,例如氧化硅、氮化硅、碳化硅、氮氧化硅等。应注意剥离层DB、载体C及缓冲层BL的材料仅用于说明,且本公开不限于此。缓冲层BL的与接触剥离层DB的图示底表面相对的图示顶表面可被整平,且可具有高平面度。然而,本公开不限于此;在其他实施例中,可省略缓冲层BL。
参考图1B,在剥离层DB上共形地形成晶种层SL。在一些实施例中,晶种层SL与剥离层DB的图示顶表面物理接触。如图1B所示,晶种层SL是单层,但是本公开不限于此。在一些替代实施例中,晶种层SL可为由不同材料形成的复合层。在一些实施例中,晶种层SL的材料可包括铜、铜合金、钛、氮化钛、钽、氮化钽、其组合或其他合适的材料。在某些实施例中,晶种层SL包括钛/铜复合层。在一些实施例中,晶种层SL的厚度可介于约10nm到约1000nm的范围内。在一些实施例中,晶种层SL通过例如溅镀或物理气相沉积(physical vapordeposition,PVD)等合适的制作技术来形成。
继续图1B,在晶种层SL上形成抗蚀剂层PR。如图1B所示,抗蚀剂层PR作为毯覆层形成在晶种层SL上,以完全覆盖晶种层SL。在一些实施例中,抗蚀剂层PR可由干膜光刻胶层形成,所述干膜光刻胶层叠层在晶种层SL上。在一些替代实施例中,抗蚀剂层PR可由液体光刻胶层形成,所述液体光刻胶层被涂布在晶种层SL上。在一些实施例中,抗蚀剂层PR的材料例如包括正性抗蚀剂材料或负性抗蚀剂材料。在一些实施例中,抗蚀剂层PR的材料可包括含酯基的抗蚀剂材料。在一些实施例中,抗蚀剂层PR适合于随后的图案化工艺,例如具有掩模的光刻工艺(例如,极紫外(extreme ultraviolet,EUV)光刻)或无掩模光刻工艺(例如,电子束(electron-beam,e-beam)写入(electron-beam writing,e-beam writing)或离子束写入)。在本公开中,抗蚀剂层PR可被称为光刻胶层。
参考图1C,对抗蚀剂层PR进行图案化以形成图案化抗蚀剂层PR’,图案化抗蚀剂层PR’中形成有多个开口O。如图1C所示,晶种层SL的多个部分分别被图案化抗蚀剂层PR’的多个开口O暴露出。开口O的数目可对应于后来形成的导电结构(例如,图1D中绘示的金属图案102)的数目,且因此开口O的数目不受图1C中呈现的图示限制。换句话说,图案化抗蚀剂层PR’可被称为用于后来形成的导电结构的图案化掩模层。在一些实施例中,如上所述,抗蚀剂层PR可通过具有掩模的光刻工艺来图案化,所述光刻工艺可包括以下步骤:在抗蚀剂层PR之上设置光掩模;以电磁辐射通过光掩模全面地照射抗蚀剂层PR,以使抗蚀剂层PR的部分成为被暴露于电磁辐射的部分且使剩余的抗蚀剂层PR成为未暴露于电磁辐射的部分;移除光掩模;以及通过显影剂移除抗蚀剂层PR的被暴露的部分或未暴露部分,以形成具有多个开口O的图案化抗蚀剂层PR’。在一些实施例中,每个开口O被形成为具有圆形俯视形状。然而,本公开不限于此。在一些替代实施例中,从俯视图看,每个开口O可表现为多边形形状或其他合适的形状。如图1C所示,由图案化抗蚀剂层PR’界定的每个开口O的侧壁是垂直轮廓,但是本公开不限于此。在一些替代实施例中,可在对应于由图案化抗蚀剂层PR’界定的每个开口O的下侧壁中观察到具有底切(undercut)的凹入轮廓(reentrant profile)。
参考图1D,在晶种层SL上及多个开口O中形成多个金属图案102。在一些实施例中,金属图案102的材料可包括铜、铝、钛、镍、钨和/或其合金。在一些实施例中,金属图案102可通过电镀、无电镀覆、浸镀等来形成。如图1D所示,金属图案102的图示顶表面低于图案化抗蚀剂层PR’的图示顶表面,使得金属图案102的形状被开口O限制。也就是说,多个金属图案102中的每一者的轮廓(contour)实质上相同于对应开口O的轮廓。换句话说,多个金属图案102中的每一者的俯视形状实质上相同于对应开口O的俯视形状。因此,在一些实施例中,每个金属图案102被形成为具有圆形俯视形状。然而,本公开不限于此。在一些替代实施例中,从俯视图看,金属图案102可表现为多边形形状或其他合适的形状。此外,如图1D所示,由于每个开口O的垂直侧壁,金属图案102具有垂直侧表面。然而,本公开不限于此。在一些替代实施例中,由于在每个开口O的下侧壁中形成的具有底切的凹入轮廓,金属图案102可不具有垂直侧表面。
在一些实施例中,在平行于载体C的法线方向的方向Z上,每个金属图案102的高度H1介于约15μm与约360μm之间的范围内。在一些实施例中,在垂直于方向Z的方向X上,每个金属图案102的宽度W1介于约5μm与约120μm之间的范围内。在每个金属图案102具有圆形俯视形状(如图2A所示)的情况下,则宽度W1可为直径。在每个金属图案102从俯视图看具有多边形形状的情况下,则宽度W1可为最大尺寸。在一些实施例中,每个金属图案102的纵横比(aspect ratio)(即,高度H1与宽度W1的比率)大于约3,即,金属图案102被形成为具有高纵横比。在某些实施例中,每个金属图案102的纵横比介于大于约3到约15的范围内。如上所述,金属图案102形成在图案化抗蚀剂层PR’的开口O中并由开口O限制,由此在每个金属图案102的纵横比(即,高度H1与宽度W1的比率)大于约3的情况下,每个开口O的纵横比必须大于约3。在一些实施例中,两个相邻金属图案102的节距(pitch)P1介于约6μm与约360μm之间的范围内。在某些实施例中,两个相邻金属图案102的节距P1介于约30μm与约120μm之间的范围内,即,金属图案102可被形成为具有高分布密度。
参考图1E,在形成金属图案102之后,对图案化抗蚀剂层PR’执行剥除工艺以移除图案化抗蚀剂层PR’。详细来说,在剥除工艺期间,图案化抗蚀剂层PR’被移除,以暴露出未被多个金属图案102覆盖的晶种层SL。也就是说,在剥除工艺期间,图案化抗蚀剂层PR’被移除,而下伏晶种层SL及多个金属图案102被保留。换句话说,在剥除工艺之后,多个金属图案102保留在晶种层SL上。在一些实施例中,保留在晶种层SL上的多个金属图案102呈阵列,如图2A所示,图2A是示出根据本公开一些实施例的图1E的阶段中的结构的一部分的示意性俯视图。在随后的工艺中,多个金属图案102被用作掩模,以用于部分地移除晶种层SL而得到多个导电穿孔100(如图1F所示)。鉴于此,参考图2A及图1E,在剥除工艺之后获得的结构可具有穿孔稀疏区B及被穿孔稀疏区B包围的穿孔密集区A。详细来说,如图2A所示,与穿孔稀疏区B中的金属图案102的密度相比,穿孔密集区A中的金属图案102的密度相对高。此外,在图2A中,在穿孔稀疏区B中没有金属图案102,但是本公开不限于此。在一些替代实施例中,金属图案102可位于穿孔稀疏区B中,而穿孔稀疏区B中的金属图案102的密度相当低。应注意,图2A中所示的穿孔密集区A的数目以及穿孔稀疏区B及穿孔密集区A的布置仅是为了说明,且本公开不限于此。
在传统剥除工艺期间,如果金属图案被形成为具有高纵横比,则穿孔密集区的边界处的金属图案朝向相邻的穿孔稀疏区倾斜或塌陷,这会导致所得封装结构的失败。参考图2A及图1E,在图案化抗蚀剂层PR’被移除之后,穿孔密集区A中的金属图案102保持实质上完整,而没有倾斜、倒落或塌陷。也就是说,在穿孔密集区A的边界处的金属图案102没有倾斜或塌陷的风险的情况下,穿孔密集区A中的金属图案102可被形成为具有高纵横比。下面将结合图3A到图3E更详细地论述关于对图案化抗蚀剂层PR’执行的剥除工艺的说明。
参考图1D到图1E及图3A到图3E,对图案化抗蚀剂层PR’执行剥除工艺以溶解图案化抗蚀剂层PR’,而不溶解晶种层SL及多个金属图案102。详细来说,在对图案化抗蚀剂层PR’执行剥除工艺期间,对图案化抗蚀剂层PR’施加剥除溶液,以使图案化抗蚀剂层PR’断裂成碎片,并将碎片溶解在剥除溶液中。在一些实施例中,剥除溶液可通过浸渍或其他合适的方法来施加。
在一些实施例中,剥除溶液包含非二甲亚砜溶剂及碱性化合物,且非二甲亚砜溶剂包括非质子溶剂及质子溶剂。也就是说,用于溶解图案化抗蚀剂层PR’的剥除溶液不含二甲亚砜溶剂。换句话说,非质子溶剂不包括二甲亚砜。在一些实施例中,非质子溶剂可包括N-甲基吡咯烷酮(N-methylpyrrolidone,NMP)、四氢呋喃(tetrahydrofuran,THF)、二甲基甲酰胺(dimethylformamide,DMF)、乙腈(MeCN)或二氯甲烷(dichloromethance,DCM),但不限于此。在一些实施例中,质子溶剂例如是烷醇胺溶剂(alkanolamine solvent)。烷醇胺溶剂可包括乙醇胺(ethanol amine,MEA)、甲基乙醇胺(methyl ethanol amine)、2-(2-氨乙基氨基)乙醇(2-(2-aminoethylamino)ethanol)或二乙醇胺(diethanolamine),但不限于此。如图3A到图3B所示,由于使用非二甲亚砜溶剂,因此图案化抗蚀剂层PR’不太可能溶胀。在某些实施例中,在剥除工艺期间,图案化抗蚀剂层PR’的体积溶胀百分比接近0%。大规模体积溶胀可导致朝向金属图案102的高应力,且然后可导致金属图案102倾斜、倒落或塌陷,因此通过使用非二甲亚砜溶剂,本公开的剥除溶液可将金属图案102的失败率(例如,倾斜或塌陷百分比(倾斜/塌陷百分比))最小化。在一些实施例中,碱性化合物例如是强碱性化合物。强碱性化合物可包括四甲基氢氧化铵(tetra-methyl ammonium hydroxide,TMAH)、氢氧化钾(KOH)、氢氧化钠(NaOH)或其组合。在某些实施例中,碱性化合物包括TMAH与KOH的混合物。详细来说,碱性化合物可在非二甲亚砜溶剂渗透到图案化抗蚀剂层PR’的同时渗透到图案化抗蚀剂层PR’中,且然后碱性化合物可与图案化抗蚀剂层PR’的交联结构反应,以使交联结构断裂(即,裂解图案化抗蚀剂层PR’)。此外,质子溶剂具有质子特性,使得质子溶剂可加速经裂解的图案化抗蚀剂层PR’在非二甲亚砜溶剂中的溶解速率。
如上所述,当剥除溶液包含碱性化合物以及含有非质子溶剂及质子溶剂的非二甲亚砜溶剂时,金属图案102的倾斜/塌陷百分比可被最小化,且经裂解的图案化抗蚀剂层PR’在非二甲亚砜溶剂中的溶解速率可增加。因此,参考图3B到图3D,通过使用所述剥除溶液,图案化抗蚀剂层PR’可从上到下逐层断裂成碎片,且所述碎片可溶解到剥除溶液中。结果,参考图3D到图3E,当一些碎片从金属图案102剥落时,很少或没有拉力施加在金属图案102上。也就是说,通过使用所述剥除溶液,图案化抗蚀剂层PR’的断裂碎片足够小,而不会导致金属图案102倾斜或塌陷。换句话说,虽然金属图案102具有大于约3的高纵横比,但是通过在剥除工艺中对图案化抗蚀剂层PR’施加包含碱性化合物以及含有非质子溶剂及质子溶剂的非二甲亚砜溶剂的剥除溶液,在穿孔密集区A中的金属图案102可保持实质上完整而不会倾斜或塌陷,同时图案化抗蚀剂层PR’被剥除溶液移除。因此,可确保随后形成的封装结构10的效能及品质。此外,如图3E所示,在使用所述剥除溶液的剥除工艺期间,晶种层SL上方的图案化抗蚀剂层PR’可被充分移除,而不存在残留物。也就是说,虽然金属图案102被布置成具有高分布密度(例如,两个相邻金属图案102的节距P1介于约30μm与约120μm之间的范围内),但是包含碱性化合物以及含有非质子溶剂及质子溶剂的非二甲亚砜溶剂的用于移除图案化抗蚀剂层PR’的剥除溶液仍然具有良好的润湿能力。因此,可确保随后形成的封装结构10的效能及品质。
在一些实施例中,以剥除溶液的总重量计,非质子溶剂的量为约20重量%到约70重量%,质子溶剂的量为约20重量%到约70重量%,且碱性化合物的量为约0.5重量%到约5.5重量%。在某些实施例中,在碱性化合物包括KOH的情况下,以剥除溶液的总重量计,KOH的量为约0.5重量%到约2.5重量%。在某些实施例中,在碱性化合物包括TMAH的情况下,以剥除溶液的总重量计,TMAH的量为约0.5重量%到约3重量%。在某些实施例中,在非质子溶剂以约20重量%到约70重量%的量使用,质子溶剂以约20重量%到约70重量%的量使用,且碱性化合物以约0.5重量%到约5.5重量%的量使用的情况下,则在剥除工艺期间金属图案102的失败率(例如,倾斜/塌陷百分比)可提高约35%。在一些实施例中,非质子溶剂的量与质子溶剂的量的比率介于约1:3.5到约3.5:1范围内。具体来说,在非质子溶剂及质子溶剂以指定比率使用的情况下,则在剥除工艺期间金属图案102的失败率(例如,倾斜/塌陷百分比)可提高约35%。在某些实施例中,非质子溶剂的量与质子溶剂的量的比率可为1:1。在一些实施例中,剥除工艺的工艺时间介于约1分钟到约180分钟范围内。在一些实施例中,剥除工艺的工艺温度介于约25℃到约100℃范围内。具体来说,在剥除工艺的工艺时间及工艺温度落在上述指定范围内的情况下,则在剥除工艺期间金属图案102的失败率(例如,倾斜/塌陷百分比)可提高约35%。
返回参考图1E及图1F,在移除图案化抗蚀剂层PR’之后,移除晶种层SL的未被多个金属图案102覆盖的部分,以在缓冲层BL与多个金属图案102之间形成多个晶种层图案104。也就是说,多个金属图案102用作用于部分地移除晶种层SL的掩模。换句话说,多个晶种层图案104源自晶种层SL的被多个金属图案102覆盖的部分。在一些实施例中,晶种层SL通过刻蚀工艺(例如各向异性刻蚀工艺或各向同性刻蚀工艺)被部分地移除。
如上所述,在剥除工艺期间,通过使用包含碱性化合物以及含有非质子溶剂及质子溶剂的非二甲亚砜溶剂的剥除溶液,图案化抗蚀剂层可被充分移除而不存在残留物,同时多个金属图案102可保持实质上完整而不倾斜或塌陷。鉴于此,在移除图案化抗蚀剂层PR’之后且通过使用多个金属图案102作为刻蚀掩模而形成的多个晶种层图案104的轮廓实质上相同于多个金属图案102的轮廓,如图1F所示。也就是说,多个晶种层图案104中的每一者的边缘与对应的上覆金属图案102的边缘实质上齐平。由于晶种层图案104的轮廓相同于金属图案102的轮廓,因此可有效地消除由晶种层图案及金属图案的形状错配引起的漏电问题,由此确保随后形成的封装结构10的效能及品质。在一些实施例中,在每个金属图案102具有圆形俯视形状的情况下,每个晶种层图案104被形成为具有圆形俯视形状。然而,本公开不限于此。在一些替代实施例中,从俯视图看,每个晶种层图案104可表现为多边形形状或其他合适的形状。
在一些实施例中,晶种层图案104及金属图案102被统称为导电穿孔100。如图1F所示,多个导电穿孔100设置在缓冲层BL上。如上所述,在通过将包含碱性化合物以及含有非质子溶剂及质子溶剂的非二甲亚砜溶剂的剥除溶液施加到图案化抗蚀剂层PR’上来移除图案化抗蚀剂层PR’之后,多个金属图案102可保持实质上完整,而不会倾斜或塌陷,由此通过使用多个金属图案102作为掩模形成的多个导电穿孔100可被形成为实质上垂直地竖立在缓冲层BL上。也就是说,多个导电穿孔100可实质上沿着方向Z从缓冲层BL突出。换句话说,多个导电穿孔100沿着方向Z的延伸方向可具有小于1°的角度偏移。因此,导电穿孔100的制造良率显著提高。在一些实施例中,大于或等于95%的导电穿孔100没有相对于方向Z的角度偏移,且小于或等于5%的导电穿孔100具有小于1°的相对于方向Z的角度偏移。在一些替代实施例中,几乎所有的导电穿孔100没有相对于方向Z的角度偏移。
在一些实施例中,由于多个金属图案102以阵列形式形成(如图2A所示),因此多个金属图案102作为其部分的多个导电穿孔100以阵列形式形成,如图2B所示,图2B是示出根据本公开一些实施例的图1F的阶段中的结构的一部分的示意性俯视图。在一些实施例中,在方向Z上,每个导电穿孔100的高度Hc介于约15μm与约360μm之间的范围内。在一些实施例中,在垂直于方向Z的方向X上,每个导电穿孔100的宽度Wc介于约5μm与约120μm之间的范围内。在每个导电穿孔100具有圆形俯视形状(如图2B所示)的情况下,则宽度Wc可为直径。在每个导电穿孔100从俯视图看具有多边形形状的情况下,则宽度Wc可为最大尺寸。
在一些实施例中,每个导电穿孔100的纵横比(即,高度Hc与宽度Wc的比率)大于约3,即,导电穿孔100被形成为具有高纵横比。也就是说,通过在剥除工艺中施加包含碱性化合物以及含有非质子溶剂及质子溶剂的非二甲亚砜溶剂的剥除溶液,以提供具有高纵横比而不倾斜或塌陷的金属图案102,可相应地形成具有高纵横比的导电穿孔100。在某些实施例中,每个导电穿孔100的纵横比介于大于约3到约15的范围内。此外,在一些实施例中,两个相邻导电穿孔100的节距Pc介于约6μm与约360μm之间的范围内。在某些实施例中,两个相邻导电穿孔100的节距Pc介于约30μm与约120μm之间的范围内,即,导电穿孔100可被形成为具有高分布密度。如上所述,由于即使金属图案102被布置成具有高分布密度,包含碱性化合物以及含有非质子溶剂及质子溶剂的非二甲亚砜溶剂的用于移除图案化抗蚀剂层PR’的剥除溶液仍具有良好的润湿能力,因此可相应地形成具有高分布密度且具有与金属图案102的轮廓相同的轮廓的导电穿孔100。因此,可确保随后形成的封装结构10的效能及品质。
参考图1G,可拾取至少一个管芯110并放置到缓冲层BL上。管芯110例如包括半导体衬底111、多个导电接垫112、钝化层113、后钝化层114、多个导电柱115及保护层116。详细来说,管芯110以管芯110的半导体衬底111贴合(或粘附)到缓冲层BL的方式放置在缓冲层BL上。在一些实施例中,管芯110通过接合膜D贴合(或粘附)到缓冲层BL。在一些实施例中,接合膜D可为粘合膜,例如管芯贴合膜(die attach film,DAF)。在一些替代实施例中,接合膜D可为用于熔融接合的任何材料。例如,接合膜D可为用于氧化物-氧化物熔融接合的氧化物系膜(例如,氧化硅膜)。
在一些实施例中,管芯110可为逻辑管芯(例如,中央处理器(central processingunit,CPU)、微控制器等)、存储器管芯(例如,动态随机存取存储器(dynamic randomaccess memory,DRAM)管芯、静态随机存取存储器(static random access memory,SRAM)管芯等)、电力管理管芯(例如,电力管理集成电路(power management integratedcircuit,PMIC)管芯)、射频(radio frequency,RF)管芯、传感器管芯、微机电系统(micro-electro-mechanical-system,MEMS)管芯、信号处理管芯(例如,数字信号处理(digitalsignal processing,DSP)管芯)、前端管芯(例如,模拟前端(analog front-end,AFE)管芯)等。在一些实施例中,多个导电接垫112设置在半导体衬底111之上。钝化层113形成在半导体衬底111之上且具有部分地暴露出多个导电接垫112的多个接触开口。半导体衬底111可为硅衬底,所述硅衬底包括形成在所述硅衬底中的有源组件(例如,晶体管等)及无源组件(例如,电阻器、电容器、电感器等)。导电接垫112可为铝接垫、铜接垫或其他合适的金属接垫。钝化层113可为氧化硅层、氮化硅层、氮氧化硅层、或由其他合适的介电材料形成的介电层。此外,后钝化层114形成在钝化层113之上。后钝化层114覆盖钝化层113且具有多个接触开口。多个导电接垫112被后钝化层114的多个接触开口部分地暴露出。后钝化层114可为聚酰亚胺(polyimide,PI)层、聚苯并恶唑(PBO)层或由其他合适的聚合物形成的介电层。此外,多个导电柱115被形成为延伸穿过后钝化层114中的多个接触开口,并机械及电耦合到对应的导电接垫112。在一些实施例中,导电柱115可为镀铜柱。保护层116形成在后钝化层114上以覆盖多个导电柱115。保护层116的材料可为聚合物,例如PBO、聚酰亚胺、苯并环丁烯(BCB)等;氮化物,例如氮化硅等;氧化物,例如氧化硅等;或其组合。保护层116可例如通过旋转涂布、叠层、化学气相沉积(chemical vapor deposition,CVD)等来形成。
在一些实施例中,在方向Z上,管芯110具有比导电穿孔100的高度小的厚度,如图1G所示。然而,本公开不限于此。在一些替代实施例中,在方向Z上,管芯110的厚度可大于或实质上等于导电穿孔100的高度。如图1G所示,管芯110是在形成导电穿孔100之后被拾取并放置到缓冲层BL上。然而,本公开不限于此。在一些替代实施例中,可在形成导电穿孔100之前将一个或多个管芯110拾取并放置到缓冲层BL上。在示例性实施例中,图1G中仅示出一个管芯110。然而,应注意,放置在缓冲层BL上的管芯110的数目不限于此,且这可基于设计要求来调整。在一些实施例中,当多于一个管芯110被放置在缓冲层BL上时,管芯110可被布置成阵列,且当管芯110被布置成阵列时,导电穿孔110可被分类成组。
参考图1H,在缓冲层BL之上形成包封体120,以包封管芯110及多个导电穿孔100。详细来说,形成包封体120以填充管芯110与多个导电穿孔100之间的间隙以及相邻导电穿孔100之间的间隙,使得包封体120覆盖管芯110及多个导电穿孔100的侧壁及图示顶表面。也就是说,管芯110及多个导电穿孔100嵌入在包封体120中,且不被显露。从另一个方面看,包封体120可被称为“间隙填充材料”。在一些实施例中,包封体120的材料可包括模制化合物、模制底部填充胶、树脂(例如环氧树脂)等。在一些替代实施例中,包封体120的材料可包括例如氮化硅等氮化物、例如氧化硅等氧化物、磷硅酸盐玻璃(phosphosilicate glass,PSG)、硼硅酸盐玻璃(borosilicate glass,BSG)、硼掺杂磷硅酸盐玻璃(boron-dopedphosphosilicate glass,BPSG)、其组合等。在又一替代实施例中,包封体120的材料可为有机材料(例如,环氧树脂、聚酰亚胺、PBO等),或者无机及有机材料的混合物(例如,氧化硅及环氧树脂的混合物等)。在一些实施例中,包封体120可通过模制工艺(例如压缩模制工艺)来形成。在一些替代实施例中,包封体120可通过例如化学气相沉积、高密度等离子体化学气相沉积(high-density plasma chemical vapor deposition,HDPCVD)或等离子体增强化学气相沉积(plasma-enhanced chemical vapor deposition,PECVD)等合适的制作技术来形成。
参考图1I,然后对包封体120、管芯110及多个导电穿孔100执行平坦化工艺,直到多个导电柱115的图示顶表面及多个导电穿孔100的图示顶表面被暴露出。在对包封体120执行平坦化工艺之后,在缓冲层BL之上形成包封体120’。在一些实施例中,在平坦化工艺之后,多个导电穿孔100、多个导电柱115、保护层116及包封体120’的图示顶表面实质上共面。在一些实施例中,平坦化工艺可为例如化学机械抛光(chemical-mechanical polish,CMP)、研磨工艺等。在一些实施例中,在平坦化工艺之后,可任选地执行清洁工艺。例如,执行清洁工艺以清洁及移除从平坦化工艺产生的残留物。然而,本公开不限于此,且平坦化工艺可通过任何其他合适的方法来执行。导电穿孔100穿透包封体120’,且导电穿孔100被称为集成扇出型穿孔。
参考图1J,在平坦化工艺之后,在包封体120’、多个导电穿孔100及管芯110上形成重布线层130。在一些实施例中,重布线层130形成在多个导电穿孔100、多个导电柱115、保护层116及包封体120’的图示顶表面上。也就是说,重布线层130沿着载体C及管芯110的堆叠方向(例如,方向Z)形成在包封体120’上。在一些实施例中,重布线层130电连接到多个导电穿孔100,且通过多个导电柱115电连接到管芯110。在一些实施例中,管芯110通过重布线层130电连接到多个导电穿孔100。
此外,在一些实施例中,形成重布线层130包括交替地依序形成一个或多个介电层132及一个或多个导电层134。在某些实施例中,多个导电层134夹在多个介电层132之间。尽管此处示出三层导电层134及四层介电层132,但是本公开的范围不受本公开的实施例限制。在其他实施例中,导电层134的数目及介电层132的数目可基于产品要求来调整。在一些实施例中,导电层134电连接到管芯110的导电柱115。此外,导电层134电连接到导电穿孔100。
在一些实施例中,介电层132的材料可为PI、PBO、BCB、例如氮化硅等氮化物、例如氧化硅等氧化物、PSG、BSG、BPSG、其组合等,其可使用光刻和/或刻蚀工艺而被图案化。在一些实施例中,介电层132的材料可通过例如旋涂、CVD、HDPCVD、PECVD、原子层沉积(atomiclayer deposition,ALD)等合适的制作技术来形成。在一些实施例中,导电层134的材料可由通过电镀或沉积形成的导电材料(例如铝、钛、铜、镍、钨和/或其合金)制成,其可使用光刻及刻蚀工艺来图案化。在一些实施例中,导电层134可为图案化铜层或其他合适的图案化金属层。
在形成重布线层130之后,在多个导电层134的最顶层的被暴露的顶表面上设置多个导电接垫140。在某些实施例中,导电接垫140例如是用于球安装的球下金属(under-ballmetallurgy,UBM)图案。如图1J所示,多个导电接垫140形成在重布线层130上并电连接到重布线层130。在一些实施例中,导电接垫140的材料可包括铜、镍、钛、钨或其合金等,且可例如通过电镀工艺来形成。导电接垫140的数目在本公开中不受限制,且可基于设计布局来选择。在一些替代实施例中,可省略导电接垫140。换句话说,在后续步骤中形成的多个导电元件142(下文所述)可直接设置在重布线层130上。
在形成多个导电接垫140之后,在多个导电接垫140上及重布线层130之上设置多个导电元件142。在一些实施例中,多个导电元件142可通过植球工艺和/或回焊工艺或其他合适的形成方法设置在多个导电接垫140上。在一些实施例中,导电元件142可为球栅阵列(ball grid array,BGA)连接件、焊料球、金属柱、受控塌陷芯片连接(controlledcollapse chip connection,C4)凸块、微凸块、无电镀镍钯浸金技术(electrolessnickel-electroless palladium-immersion gold technique,ENEPIG)形成的凸块等。在一些实施例中,多个导电元件142通过多个导电接垫140连接到重布线层130。在某些实施例中,多个导电元件142中的一些可通过重布线层130电连接到管芯110。此外,多个导电元件142中的一些可通过重布线层130电连接到多个导电穿孔100。导电元件142的数目不限于本公开,且可基于导电接垫140的数目来指定及选择。导电元件142的材料例如可包括导电材料,例如焊料、铜、铝、金、镍、银、钯、锡或其组合。在一个实施例中,导电元件142的材料例如可为无焊料的。
参考图1K,在形成重布线层130并在其上放置多个导电元件142之后,图1J所示的结构可被颠倒并贴合到由框架F支撑的胶带T(例如,切分胶带(dicing tape))。在一些实施例中,多个导电元件142与胶带T接触。如图1K所示,载体C被剥离并与缓冲层BL分离。在一些实施例中,剥离工艺包括将例如激光或紫外光等光投射在剥离层DB(例如,LTHC释放层)上,使得载体C可容易地与剥离层DB一起移除。在剥离步骤期间,在剥离载体C及剥离层DB之前,使用胶带T来固定封装结构。在剥离工艺之后,缓冲层BL的背侧表面(即,图1K中所示的顶表面)被显露或暴露。
参考图1K及图1L,在剥离工艺之后,沿着切分线DL执行切分工艺,以将图1K所示的整个结构切割(即,切透缓冲层BL、包封体120’及重布线层130)成多个封装结构10。封装结构10被称为集成扇出型(integrated fan-out,InFO)封装。在示例性实施例中,所述切分工艺是包括机械刀片锯切或激光切割的晶片切分工艺。在随后的工艺中,分离的封装结构10可例如基于要求设置在电路衬底上或其他组件上。
尽管将所述方法的步骤示出并阐述为一系列的动作或事件,但将知,这类动作或事件的所示出的排序不应以限制意义进行解释。另外,并不要求进行所有所示出的工艺或步骤来实施本公开的一个或多个实施例。
图4是根据本公开一些替代实施例的封装结构的示意性剖视图。与先前所述的元件相似或实质上相同的元件将使用相同的参考编号,且本文中将不重复相同元件的某些细节或说明(例如,材料、形成工艺、定位配置等)。参考图4,在制作第一封装(例如图1L所示的封装结构10)之后,可将第二封装200堆叠在封装结构10(第一封装)上,以形成叠层封装(package-on-package,PoP)结构20。如图4所示,第二封装200电连接到封装结构10(第一封装)的多个导电穿孔100。在一些实施例中,第二封装200具有衬底202、多个半导体管芯204、多个接合线206、多个导电接垫208、多个导电接垫212及包封体210。在一些实施例中,多个半导体管芯204安装在图4所示的衬底202的图示顶表面上。在一些实施例中,多个接合线206用于提供多个半导体管芯204与多个导电接垫208(例如接合接垫)之间的电连接。在一些实施例中,包封体210被形成为包封及保护多个半导体管芯204及多个接合线206。在一些实施例中,嵌入在衬底202中的多个内连线(未示出)或多个导电穿孔(未示出)可用于提供多个导电接垫208与多个导电接垫212(例如接合接垫)之间的电连接。在一些实施例中,多个导电接垫208及多个导电接垫212分别设置在衬底202的两个相对的表面上,如图4所示。在某些实施例中,多个导电接垫212通过多个内连线(未示出)或多个导电穿孔(未示出)电连接到多个半导体管芯204。在一些实施例中,封装结构200的多个导电接垫212电连接到多个导电元件214。此外,多个导电元件214电连接到封装结构10(第一封装)的多个导电穿孔100。在一些实施例中,还提供底部填充胶216来填充封装结构10(第一封装)和第二封装200之间的间隙,以保护多个导电元件214。由于底部填充胶216,第二封装200与封装结构10(第一封装)之间的接合强度增强,由此提高图4所示封装结构的可靠性。在将第二封装200堆叠在封装结构10(第一封装)上并提供其之间的电连接之后,可制作叠层封装结构20。
图5是根据本公开一些替代实施例的封装结构的示意性剖视图。与先前所述的元件相似或实质上相同的元件将使用相同的参考编号,且本文中将不重复相同元件的某些细节或说明(例如,材料、形成工艺、定位配置等)。参考图5,在一些实施例中,提供封装组件300,其中图4所示叠层封装结构20接合在封装组件300上,以形成具有堆叠结构的封装结构30。在一些实施例中,封装组件300包括多个导电接垫302。在一些实施例中,封装组件300是封装衬底,其可为无芯衬底或具有芯的衬底。在一些替代实施例中,封装组件300是印刷电路板或封装。在一些实施例中,如图5所示,叠层封装结构20中的封装结构10的多个导电元件142接合到多个导电接垫302(例如接合接垫),以提供封装组件300与叠层封装结构20之间的电连接。也就是说,叠层封装结构20物理及电连接到封装组件300。在一些实施例中,可施加底部填充胶(未示出)以填充叠层封装结构20与封装组件300之间的间隙,从而保护多个导电元件142及多个导电接垫140,这会增强叠层封装结构20与封装组件300之间的接合强度;由此提高图5所示封装结构的可靠性。
图6是根据本公开一些替代实施例的封装结构的示意性剖视图。图6中所示的封装结构40类似于图1L中所示的封装结构10,因此相同的参考编号用于指代相同或相似的部分,并且此处将省略其详细说明。下面将阐述图6所示的封装结构40与图1L所示的封装结构10之间的差异。
参考图6,在封装结构40中,多个导电柱400设置在多个导电层134的最顶层的被暴露的顶表面上。在一些实施例中,导电柱400的材料例如可包括导电材料,例如铜、铝、钛、镍、钨、锡、焊料或其组合。在某些实施例中,导电柱400可为镀铜柱。此外,参考图6及图1L,导电柱400用于代替导电接垫140,以提供导电元件142与重布线层130之间的电连接。
在图1L所示的封装结构10中,仅一个管芯110设置在多个导电穿孔100之间。然而,本公开不限于此。在一些替代实施例中,可在多个导电穿孔100之间设置多于一个管芯110。在下文中,将参考图7阐述其他实施例。
图7是根据本公开一些替代实施例的封装结构的示意性剖视图。图7中所示的封装结构50类似于图1L中所示的封装结构10,因此相同的参考编号用于指代相同或相似的部分,并且此处将省略其详细说明。参考图7及图1L,图7所示的封装结构50与图1L所示的封装结构10之间的差异在于,两个管芯110设置在封装结构50中的多个导电穿孔100之间。然而,本公开不限于此。在一些替代实施例中,可基于设计要求形成更多数目的管芯110。
图8是根据本公开一些替代实施例的封装结构的示意性剖视图。图8中所示的封装结构60类似于图1L中所示的封装结构10,因此相同的参考编号用于指代相同或相似的部分,并且此处将省略其详细说明。下面将阐述图8所示的封装结构60与图1L所示的封装结构10之间的差异。
参考图8,封装结构60中包括另一个重布线层600。在一些实施例中,如图8所示,重布线层600及重布线层130分别设置在包封体120’的两个相对的表面上。也就是说,管芯110设置在重布线层600与重布线层130之间。在一些实施例中,如图8所示,形成重布线层600包括交替地依序形成一个或多个介电层602及一个或多个导电层604。尽管图8示出重布线层600包括两个介电层602及一个导电层604,其中导电层604夹在两个介电层602之间,但是本公开不限于此。在其他实施例中,介电层602的数目及导电层604的数目可基于产品要求来调整。在一些实施例中,多个导电穿孔100电连接到重布线层600的导电层604。也就是说,在封装结构60中,多个导电穿孔100可用于提供重布线层130与重布线层600之间的电连接。在一些实施例中,重布线层600的介电层602及导电层604的材料类似于针对重布线层130提到的介电层132及导电层134的材料。因此,此处将省略介电层602及导电层604的详细说明。此外,参考图8及图1L两者,重布线层600设置在包封体120’上,以代替缓冲层BL。
图9是根据本公开一些替代实施例的封装结构的示意性剖视图。图9中所示的封装结构70类似于图1L中所示的封装结构10,因此相同的参考编号用于指代相同或相似的部分,并且此处将省略其详细说明。下面将阐述图9所示的封装结构70与图1L所示的封装结构10之间的差异。
参考图9及图1L,封装结构70与封装结构10之间的主要区别在于管芯700还包括在封装结构70中。在示例性实施例中,管芯700包括半导体衬底701、多个导电接垫702、钝化层703、后钝化层704、多个导电柱705及保护层706。管芯700的这些元件可类似于管芯110的半导体衬底111、多个导电接垫112、钝化层113、后钝化层114、多个导电柱115及保护层116,因此管芯700的所述元件的详细说明可参考管芯110的该些元件的详细说明。简单来说,多个导电接垫702位于半导体衬底701上,钝化层703及后钝化层704依序位于半导体衬底701及多个导电接垫702上,保护层706位于后钝化层704上,多个导电柱705嵌入后钝化层704及保护层706中,且多个导电柱705与多个导电接垫702电连接。如图9所示,管芯700沿着方向Z位于管芯110之上。
在一些实施例中,如图9所示,形成包封体710来包封管芯700。包封体710可类似于包封体120’,因此包封体710的详细说明可参考包封体120’的详细说明。在一些实施例中,如图9所示,多个导电穿孔720嵌入包封体710内。导电穿孔720可类似于导电穿孔100,因此导电穿孔720的详细说明可参考导电穿孔100的详细说明。简单来说,如上所述,通过在剥除工艺中施加包含碱性化合物以及含有非质子溶剂及质子溶剂的非二甲亚砜溶剂的剥除溶液,具有高纵横比的导电穿孔720可被形成为具有显著提高的制造良率。此外,如上所述,通过在剥除工艺中施加包含碱性化合物以及含有非质子溶剂及质子溶剂的非二甲亚砜溶剂的剥除溶液,导电穿孔720可被形成为具有高分布密度。
在一些实施例中,如图9所示,包封体710与包封体120’之间设置有内连层730。在一些实施例中,内连层730包括层间介电层732及多个导电层734。在一些实施例中,多个导电层734嵌入层间介电层732中。为简单起见,在图9中,层间介电层732被示为单一庞大(bulky)的层,但是应理解,层间介电层732可由多个介电层构成,且层间介电层732中的介电层的数目可根据产品要求来调整。此外,多个导电层734及层间介电层732的多个介电层可交替堆叠。应注意,图9中所示的导电层734的数目仅是说明,并且本公开不受限制。在一些替代实施例中,导电层734的数目可基于产品要求来调整。
在一些实施例中,层间介电层732的材料可为PI、PBO、BCB、例如氮化硅等氮化物、例如氧化硅等氧化物、PSG、BSG、BPSG、其组合等,其可使用光刻和/或刻蚀工艺而被图案化。在一些实施例中,层间介电层732的材料可通过例如旋涂、CVD、HDPCVD、PECVD、ALD等合适的制作技术来形成。在一些实施例中,导电层734的材料可由通过电镀或沉积形成的导电材料(例如铝、钛、铜、镍、钨和/或其合金)制成,其可使用光刻及刻蚀工艺来图案化。在一些实施例中,导电层734可为图案化铜层或其他适合的图案化金属层。
在一些实施例中,如图9所示,内连层730电连接到多个导电穿孔100、管芯110的多个导电柱115及多个导电穿孔720。在一些实施例中,管芯110通过内连层730电连接到多个导电穿孔100。在一些实施例中,如图9所示,管芯700通过接合膜D1贴合(或粘附)到内连层730中的层间介电层732。在一些实施例中,接合膜D1可为粘合膜,例如管芯贴合膜(DAF)。在一些替代实施例中,接合膜D1可为用于熔融接合的任何材料。例如,接合膜D1可为用于氧化物-氧化物熔融接合的氧化物系膜(例如,氧化硅膜)。在一些实施例中,如图9所示,重布线层130电连接到管芯700的多个导电柱705及多个导电穿孔720。此外,在一些实施例中,管芯110与管芯700可具有不同的大小(例如,不同的高度和/或表面积)。在一些替代实施例中,管芯110与管芯700可具有相同的大小(例如,相同的高度和/或表面积)。
图10是根据本公开一些替代实施例的封装结构的示意性剖视图。图10中所示的封装结构80类似于图1L中所示的封装结构10,因此相同的参考编号用于指代相同或相似的部分,并且此处将省略其详细说明。下面将阐述图10所示的封装结构80与图1L所示的封装结构10之间的差异。
参考图10及图1L,封装结构80与封装结构10之间的主要区别在于从封装结构80中省略了管芯110。详细来说,参考图10及图1L,封装800被包封体120’包封以代替管芯110。在示例性实施例中,封装800包括第一管芯810、第二管芯820、包封体830及多个导电穿孔840。如图10所示,第二管芯820沿着方向Z堆叠在第一管芯810上。换句话说,多个管芯(即第一管芯810、第二管芯820)被集成到单个封装800中。因此,封装800可被称为“集成电路上系统(system on integrated circuit,SOIC)封装”在一些实施例中,如图10所示,封装800通过接合膜D2贴合(或粘附)到缓冲层BL。在一些实施例中,接合膜D2可为粘合膜,例如管芯贴合膜(DAF)。在一些替代实施例中,接合膜D2可为用于熔融接合的任何材料。例如,接合膜D2可为用于氧化物-氧化物熔融接合的氧化物系膜(例如,氧化硅膜)。
在一些实施例中,第一管芯810可包括半导体衬底811、多个导电接垫812、钝化层813、后钝化层814、导电层815及介电层816,如图10所示。第一管芯810的半导体衬底811、导电接垫812、钝化层813及后钝化层814可类似于管芯110的半导体衬底111、导电接垫112、钝化层113及后钝化层114,因此所述元件的详细说明可参考管芯110的该些元件的详细说明。简单来说,多个导电接垫812位于半导体衬底811上,且钝化层813及后钝化层814依序位于半导体衬底811及多个导电接垫812上。在一些实施例中,如图10所示,导电层815设置在后钝化层814上,并通过后钝化层814的接触开口与多个导电接垫812电连接。在一些实施例中,导电层815的材料例如可包括导电材料,例如铜、铝、钛、镍、钨、锡、焊料或其组合。在一些实施例中,导电层815可通过例如电镀、沉积和/或光刻及刻蚀来形成。在一些实施例中,如图10所示,介电层816设置在导电层815上。在一些实施例中,介电层816的材料可为PI、PBO、BCB、例如氮化硅等氮化物、例如氧化硅等氧化物、PSG、BSG、BPSG、其组合等,其可使用光刻和/或刻蚀工艺而被图案化。在一些实施例中,介电层816的材料可通过例如旋涂、CVD、HDPCVD、PECVD、原子层沉积(ALD)等合适的制作技术来形成。介电层816的与接触导电层815的图示底表面相对的图示顶表面可被整平,且可具有高平面度。
在一些实施例中,第二管芯820可包括半导体衬底821、多个导电接垫822、钝化层823、后钝化层824、多个导电柱825及保护层826,如图10所示。第二管芯820的这些元件可类似于管芯110的半导体衬底111、多个导电接垫112、钝化层113、后钝化层114、多个导电柱115及保护层116,因此第二管芯820的所述元件的详细说明可参考管芯110的该些元件的详细说明。简单来说,多个导电接垫822位于半导体衬底821上,钝化层823及后钝化层824依序位于半导体衬底821及多个导电接垫822上,保护层826位于后钝化层824上,多个导电柱825嵌入后钝化层824及保护层826中,且多个导电柱825与多个导电接垫822电连接。此外,在一些实施例中,如图10所示,第二管芯820通过接合膜D3贴合(或粘附)到第一管芯810上的介电层816。在一些实施例中,接合膜D3可为粘合膜,例如管芯贴合膜(DAF)。在一些替代实施例中,接合膜D3可为用于熔融接合的任何材料。例如,接合膜D3可为用于氧化物-氧化物熔融接合的氧化物系膜(例如,氧化硅膜)。
在一些实施例中,如图10所示,形成包封体830来包封第二管芯820。包封体830可类似于包封体120’,因此包封体830的详细说明可参考包封体120’的详细说明。在一些实施例中,如图10所示,多个导电穿孔840嵌入包封体830内。在一些实施例中,每个导电穿孔840被形成为具有圆形俯视形状。然而,本公开不限于此。在一些替代实施例中,从俯视图看,每个导电穿孔840可表现为多边形形状或其他合适的形状。在一些实施例中,在方向Z上,每个导电穿孔840的高度H2介于约15μm与约360μm之间的范围内。在一些实施例中,在垂直于方向Z的方向X上,每个导电穿孔840的宽度W2介于约5μm与约120μm之间的范围内。在每个导电穿孔840具有圆形俯视形状的情况下,则宽度W2可为直径。在每个导电穿孔840从俯视图看具有多边形形状的情况下,则宽度W2可为最大尺寸。在一些实施例中,每个导电穿孔840的纵横比(即,高度H2与宽度W2的比率)介于大于约3到约15的范围内。根据关于图1A到图1L及图3A到图3E的说明,可推断出上面结合图3A到图3E阐述的方法可应用于包括导电穿孔(甚至具有高纵横比的导电穿孔)的任何封装结构的制造工艺。因此,本领域中的技术人员应理解,以上结合图3A到图3E阐述的方法可应用于制造导电穿孔840,由此无论导电穿孔840是否具有高纵横比,导电穿孔840都可被形成为具有显著提高的制造良率。然而,本公开不限于此。
在一些实施例中,如图10所示,多个导电穿孔840电连接到第一管芯810的导电层815。在一些实施例中,如图10所示,重布线层130电连接到多个导电穿孔100、第二管芯820的多个导电柱825及多个导电穿孔840。在一些实施例中,第二管芯820通过重布线层130及多个导电穿孔840电连接到第一管芯810。在一些实施例中,封装800通过重布线层130电连接到多个导电穿孔100。
图11是根据本公开一些替代实施例的封装结构的示意性剖视图。
参考图11,封装结构90可包括封装P、载体管芯950、底部填充胶960、包封体970、重布线层980、多个导电接垫990及多个导电元件992。在示例性实施例中,封装P包括层级(tier)结构T1、层级结构T2、层级结构T3、层级结构T4及多个导电端子940。尽管图11示出封装P包括四个层级结构(即,层级结构T1到T4),但是本公开不限于此。在其他实施例中,封装P中的层级结构的数目可基于产品要求来调整。
如图11所示,层级结构T1、层级结构T2、层级结构T3及层级结构T4中的每一者包括管芯900、包封体910及重布线层930。此外,如图11所示,层级结构T1、层级结构T2、层级结构T3及层级结构T4中的每一者包括多个导电穿孔920。在一些实施例中,如图11所示,每个管芯900可包括半导体衬底901、多个导电柱905及保护层906。管芯900的这些元件可类似于管芯110的半导体衬底111、多个导电柱115及保护层116,因此管芯900的所述元件的详细说明可参考管芯110的该些元件的详细说明。在一些实施例中,每个管芯900还可包括内连线结构(未示出)、多个导电接垫(未示出)、钝化层(未示出)及后钝化层(未示出)。在一些实施例中,每个管芯900可为存储器管芯(例如,DRAM管芯、SRAM管芯、同步动态随机存取存储器(synchronous dynamic random access memory,SDRAM)、与非(NAND)闪存等)。尽管图11示出层级结构T1、层级结构T2、层级结构T3及层级结构T4中的每一者包括两个管芯900,但是本公开不限于此。在其他实施例中,包括在层级结构中的管芯900的数目可基于产品要求来调整。此外,如图11所示,层级结构T1包括两个分离的管芯900。然而,本公开不限于此。在一些替代实施例中,层级结构T1可包括单个管芯900。
在一些实施例中,如图11所示,在层级结构T1、层级结构T2、层级结构T3及层级结构T4中的每一者中,形成包封体910来包封管芯900。包封体910可类似于包封体120’,因此包封体910的详细说明可参考包封体120’的详细说明。
在一些实施例中,如图11所示,在层级结构T2、层级结构T3及层级结构T4中的每一者中,多个导电穿孔920嵌入包封体910内。在一些实施例中,每个导电穿孔920被形成为具有圆形俯视形状。然而,本公开不限于此。在一些替代实施例中,从俯视图看,每个导电穿孔920可表现为多边形形状或其他合适的形状。在一些实施例中,在方向Z上,每个导电穿孔920的高度H3介于约15μm与约360μm之间的范围内。在一些实施例中,在垂直于方向Z的方向X上,每个导电穿孔920的宽度W3介于约5μm与约120μm之间的范围内。在每个导电穿孔920具有圆形俯视形状的情况下,则宽度W3可为直径。在每个导电穿孔920从俯视图看具有多边形形状的情况下,则宽度W3可为最大尺寸。在一些实施例中,每个导电穿孔920的纵横比(即,高度H3与宽度W3的比率)大于约3,即,导电穿孔920被形成为具有高纵横比。根据关于图1A到图1L及图3A到图3E的说明,可推断出上面结合图3A到图3E阐述的方法可应用于包括具有高纵横比的导电穿孔的任何封装结构的制造工艺。因此,本领域中的技术人员应理解,以上结合图3A到图3E阐述的方法可应用于制造导电穿孔920,由此具有高纵横比的导电穿孔920可被形成为具有显著提高的制造良率。
在一些实施例中,如图11所示,在层级结构T1、层级结构T2、层级结构T3及层级结构T4中的每一者中,重布线层930形成在包封体910及多个管芯900上。在示例性实施例中,重布线层930包括介电层932及多个导电层934。重布线层930的这些元件可类似于重布线层130的介电层132及导电层134,因此重布线层930的所述元件的详细说明可参考对重布线层130的该些元件的详细说明。为简单起见,在图11中,介电层932被示为单一庞大的层,但是应理解,介电层932可由多个介电层构成,且介电层932中的介电层的数目可根据产品要求来调整。此外,多个导电层934及介电层932的多个介电层可交替堆叠。应注意,图11中所示的导电层934的数目仅是说明,并且本公开不受限制。在一些替代实施例中,导电层934的数目可基于产品要求来调整。
在一些实施例中,如图11所示,层级结构T1的重布线层930电连接到层级结构T1的多个管芯900及层级结构T2的多个导电穿孔920;层级结构T2的重布线层930电连接到层级结构T2的多个管芯900、层级结构T2的多个导电穿孔920及层级结构T3的多个导电穿孔920;层级结构T3的重布线层930电连接到层级结构T3的多个管芯900、层级结构T3的多个导电穿孔920及层级结构T4的多个导电穿孔920;层级结构T4的重布线层930电连接到层级结构T4的多个管芯900及层级结构T4的多个导电穿孔920。在一些实施例中,如图11所示,层级结构T2中的每个管芯900通过接合膜D4贴合(或粘附)到层级结构T1的重布线层930;层级结构T3中的每个管芯900通过接合膜D5贴合(或粘附)到层级结构T2的重布线层930;层级结构T4中的每个管芯900通过接合膜D6贴合(或粘附)到层级结构T3的重布线层930。在一些实施例中,接合膜D4、接合膜D5及接合膜D6中的每一者可为粘合膜,例如管芯贴合膜(DAF)。在一些替代实施例中,接合膜D4、接合膜D5及接合膜D6中的每一者可为用于熔融接合的任何材料。例如,接合膜D4、接合膜D5及接合膜D6中的每一者可为用于氧化物-氧化物熔融接合的氧化物系膜(例如,氧化硅膜)。
在一些实施例中,如图11所示,多个导电端子940形成在层级结构T4中的重布线层930的被暴露的表面处。导电端子940可通过使用例如溅镀、印刷、镀覆、沉积等来形成。导电端子940可由导电材料(包括铜、铝、金、镍、银、钯、锡、焊料、金属合金等或其组合)来形成。在示例性实施例中,多个导电端子940中的每一者包括凸块942及形成在凸块942上的金属顶盖944,如图11所示。凸块942可为微凸块、金属柱、ENEPIG形成的凸块、C4凸块、BGA凸块等。在凸块942是微凸块的实施例中,两个相邻凸块942之间的凸块节距介于约20μm到约140μm的范围内。凸块942可为无焊料的,且可具有实质上垂直的侧壁。在一些实施例中,金属顶盖944通过例如镀覆、印刷等形成。例如,金属顶盖944的材料包括镍、锡、锡-铅、金、银、钯、镍-钯-金、镍-金等,或者这些的任意组合。
在一些实施例中,载体管芯950可为逻辑管芯(例如,CPU、微控制器、系统芯片(system-on-a-chip,SoC)、图形处理单元(graphics processing unit,GPU)等)。在一些实施例中,载体管芯950可用于为层级结构T1到T4中的管芯900提供控制功能。在示例性实施例中,载体管芯950包括半导体衬底952、多个导电穿孔954及多个导电接垫956。半导体衬底952可类似于管芯110的半导体衬底111,因此半导体衬底952的详细说明可参考半导体衬底111的详细说明。如图11所示,多个导电穿孔954穿透半导体衬底952。多个导电穿孔954可通过以下步骤形成。首先,通过例如刻蚀、铣削、激光技术或其组合在半导体衬底952中形成多个开口。然后,可通过使用例如氧化技术在多个开口中形成薄介电材料。然后,可在半导体衬底952之上及多个开口中共形地沉积阻挡层。阻挡层的材料可包括氮化物或氮氧化物,例如氮化钛、氮氧化钛、氮化钽、氮氧化钽、氮化钨或其组合。接下来,可在阻挡层之上及多个开口中沉积导电材料。导电材料可通过电化学镀覆工艺、CVD、ALD、PVD或其组合来形成。导电材料的实例是铜、钨、铝、银、金或其组合。之后,通过例如CMP从半导体衬底952移除多个开口外部的导电材料及阻挡层。因此,导电穿孔954可包含导电材料及导电材料与半导体衬底952之间的阻挡层。
在一些实施例中,如图11所示,封装P的多个导电端子940通过倒装芯片接合(flip-chip bonding)物理连接载体管芯950的多个导电接垫956(例如接合接垫),以提供封装P与载体管芯950之间的电连接。也就是说,封装P通过导电端子940及导电接垫956物理及电连接到载体管芯950。在一些实施例中,如图11所示,导电穿孔954电连接到导电接垫956。
在一些实施例中,如图11所示,提供底部填充胶960以填充封装P与载体管芯950之间的间隙。如图11所示,底部填充胶960可沿着封装P的侧壁向上延伸。由于底部填充胶960,封装P与载体管芯950之间的接合强度增强,由此提高图11所示的封装结构90的可靠性。在一些实施例中,如图11所示,形成包封体970来包封封装P及底部填充胶960。包封体970可类似于包封体120’,因此包封体970的详细说明可参考包封体120’的详细说明。
在一些实施例中,如图11所示,重布线层980形成在载体管芯950的半导体衬底952上且与封装p相对。重布线层980可以类似于重布线层130的方式形成,因此重布线层980的详细说明可参考重布线层130的详细说明。在一些实施例中,如图11所示,多个导电接垫990及多个导电元件992形成在重布线层980上且与载体管芯950相对。导电接垫990及导电元件992可类似于导电接垫140及导电元件142,因此导电接垫990及导电元件992的详细说明可参考导电接垫140及导电元件142的详细说明。在一些实施例中,重布线层980用于提供导电接垫990与导电穿孔954之间的电连接。
根据本公开的一些实施例,提供一种包括以下步骤的移除抗蚀剂层的方法。在材料层上形成图案化抗蚀剂层。对所述图案化抗蚀剂层施加剥除溶液以溶解所述图案化抗蚀剂层而不溶解所述材料层,其中所述剥除溶液包含非二甲亚砜溶剂及碱性化合物,所述非二甲亚砜溶剂包含非质子溶剂及质子溶剂。
在一些实施例中,所述非质子溶剂包括N-甲基吡咯烷酮(NMP)、四氢呋喃(THF)、二甲基甲酰胺(DMF)、乙腈(MeCN)或二氯甲烷(DCM)。在一些实施例中,所述质子溶剂包括烷醇胺溶剂。在一些实施例中,所述碱性化合物包括四甲基氢氧化铵(TMAH)、氢氧化钾(KOH)、氢氧化钠(NaOH)或其组合。在一些实施例中,以所述剥除溶液的总重量计,所述非质子溶剂的量为20重量%到70重量%,所述质子溶剂的量为20重量%到70重量%,所述碱性化合物的量为0.5重量%到5.5重量%。在一些实施例中,所述非质子溶剂的量与所述质子溶剂的量的比率介于1:3.5到3.5:1范围内。
根据本公开的一些替代实施例,提供一种包括以下步骤的制造半导体结构的方法。形成晶种层。在所述晶种层上形成图案化掩模层,其中所述图案化掩模层具有暴露出所述晶种层的多个开口。在所述多个开口中形成多个金属图案。通过施加剥除溶液以使所述图案化掩模层断裂成碎片并将所述图案化掩模层的所述碎片溶解在所述剥除溶液中,对所述图案化掩模层执行剥除工艺,其中所述剥除溶液包含非二甲亚砜溶剂及碱性化合物,所述非二甲亚砜溶剂包含非质子溶剂及质子溶剂。
在一些实施例中,所述非质子溶剂包括N-甲基吡咯烷酮(NMP)、四氢呋喃(THF)、二甲基甲酰胺(DMF)、乙腈(MeCN)或二氯甲烷(DCM),所述质子溶剂包括乙醇胺(MEA)、甲基乙醇胺、2-(2-氨基乙基氨基)乙醇或二乙醇胺,所述碱性化合物包括四甲基氢氧化铵(TMAH)、氢氧化钾(KOH)、氢氧化钠(NaOH)或其组合,且以所述剥除溶液的总重量计,所述非质子溶剂的量为20重量%到70重量%,所述质子溶剂的量为20重量%到70重量%,所述碱性化合物的量为0.5重量%到5.5重量%。在一些实施例中,所述多个金属图案被形成为具有介于30μm到120μm范围内的两个相邻金属图案的节距。在一些实施例中,所述图案化掩模层的材料包括含酯基的抗蚀剂材料。在一些实施例中,在所述剥除工艺期间,所述碱性化合物渗透到所述图案化掩模层中,以使所述图案化掩模层的交联结构断裂。在一些实施例中,所述非质子溶剂的量与所述质子溶剂的量的比率介于1:3.5到3.5:1范围内。在一些实施例中,所述多个金属图案中的至少一者被形成为具有大于3的纵横比。
根据本公开的一些替代实施例,提供一种包括以下步骤的制造半导体结构的方法。在载体上形成多个导电穿孔。在所述载体上设置管芯。用包封体在侧向上包封所述管芯及所述多个导电穿孔,其中在所述载体上形成所述多个导电穿孔包括:在所述载体上依序形成晶种层及抗蚀剂层;对所述抗蚀剂层进行图案化以形成暴露出所述晶种层的多个开口;在所述多个开口中形成多个金属图案;以及用剥除溶液执行剥除工艺以移除经图案化的所述抗蚀剂层,其中所述剥除溶液包含非二甲亚砜溶剂及碱性化合物,所述非二甲亚砜溶剂包含非质子溶剂及质子溶剂。
在一些实施例中,所述非质子溶剂包括N-甲基吡咯烷酮(NMP)、四氢呋喃(THF)、二甲基甲酰胺(DMF)、乙腈(MeCN)或二氯甲烷(DCM),所述质子溶剂包括乙醇胺(MEA)、甲基乙醇胺、2-(2-氨基乙基氨基)乙醇或二乙醇胺,所述碱性化合物包括四甲基氢氧化铵(TMAH)、氢氧化钾(KOH)、氢氧化钠(NaOH)或其组合,且以所述剥除溶液的总重量计,所述非质子溶剂的量为20重量%到70重量%,所述质子溶剂的量为20重量%到70重量%,所述碱性化合物的量为0.5重量%到5.5重量%。
以上概述了若干实施例的特征,以使本领域中的技术人员可更好地理解本公开的各个方面。本领域中的技术人员应理解,其可容易地使用本公开作为设计或修改其他工艺及结构的基础来施行与本文中所介绍的实施例相同的目的和/或实现与本文中所介绍的实施例相同的优点。本领域中的技术人员还应认识到,这些等效构造并不背离本公开的精神及范围,而且他们可在不背离本公开的精神及范围的条件下在本文中作出各种改变、代替及变更。
Claims (10)
1.一种移除抗蚀剂层的方法,包括:
在材料层上形成图案化抗蚀剂层;以及
对所述图案化抗蚀剂层施加剥除溶液以溶解所述图案化抗蚀剂层而不溶解所述材料层,其中所述剥除溶液包含非二甲亚砜溶剂及碱性化合物,所述非二甲亚砜溶剂包含非质子溶剂及质子溶剂。
2.根据权利要求1所述的移除抗蚀剂层的方法,其中所述非质子溶剂包括N-甲基吡咯烷酮(NMP)、四氢呋喃(THF)、二甲基甲酰胺(DMF)、乙腈(MeCN)或二氯甲烷(DCM),其中所述质子溶剂包括烷醇胺溶剂,其中所述碱性化合物包括四甲基氢氧化铵(TMAH)、氢氧化钾(KOH)、氢氧化钠(NaOH)或其组合。
3.根据权利要求1所述的移除抗蚀剂层的方法,其中以所述剥除溶液的总重量计,所述非质子溶剂的量为20重量%到70重量%,所述质子溶剂的量为20重量%到70重量%,所述碱性化合物的量为0.5重量%到5.5重量%。
4.根据权利要求1所述的移除抗蚀剂层的方法,其中所述非质子溶剂的量与所述质子溶剂的量的比率介于1:3.5到3.5:1范围内。
5.一种制造半导体结构的方法,包括:
形成晶种层;
在所述晶种层上形成图案化掩模层,其中所述图案化掩模层具有暴露出所述晶种层的多个开口;
在所述多个开口中形成多个金属图案;以及
通过施加剥除溶液以使所述图案化掩模层断裂成碎片并将所述图案化掩模层的所述碎片溶解在所述剥除溶液中,对所述图案化掩模层执行剥除工艺,其中所述剥除溶液包含非二甲亚砜溶剂及碱性化合物,所述非二甲亚砜溶剂包括非质子溶剂及质子溶剂。
6.根据权利要求5所述的制造半导体结构的方法,其中所述非质子溶剂包括N-甲基吡咯烷酮(NMP)、四氢呋喃(THF)、二甲基甲酰胺(DMF)、乙腈(MeCN)或二氯甲烷(DCM),所述质子溶剂包括乙醇胺(MEA)、甲基乙醇胺、2-(2-氨基乙基氨基)乙醇或二乙醇胺,所述碱性化合物包括四甲基氢氧化铵(TMAH)、氢氧化钾(KOH)、氢氧化钠(NaOH)或其组合,且以所述剥除溶液的总重量计,所述非质子溶剂的量为20重量%到70重量%,所述质子溶剂的量为20重量%到70重量%,所述碱性化合物的量为0.5重量%到5.5重量%。
7.根据权利要求5所述的制造半导体结构的方法,其中所述图案化掩模层的材料包括含酯基的抗蚀剂材料。
8.根据权利要求5所述的制造半导体结构的方法,其中在所述剥除工艺期间,所述碱性化合物渗透到所述图案化掩模层中,以使所述图案化掩模层的交联结构断裂。
9.一种制造半导体结构的方法,包括:
在载体上形成多个导电穿孔;
在所述载体上设置管芯;以及
用包封体在侧向上包封所述管芯及所述多个导电穿孔,其中在所述载体上形成所述多个导电穿孔包括:
在所述载体上依序形成晶种层及抗蚀剂层;
对所述抗蚀剂层进行图案化以形成暴露出所述晶种层的多个开口;
在所述多个开口中形成多个金属图案;以及
用剥除溶液执行剥除工艺以移除经图案化的所述抗蚀剂层,其中所述剥除溶液包含非二甲亚砜溶剂及碱性化合物,所述非二甲亚砜溶剂包含非质子溶剂及质子溶剂。
10.根据权利要求9所述的制造半导体结构的方法,其中所述剥除工艺的工艺时间介于1分钟到180分钟范围内,且所述剥除工艺的工艺温度介于25℃到100℃范围内。
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