TW202212553A - 移除抗蝕劑層的方法及製造半導體結構的方法 - Google Patents
移除抗蝕劑層的方法及製造半導體結構的方法 Download PDFInfo
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Abstract
提供一種包括以下步驟的移除抗蝕劑層的方法。在材料層上形成圖案化抗蝕劑層。對圖案化抗蝕劑層施加剝除溶液以溶解圖案化抗蝕劑層而不溶解材料層,其中剝除溶液包含非二甲亞碸溶劑及鹼性化合物,非二甲亞碸溶劑包含非質子溶劑及質子溶劑。
Description
隨著半導體技術的發展,需要將更多的功能積體到半導體晶粒中。因此,半導體晶粒需要將越來越大數目的輸入/輸出(I/O)接墊包裝至更小的面積中,且輸入/輸出接墊的密度隨著時間迅速上升。因此,對半導體晶粒的封裝變得更困難,此會不利地影響封裝的良率(yield)。目前,積體扇出型封裝變得越來越流行,這是因為晶粒上的輸入/輸出接墊可被重佈到比晶粒大的面積,且因此包裝在晶粒的表面上的輸入/輸出接墊的數目可增加。這種封裝技術的另一個有利特徵是「已知良好的晶粒」被封裝,而有缺陷的晶粒被丟棄,且因此成本及努力不會浪費在有缺陷的晶粒上。
以下公開內容提供用於實施所提供主題的不同特徵的許多不同的實施例或實例。以下闡述組件及佈置的具體實例以簡化本公開。當然,這些僅為實例而非旨在進行限制。舉例來說,在以下說明中,在第二特徵之上或第二特徵上形成第一特徵可包括其中第一特徵與第二特徵被形成為直接接觸的實施例,且也可包括其中第一特徵與第二特徵之間可形成附加特徵從而使得第一特徵與第二特徵可不直接接觸的實施例。另外,本公開在各種實例中可重複使用參考編號和/或字母。此種重複使用是為了簡明及清晰起見,且自身並不表示所論述的各個實施例和/或配置之間的關係。
此外,為易於說明,本文中可能使用例如「在...之下」、「在...下方」、「下部的」、「在...上方」、「上部的」等空間相對性用語來闡述圖中所示一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的取向外更囊括裝置在使用或操作中的不同取向。設備可另外取向(旋轉90度或處於其他取向),且本文中所用的空間相對性描述語可同樣相應地進行解釋。
另外,為易於說明,本文中可使用例如「第一」、「第二」、「第三」、「第四」等用語來闡述圖中所示相似或不同的元件或特徵,且可依據存在的次序或說明的上下文而互換地使用。
也可包括其他特徵及製程。舉例來說,可包括測試結構,以幫助對三維(three-dimensional,3D)封裝或三維積體電路(three-dimensional integrated circuit,3DIC)裝置進行驗證測試。所述測試結構可例如包括在重佈線層中或在基底上形成的測試接墊,以使得能夠對三維封裝或三維積體電路進行測試、對探針和/或探針卡(probe card)進行使用等。可對中間結構以及最終結構執行驗證測試。另外,本文中所公開的結構及方法可接合包括對已知良好晶粒進行中間驗證的測試方法來使用,以提高良率並降低成本。
圖1A到圖1L是根據本公開一些實施例的製造封裝結構的方法中的各個階段的示意性剖視圖。
參考圖1A,提供載體C,載體C上形成有剝離層DB及緩衝層BL。在一些實施例中,載體C可為玻璃載體或任何適用於為封裝結構的製造方法承載半導體晶圓或重構晶圓(reconstituted wafer)的載體。在一些實施例中,載體C可具有圓形俯視形狀,且可具有矽晶圓的大小。
在一些實施例中,剝離層DB與載體C的圖示頂表面物理接觸,且可通過例如塗佈、疊層(lamination)或沉積等合適的製作技術來形成。在一些實施例中,剝離層DB的材料可為適用於將載體C從上方的層或設置在其上的任何晶圓接合及剝離的任何材料。在一些實施例中,剝離層DB可包括由介電材料製成的介電材料層,所述介電材料包括任何合適的聚合物系介電材料(例如苯並環丁烯(benzocyclobutene,BCB)、聚苯並噁唑(polybenzoxazole,PBO))。在替代實施例中,剝離層DB可包括介電材料層,所述介電材料層是由在受熱時會失去其黏合性質的環氧系熱釋放材料(例如光熱轉換(light-to-heat-conversion,LTHC)釋放塗膜)製成。在另一個替代實施例中,剝離層DB可包括介電材料層,所述介電材料層是由在暴露於紫外(ultra-violet,UV)光時會失去其黏合性質的紫外(UV)膠製成。在某些實施例中,剝離層DB可作為液體進行分配dispensed)並進行固化,或者可為被疊層到載體C上的疊層體膜(laminate film),或者可為類似物。在一些實施例中,剝離層DB的與接觸載體C的圖示底表面相對的圖示頂表面可被整平,且可具有高平面度(degree of planarity),但是本公開不限於此。在某些實施例中,剝離層DB例如是具有良好耐化學性(chemical resistance)的LTHC釋放層,且這種層能夠通過施加雷射輻射來在室溫下從載體C剝離,然而本公開不限於此。
在一些實施例中,緩衝層BL與剝離層DB的圖示頂表面物理接觸,且剝離層DB位於載體C與緩衝層BL之間。在一些實施例中,緩衝層BL可通過例如塗佈、疊層或沉積等合適的製作技術來形成。在一些實施例中,緩衝層BL例如是例如聚醯亞胺、BCB、PBO等聚合物。在一些替代實施例中,緩衝層BL可包括非有機介電材料,例如氧化矽、氮化矽、碳化矽、氮氧化矽等。應注意剝離層DB、載體C及緩衝層BL的材料僅用於說明,且本公開不限於此。緩衝層BL的與接觸剝離層DB的圖示底表面相對的圖示頂表面可被整平,且可具有高平面度。然而,本公開不限於此;在其他實施例中,可省略緩衝層BL。
參考圖1B,在剝離層DB上共形地形成晶種層SL。在一些實施例中,晶種層SL與剝離層DB的圖示頂表面物理接觸。如圖1B所示,晶種層SL是單層,但是本公開不限於此。在一些替代實施例中,晶種層SL可為由不同材料形成的複合層。在一些實施例中,晶種層SL的材料可包括銅、銅合金、鈦、氮化鈦、鉭、氮化鉭、其組合或其他合適的材料。在某些實施例中,晶種層SL包括鈦/銅複合層。在一些實施例中,晶種層SL的厚度可介於約10 nm到約1000 nm的範圍內。在一些實施例中,晶種層SL通過例如濺鍍或物理氣相沉積(physical vapor deposition,PVD)等合適的製作技術來形成。
繼續圖1B,在晶種層SL上形成抗蝕劑層PR。如圖1B所示,抗蝕劑層PR作為毯覆層形成在晶種層SL上,以完全覆蓋晶種層SL。在一些實施例中,抗蝕劑層PR可由乾膜光阻層形成,所述乾膜光阻層疊層在晶種層SL上。在一些替代實施例中,抗蝕劑層PR可由液體光阻層形成,所述液體光阻層被塗佈在晶種層SL上。在一些實施例中,抗蝕劑層PR的材料例如包括正性抗蝕劑材料或負性抗蝕劑材料。在一些實施例中,抗蝕劑層PR的材料可包括含酯基的抗蝕劑材料。在一些實施例中,抗蝕劑層PR適合於隨後的圖案化製程,例如具有罩幕的微影製程(例如,極紫外(extreme ultraviolet,EUV)微影)或無罩幕微影製程(例如,電子束(electron-beam,e-beam)寫入(electron-beam writing, e-beam writing)或離子束寫入)。在本公開中,抗蝕劑層PR可被稱為光阻層。
參考圖1C,對抗蝕劑層PR進行圖案化以形成圖案化抗蝕劑層PR’,圖案化抗蝕劑層PR’中形成有多個開口O。如圖1C所示,晶種層SL的多個部分分別被圖案化抗蝕劑層PR’的多個開口O暴露出。開口O的數目可對應於後來形成的導電結構(例如,圖1D中繪示的金屬圖案102)的數目,且因此開口O的數目不受圖1C中呈現的圖示限制。換句話說,圖案化抗蝕劑層PR’可被稱為用於後來形成的導電結構的圖案化罩幕層。在一些實施例中,如上所述,抗蝕劑層PR可通過具有罩幕的微影製程來圖案化,所述微影製程可包括以下步驟:在抗蝕劑層PR之上設置光罩幕;以電磁輻射通過光罩幕全面地照射抗蝕劑層PR,以使抗蝕劑層PR的部分成為被暴露於電磁輻射的部分且使剩餘的抗蝕劑層PR成為未暴露於電磁輻射的部分;移除光罩幕;以及通過顯影劑移除抗蝕劑層PR的被暴露的部分或未暴露部分,以形成具有多個開口O的圖案化抗蝕劑層PR’。在一些實施例中,每個開口O被形成為具有圓形俯視形狀。然而,本公開不限於此。在一些替代實施例中,從俯視圖看,每個開口O可表現為多邊形形狀或其他合適的形狀。如圖1C所示,由圖案化抗蝕劑層PR’界定的每個開口O的側壁是垂直輪廓,但是本公開不限於此。在一些替代實施例中,可在對應於由圖案化抗蝕劑層PR’界定的每個開口O的下側壁中觀察到具有底切(undercut)的凹入輪廓(reentrant profile)。
參考圖1D,在晶種層SL上及多個開口O中形成多個金屬圖案102。在一些實施例中,金屬圖案102的材料可包括銅、鋁、鈦、鎳、鎢和/或其合金。在一些實施例中,金屬圖案102可通過電鍍、無電鍍覆、浸鍍等來形成。如圖1D所示,金屬圖案102的圖示頂表面低於圖案化抗蝕劑層PR’的圖示頂表面,使得金屬圖案102的形狀被開口O限制。也就是說,多個金屬圖案102中的每一者的輪廓(contour)實質上相同於對應開口O的輪廓。換句話說,多個金屬圖案102中的每一者的俯視形狀實質上相同於對應開口O的俯視形狀。因此,在一些實施例中,每個金屬圖案102被形成為具有圓形俯視形狀。然而,本公開不限於此。在一些替代實施例中,從俯視圖看,金屬圖案102可表現為多邊形形狀或其他合適的形狀。此外,如圖1D所示,由於每個開口O的垂直側壁,金屬圖案102具有垂直側表面。然而,本公開不限於此。在一些替代實施例中,由於在每個開口O的下側壁中形成的具有底切的凹入輪廓,金屬圖案102可不具有垂直側表面。
在一些實施例中,在平行於載體C的法線方向的方向Z上,每個金屬圖案102的高度H
1介於約15 μm與約360 μm之間的範圍內。在一些實施例中,在垂直於方向Z的方向X上,每個金屬圖案102的寬度W
1介於約5 μm與約120 μm之間的範圍內。在每個金屬圖案102具有圓形俯視形狀(如圖2A所示)的情况下,則寬度W
1可為直徑。在每個金屬圖案102從俯視圖看具有多邊形形狀的情况下,則寬度W
1可為最大尺寸。在一些實施例中,每個金屬圖案102的縱橫比(aspect ratio)(即,高度H
1與寬度W
1的比率)大於約3,即,金屬圖案102被形成為具有高縱橫比。在某些實施例中,每個金屬圖案102的縱橫比介於大於約3到約15的範圍內。如上所述,金屬圖案102形成在圖案化抗蝕劑層PR’的開口O中並由開口O限制,由此在每個金屬圖案102的縱橫比(即,高度H
1與寬度W
1的比率)大於約3的情况下,每個開口O的縱橫比必須大於約3。在一些實施例中,兩個相鄰金屬圖案102的節距(pitch)P
1介於約6 μm與約360 μm之間的範圍內。在某些實施例中,兩個相鄰金屬圖案102的節距P
1介於約30 μm與約120 μm之間的範圍內,即,金屬圖案102可被形成為具有高分佈密度。
參考圖1E,在形成金屬圖案102之後,對圖案化抗蝕劑層PR’執行剝除製程以移除圖案化抗蝕劑層PR’。詳細來說,在剝除製程期間,圖案化抗蝕劑層PR’被移除,以暴露出未被多個金屬圖案102覆蓋的晶種層SL。也就是說,在剝除製程期間,圖案化抗蝕劑層PR’被移除,而下伏晶種層SL及多個金屬圖案102被保留。換句話說,在剝除製程之後,多個金屬圖案102保留在晶種層SL上。在一些實施例中,保留在晶種層SL上的多個金屬圖案102呈陣列,如圖2A所示,圖2A是示出根據本公開一些實施例的圖1E的階段中的結構的一部分的示意性俯視圖。在隨後的製程中,多個金屬圖案102被用作罩幕,以用於部分地移除晶種層SL而得到多個導電穿孔100(如圖1F所示)。鑒於此,參考圖2A及圖1E,在剝除製程之後獲得的結構可具有穿孔稀疏區B及被穿孔稀疏區B包圍的穿孔密集區A。詳細來說,如圖2A所示,與穿孔稀疏區B中的金屬圖案102的密度相比,穿孔密集區A中的金屬圖案102的密度相對高。此外,在圖2A中,在穿孔稀疏區B中沒有金屬圖案102,但是本公開不限於此。在一些替代實施例中,金屬圖案102可位於穿孔稀疏區B中,而穿孔稀疏區B中的金屬圖案102的密度相當低。應注意,圖2A中所示的穿孔密集區A的數目以及穿孔稀疏區B及穿孔密集區A的佈置僅是為了說明,且本公開不限於此。
在傳統剝除製程期間,如果金屬圖案被形成為具有高縱橫比,則穿孔密集區的邊界處的金屬圖案朝向相鄰的穿孔稀疏區傾斜或塌陷,這會導致所得封裝結構的失敗。參考圖2A及圖1E,在圖案化抗蝕劑層PR’被移除之後,穿孔密集區A中的金屬圖案102保持實質上完整,而沒有傾斜、倒落或塌陷。也就是說,在穿孔密集區A的邊界處的金屬圖案102沒有傾斜或塌陷的風險的情况下,穿孔密集區A中的金屬圖案102可被形成為具有高縱橫比。下面將結合圖3A到圖3E更詳細地論述關於對圖案化抗蝕劑層PR’執行的剝除製程的說明。
參考圖1D到圖1E及圖3A到圖3E,對圖案化抗蝕劑層PR’執行剝除製程以溶解圖案化抗蝕劑層PR’,而不溶解晶種層SL及多個金屬圖案102。詳細來說,在對圖案化抗蝕劑層PR’執行剝除製程期間,對圖案化抗蝕劑層PR’施加剝除溶液,以使圖案化抗蝕劑層PR’斷裂成碎片,並將碎片溶解在剝除溶液中。在一些實施例中,剝除溶液可通過浸漬或其他合適的方法來施加。
在一些實施例中,剝除溶液包含非二甲亞碸溶劑及鹼性化合物,且非二甲亞碸溶劑包括非質子溶劑及質子溶劑。也就是說,用於溶解圖案化抗蝕劑層PR’的剝除溶液不含二甲亞碸溶劑。換句話說,非質子溶劑不包括二甲亞碸。在一些實施例中,非質子溶劑可包括N-甲基吡咯烷酮(N-methylpyrrolidone,NMP)、四氫呋喃(tetrahydrofuran,THF)、二甲基甲醯胺(dimethylformamide,DMF)、乙腈(MeCN)或二氯甲烷(dichloromethance,DCM),但不限於此。在一些實施例中,質子溶劑例如是烷醇胺溶劑(alkanolamine solvent)。烷醇胺溶劑可包括乙醇胺(ethanol amine,MEA)、甲基乙醇胺(methyl ethanol amine)、2-(2-氨乙基氨基)乙醇(2-(2-aminoethylamino)ethanol)或二乙醇胺(diethanolamine),但不限於此。如圖3A到圖3B所示,由於使用非二甲亞碸溶劑,因此圖案化抗蝕劑層PR’不太可能溶脹。在某些實施例中,在剝除製程期間,圖案化抗蝕劑層PR’的體積溶脹百分比接近0%。大規模體積溶脹可導致朝向金屬圖案102的高應力,且然後可導致金屬圖案102傾斜、倒落或塌陷,因此通過使用非二甲亞碸溶劑,本公開的剝除溶液可將金屬圖案102的失敗率(例如,傾斜或塌陷百分比(傾斜/塌陷百分比))最小化。在一些實施例中,鹼性化合物例如是强鹼性化合物。强鹼性化合物可包括四甲基氫氧化銨(tetra-methyl ammonium hydroxide,TMAH)、氫氧化鉀(KOH)、氫氧化鈉(NaOH)或其組合。在某些實施例中,鹼性化合物包括TMAH與KOH的混合物。詳細來說,鹼性化合物可在非二甲亞碸溶劑滲透到圖案化抗蝕劑層PR’的同時滲透到圖案化抗蝕劑層PR’中,且然後鹼性化合物可與圖案化抗蝕劑層PR’的交聯結構反應,以使交聯結構斷裂(即,裂解圖案化抗蝕劑層PR’)。此外,質子溶劑具有質子特性,使得質子溶劑可加速經裂解的圖案化抗蝕劑層PR’在非二甲亞碸溶劑中的溶解速率。
如上所述,當剝除溶液包含鹼性化合物以及含有非質子溶劑及質子溶劑的非二甲亞碸溶劑時,金屬圖案102的傾斜/塌陷百分比可被最小化,且經裂解的圖案化抗蝕劑層PR’在非二甲亞碸溶劑中的溶解速率可增加。因此,參考圖3B到圖3D,通過使用所述剝除溶液,圖案化抗蝕劑層PR’可從上到下逐層斷裂成碎片,且所述碎片可溶解到剝除溶液中。結果,參考圖3D到圖3E,當一些碎片從金屬圖案102剝落時,很少或沒有拉力施加在金屬圖案102上。也就是說,通過使用所述剝除溶液,圖案化抗蝕劑層PR’的斷裂碎片足夠小,而不會導致金屬圖案102傾斜或塌陷。換句話說,雖然金屬圖案102具有大於約3的高縱橫比,但是通過在剝除製程中對圖案化抗蝕劑層PR’施加包含鹼性化合物以及含有非質子溶劑及質子溶劑的非二甲亞碸溶劑的剝除溶液,在穿孔密集區A中的金屬圖案102可保持實質上完整而不會傾斜或塌陷,同時圖案化抗蝕劑層PR’被剝除溶液移除。因此,可確保隨後形成的封裝結構10的效能及品質。此外,如圖3E所示,在使用所述剝除溶液的剝除製程期間,晶種層SL上方的圖案化抗蝕劑層PR’可被充分移除,而不存在殘留物。也就是說,雖然金屬圖案102被佈置成具有高分佈密度(例如,兩個相鄰金屬圖案102的節距P
1介於約30 μm與約120 μm之間的範圍內),但是包含鹼性化合物以及含有非質子溶劑及質子溶劑的非二甲亞碸溶劑的用於移除圖案化抗蝕劑層PR’的剝除溶液仍然具有良好的潤濕能力。因此,可確保隨後形成的封裝結構10的效能及品質。
在一些實施例中,以剝除溶液的總重量計,非質子溶劑的量為約20重量%到約70重量%,質子溶劑的量為約20重量%到約70重量%,且鹼性化合物的量為約0.5重量%到約5.5重量%。在某些實施例中,在鹼性化合物包括KOH的情况下,以剝除溶液的總重量計,KOH的量為約0.5重量%到約2.5重量%。在某些實施例中,在鹼性化合物包括TMAH的情况下,以剝除溶液的總重量計,TMAH的量為約0.5重量%到約3重量%。在某些實施例中,在非質子溶劑以約20重量%到約70重量%的量使用,質子溶劑以約20重量%到約70重量%的量使用,且鹼性化合物以約0.5重量%到約5.5重量%的量使用的情况下,則在剝除製程期間金屬圖案102的失敗率(例如,傾斜/塌陷百分比)可提高約35%。在一些實施例中,非質子溶劑的量與質子溶劑的量的比率介於約1:3.5到約3.5:1範圍內。具體來說,在非質子溶劑及質子溶劑以指定比率使用的情况下,則在剝除製程期間金屬圖案102的失敗率(例如,傾斜/塌陷百分比)可提高約35%。在某些實施例中,非質子溶劑的量與質子溶劑的量的比率可為1:1。在一些實施例中,剝除製程的製程時間介於約1分鐘到約180分鐘範圍內。在一些實施例中,剝除製程的製程溫度介於約25℃到約100℃範圍內。具體來說,在剝除製程的製程時間及製程溫度落在上述指定範圍內的情况下,則在剝除製程期間金屬圖案102的失敗率(例如,傾斜/塌陷百分比)可提高約35%。
返回參考圖1E及圖1F,在移除圖案化抗蝕劑層PR’之後,移除晶種層SL的未被多個金屬圖案102覆蓋的部分,以在緩衝層BL與多個金屬圖案102之間形成多個晶種層圖案104。也就是說,多個金屬圖案102用作用於部分地移除晶種層SL的罩幕。換句話說,多個晶種層圖案104源自晶種層SL的被多個金屬圖案102覆蓋的部分。在一些實施例中,晶種層SL通過蝕刻製程(例如等向性蝕刻製程或非等向性蝕刻製程)被部分地移除。
如上所述,在剝除製程期間,通過使用包含鹼性化合物以及含有非質子溶劑及質子溶劑的非二甲亞碸溶劑的剝除溶液,圖案化抗蝕劑層可被充分移除而不存在殘留物,同時多個金屬圖案102可保持實質上完整而不傾斜或塌陷。鑒於此,在移除圖案化抗蝕劑層PR’之後且通過使用多個金屬圖案102作為蝕刻罩幕而形成的多個晶種層圖案104的輪廓實質上相同於多個金屬圖案102的輪廓,如圖1F所示。也就是說,多個晶種層圖案104中的每一者的邊緣與對應的上覆金屬圖案102的邊緣實質上齊平。由於晶種層圖案104的輪廓相同於金屬圖案102的輪廓,因此可有效地消除由晶種層圖案及金屬圖案的形狀錯配引起的漏電問題,由此確保隨後形成的封裝結構10的效能及品質。在一些實施例中,在每個金屬圖案102具有圓形俯視形狀的情况下,每個晶種層圖案104被形成為具有圓形俯視形狀。然而,本公開不限於此。在一些替代實施例中,從俯視圖看,每個晶種層圖案104可表現為多邊形形狀或其他合適的形狀。
在一些實施例中,晶種層圖案104及金屬圖案102被統稱為導電穿孔100。如圖1F所示,多個導電穿孔100設置在緩衝層BL上。如上所述,在通過將包含鹼性化合物以及含有非質子溶劑及質子溶劑的非二甲亞碸溶劑的剝除溶液施加到圖案化抗蝕劑層PR’上來移除圖案化抗蝕劑層PR’之後,多個金屬圖案102可保持實質上完整,而不會傾斜或塌陷,由此通過使用多個金屬圖案102作為罩幕形成的多個導電穿孔100可被形成為實質上垂直地竪立在緩衝層BL上。也就是說,多個導電穿孔100可實質上沿著方向Z從緩衝層BL突出。換句話說,多個導電穿孔100沿著方向Z的延伸方向可具有小於1°的角度偏移。因此,導電穿孔100的製造良率顯著提高。在一些實施例中,大於或等於95%的導電穿孔100沒有相對於方向Z的角度偏移,且小於或等於5%的導電穿孔100具有小於1°的相對於方向Z的角度偏移。在一些替代實施例中,幾乎所有的導電穿孔100沒有相對於方向Z的角度偏移。
在一些實施例中,由於多個金屬圖案102以陣列形式形成(如圖2A所示),因此多個金屬圖案102作為其部分的多個導電穿孔100以陣列形式形成,如圖2B所示,圖2B是示出根據本公開一些實施例的圖1F的階段中的結構的一部分的示意性俯視圖。在一些實施例中,在方向Z上,每個導電穿孔100的高度Hc介於約15 μm與約360 μm之間的範圍內。在一些實施例中,在垂直於方向Z的方向X上,每個導電穿孔100的寬度Wc介於約5 μm與約120 μm之間的範圍內。在每個導電穿孔100具有圓形俯視形狀(如圖2B所示)的情况下,則寬度Wc可為直徑。在每個導電穿孔100從俯視圖看具有多邊形形狀的情况下,則寬度Wc可為最大尺寸。
在一些實施例中,每個導電穿孔100的縱橫比(即,高度Hc與寬度Wc的比率)大於約3,即,導電穿孔100被形成為具有高縱橫比。也就是說,通過在剝除製程中施加包含鹼性化合物以及含有非質子溶劑及質子溶劑的非二甲亞碸溶劑的剝除溶液,以提供具有高縱橫比而不傾斜或塌陷的金屬圖案102,可相應地形成具有高縱橫比的導電穿孔100。在某些實施例中,每個導電穿孔100的縱橫比介於大於約3到約15的範圍內。此外,在一些實施例中,兩個相鄰導電穿孔100的節距Pc介於約6 μm與約360 μm之間的範圍內。在某些實施例中,兩個相鄰導電穿孔100的節距Pc介於約30 μm與約120 μm之間的範圍內,即,導電穿孔100可被形成為具有高分佈密度。如上所述,由於即使金屬圖案102被佈置成具有高分佈密度,包含鹼性化合物以及含有非質子溶劑及質子溶劑的非二甲亞碸溶劑的用於移除圖案化抗蝕劑層PR’的剝除溶液仍具有良好的潤濕能力,因此可相應地形成具有高分佈密度且具有與金屬圖案102的輪廓相同的輪廓的導電穿孔100。因此,可確保隨後形成的封裝結構10的效能及品質。
參考圖1G,可拾取至少一個晶粒110並放置到緩衝層BL上。晶粒110例如包括半導體基底111、多個導電接墊112、鈍化層113、後鈍化層114、多個導電柱115及保護層116。詳細來說,晶粒110以晶粒110的半導體基底111貼合(或黏附)到緩衝層BL的方式放置在緩衝層BL上。在一些實施例中,晶粒110通過接合膜D貼合(或黏附)到緩衝層BL。在一些實施例中,接合膜D可為黏合膜,例如晶粒貼合膜(die attach film,DAF)。在一些替代實施例中,接合膜D可為用於熔融接合的任何材料。例如,接合膜D可為用於氧化物-氧化物熔融接合的氧化物系膜(例如,氧化矽膜)。
在一些實施例中,晶粒110可為邏輯晶粒(例如,中央處理器(central processing unit,CPU)、微控制器等)、記憶體晶粒(例如,動態隨機存取記憶體(dynamic random access memory,DRAM)晶粒、靜態隨機存取記憶體(static random access memory,SRAM)晶粒等)、電力管理晶粒(例如,電力管理積體電路(power management integrated circuit,PMIC)晶粒)、射頻(radio frequency,RF)晶粒、感測器晶粒、微機電系統(micro-electro-mechanical-system,MEMS)晶粒、訊號處理晶粒(例如,數位訊號處理(digital signal processing,DSP)晶粒)、前端晶粒(例如,類比前端(analog front-end,AFE)晶粒)等。在一些實施例中,多個導電接墊112設置在半導體基底111之上。鈍化層113形成在半導體基底111之上且具有部分地暴露出多個導電接墊112的多個接觸開口。半導體基底111可為矽基底,所述矽基底包括形成在所述矽基底中的主動組件(例如,電晶體等)及被動組件(例如,電阻器、電容器、電感器等)。導電接墊112可為鋁接墊、銅接墊或其他合適的金屬接墊。鈍化層113可為氧化矽層、氮化矽層、氮氧化矽層、或由其他合適的介電材料形成的介電層。此外,後鈍化層114形成在鈍化層113之上。後鈍化層114覆蓋鈍化層113且具有多個接觸開口。多個導電接墊112被後鈍化層114的多個接觸開口部分地暴露出。後鈍化層114可為聚醯亞胺(polyimide,PI)層、聚苯並噁唑(PBO)層或由其他合適的聚合物形成的介電層。此外,多個導電柱115被形成為延伸穿過後鈍化層114中的多個接觸開口,並機械及電耦合到對應的導電接墊112。在一些實施例中,導電柱115可為鍍銅柱。保護層116形成在後鈍化層114上以覆蓋多個導電柱115。保護層116的材料可為聚合物,例如PBO、聚醯亞胺、苯並環丁烯(BCB)等;氮化物,例如氮化矽等;氧化物,例如氧化矽等;或其組合。保護層116可例如通過旋轉塗佈、疊層、化學氣相沉積(chemical vapor deposition,CVD)等來形成。
在一些實施例中,在方向Z上,晶粒110具有比導電穿孔100的高度小的厚度,如圖1G所示。然而,本公開不限於此。在一些替代實施例中,在方向Z上,晶粒110的厚度可大於或實質上等於導電穿孔100的高度。如圖1G所示,晶粒110是在形成導電穿孔100之後被拾取並放置到緩衝層BL上。然而,本公開不限於此。在一些替代實施例中,可在形成導電穿孔100之前將一個或多個晶粒110拾取並放置到緩衝層BL上。在示例性實施例中,圖1G中僅示出一個晶粒110。然而,應注意,放置在緩衝層BL上的晶粒110的數目不限於此,且這可基於設計要求來調整。在一些實施例中,當多於一個晶粒110被放置在緩衝層BL上時,晶粒110可被佈置成陣列,且當晶粒110被佈置成陣列時,導電穿孔110可被分類成組。
參考圖1H,在緩衝層BL之上形成包封體120,以包封晶粒110及多個導電穿孔100。詳細來說,形成包封體120以填充晶粒110與多個導電穿孔100之間的間隙以及相鄰導電穿孔100之間的間隙,使得包封體120覆蓋晶粒110及多個導電穿孔100的側壁及圖示頂表面。也就是說,晶粒110及多個導電穿孔100嵌入在包封體120中,且不被顯露。從另一個方面看,包封體120可被稱為「間隙填充材料」。在一些實施例中,包封體120的材料可包括模製化合物、模製底部填充膠、樹脂(例如環氧樹脂)等。在一些替代實施例中,包封體120的材料可包括例如氮化矽等氮化物、例如氧化矽等氧化物、磷矽酸鹽玻璃(phosphosilicate glass,PSG)、硼矽酸鹽玻璃(borosilicate glass,BSG)、硼摻雜磷矽酸鹽玻璃(boron-doped phosphosilicate glass,BPSG)、其組合等。在又一替代實施例中,包封體120的材料可為有機材料(例如,環氧樹脂、聚醯亞胺、PBO等),或者無機及有機材料的混合物(例如,氧化矽及環氧樹脂的混合物等)。在一些實施例中,包封體120可通過模製製程(例如壓縮模製製程)來形成。在一些替代實施例中,包封體120可通過例如化學氣相沉積、高密度電漿化學氣相沉積(high-density plasma chemical vapor deposition,HDPCVD)或電漿增强化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)等合適的製作技術來形成。
參考圖1I,然後對包封體120、晶粒110及多個導電穿孔100執行平坦化製程,直到多個導電柱115的圖示頂表面及多個導電穿孔100的圖示頂表面被暴露出。在對包封體120執行平坦化製程之後,在緩衝層BL之上形成包封體120’。在一些實施例中,在平坦化製程之後,多個導電穿孔100、多個導電柱115、保護層116及包封體120’的圖示頂表面實質上共面。在一些實施例中,平坦化製程可為例如化學機械拋光(chemical-mechanical polish,CMP)、研磨製程等。在一些實施例中,在平坦化製程之後,可任選地執行清潔製程。例如,執行清潔製程以清潔及移除從平坦化製程產生的殘留物。然而,本公開不限於此,且平坦化製程可通過任何其他合適的方法來執行。導電穿孔100穿透包封體120’,且導電穿孔100被稱為積體扇出型穿孔。
參考圖1J,在平坦化製程之後,在包封體120’、多個導電穿孔100及晶粒110上形成重佈線層130。在一些實施例中,重佈線層130形成在多個導電穿孔100、多個導電柱115、保護層116及包封體120’的圖示頂表面上。也就是說,重佈線層130沿著載體C及晶粒110的堆疊方向(例如,方向Z)形成在包封體120’上。在一些實施例中,重佈線層130電連接到多個導電穿孔100,且通過多個導電柱115電連接到晶粒110。在一些實施例中,晶粒110通過重佈線層130電連接到多個導電穿孔100。
此外,在一些實施例中,形成重佈線層130包括交替地依序形成一個或多個介電層132及一個或多個導電層134。在某些實施例中,多個導電層134夾在多個介電層132之間。儘管此處示出三層導電層134及四層介電層132,但是本公開的範圍不受本公開的實施例限制。在其他實施例中,導電層134的數目及介電層132的數目可基於產品要求來調整。在一些實施例中,導電層134電連接到晶粒110的導電柱115。此外,導電層134電連接到導電穿孔100。
在一些實施例中,介電層132的材料可為PI、PBO、BCB、例如氮化矽等氮化物、例如氧化矽等氧化物、PSG、BSG、BPSG、其組合等,其可使用微影和/或蝕刻製程而被圖案化。在一些實施例中,介電層132的材料可通過例如旋塗、CVD、HDPCVD、PECVD、原子層沉積(atomic layer deposition,ALD)等合適的製作技術來形成。在一些實施例中,導電層134的材料可由通過電鍍或沉積形成的導電材料(例如鋁、鈦、銅、鎳、鎢和/或其合金)製成,其可使用微影及蝕刻製程來圖案化。在一些實施例中,導電層134可為圖案化銅層或其他合適的圖案化金屬層。
在形成重佈線層130之後,在多個導電層134的最頂層的被暴露的頂表面上設置多個導電接墊140。在某些實施例中,導電接墊140例如是用於球安裝的球下金屬(under-ball metallurgy,UBM)圖案。如圖1J所示,多個導電接墊140形成在重佈線層130上並電連接到重佈線層130。在一些實施例中,導電接墊140的材料可包括銅、鎳、鈦、鎢或其合金等,且可例如通過電鍍製程來形成。導電接墊140的數目在本公開中不受限制,且可基於設計佈局來選擇。在一些替代實施例中,可省略導電接墊140。換句話說,在後續步驟中形成的多個導電元件142(下文所述)可直接設置在重佈線層130上。
在形成多個導電接墊140之後,在多個導電接墊140上及重佈線層130之上設置多個導電元件142。在一些實施例中,多個導電元件142可通過植球製程和/或回焊製程或其他合適的形成方法設置在多個導電接墊140上。在一些實施例中,導電元件142可為球柵陣列(ball grid array,BGA)連接件、焊料球、金屬柱、受控塌陷芯片連接(controlled collapse chip connection,C4)凸塊、微凸塊、無電鍍鎳鈀浸金技術(electroless nickel-electroless palladium-immersion gold technique,ENEPIG)形成的凸塊等。在一些實施例中,多個導電元件142通過多個導電接墊140連接到重佈線層130。在某些實施例中,多個導電元件142中的一些可通過重佈線層130電連接到晶粒110。此外,多個導電元件142中的一些可通過重佈線層130電連接到多個導電穿孔100。導電元件142的數目不限於本公開,且可基於導電接墊140的數目來指定及選擇。導電元件142的材料例如可包括導電材料,例如焊料、銅、鋁、金、鎳、銀、鈀、錫或其組合。在一個實施例中,導電元件142的材料例如可為無焊料的。
參考圖1K,在形成重佈線層130並在其上放置多個導電元件142之後,圖1J所示的結構可被顛倒並貼合到由框架F支撑的膠帶T(例如,切分膠帶(dicing tape))。在一些實施例中,多個導電元件142與膠帶T接觸。如圖1K所示,載體C被剝離並與緩衝層BL分離。在一些實施例中,剝離製程包括將例如雷射或紫外光等光投射在剝離層DB(例如,LTHC釋放層)上,使得載體C可容易地與剝離層DB一起移除。在剝離步驟期間,在剝離載體C及剝離層DB之前,使用膠帶T來固定封裝結構。在剝離製程之後,緩衝層BL的背側表面(即,圖1K中所示的頂表面)被顯露或暴露。
參考圖1K及圖1L,在剝離製程之後,沿著切分線DL執行切分製程,以將圖1K所示的整個結構切割(即,切透緩衝層BL、包封體120’及重佈線層130)成多個封裝結構10。封裝結構10被稱為積體扇出型(integrated fan-out,InFO)封裝。在示例性實施例中,所述切分製程是包括機械刀片鋸切或雷射切割的晶圓切分製程。在隨後的製程中,分離的封裝結構10可例如基於要求設置在電路基底上或其他組件上。
儘管將所述方法的步驟示出並闡述為一系列的動作或事件,但將知,這類動作或事件的所示出的排序不應以限制意義進行解釋。另外,並不要求進行所有所示出的製程或步驟來實施本公開的一個或多個實施例。
圖4是根據本公開一些替代實施例的封裝結構的示意性剖視圖。與先前所述的元件相似或實質上相同的元件將使用相同的參考編號,且本文中將不重複相同元件的某些細節或說明(例如,材料、形成製程、定位配置等)。參考圖4,在製作第一封裝(例如圖1L所示的封裝結構10)之後,可將第二封裝200堆疊在封裝結構10(第一封裝)上,以形成疊層封裝(package-on-package,PoP)結構20。如圖4所示,第二封裝200電連接到封裝結構10(第一封裝)的多個導電穿孔100。在一些實施例中,第二封裝200具有基底202、多個半導體晶粒204、多個接合線206、多個導電接墊208、多個導電接墊212及包封體210。在一些實施例中,多個半導體晶粒204安裝在圖4所示的基底202的圖示頂表面上。在一些實施例中,多個接合線206用於提供多個半導體晶粒204與多個導電接墊208(例如接合接墊)之間的電連接。在一些實施例中,包封體210被形成為包封及保護多個半導體晶粒204及多個接合線206。在一些實施例中,嵌入在基底202中的多個內連線(未示出)或多個導電穿孔(未示出)可用於提供多個導電接墊208與多個導電接墊212(例如接合接墊)之間的電連接。在一些實施例中,多個導電接墊208及多個導電接墊212分別設置在基底202的兩個相對的表面上,如圖4所示。在某些實施例中,多個導電接墊212通過多個內連線(未示出)或多個導電穿孔(未示出)電連接到多個半導體晶粒204。在一些實施例中,封裝結構200的多個導電接墊212電連接到多個導電元件214。此外,多個導電元件214電連接到封裝結構10(第一封裝)的多個導電穿孔100。在一些實施例中,更提供底部填充膠216來填充封裝結構10(第一封裝)和第二封裝200之間的間隙,以保護多個導電元件214。由於底部填充膠216,第二封裝200與封裝結構10(第一封裝)之間的接合强度增强,由此提高圖4所示封裝結構的可靠性。在將第二封裝200堆疊在封裝結構10(第一封裝)上並提供其之間的電連接之後,可製作疊層封裝結構20。
圖5是根據本公開一些替代實施例的封裝結構的示意性剖視圖。與先前所述的元件相似或實質上相同的元件將使用相同的參考編號,且本文中將不重複相同元件的某些細節或說明(例如,材料、形成製程、定位配置等)。參考圖5,在一些實施例中,提供封裝組件300,其中圖4所示疊層封裝結構20接合在封裝組件300上,以形成具有堆疊結構的封裝結構30。在一些實施例中,封裝組件300包括多個導電接墊302。在一些實施例中,封裝組件300是封裝基底,其可為無芯基底或具有芯的基底。在一些替代實施例中,封裝組件300是印刷電路板或封裝。在一些實施例中,如圖5所示,疊層封裝結構20中的封裝結構10的多個導電元件142接合到多個導電接墊302(例如接合接墊),以提供封裝組件300與疊層封裝結構20之間的電連接。也就是說,疊層封裝結構20物理及電連接到封裝組件300。在一些實施例中,可施加底部填充膠(未示出)以填充疊層封裝結構20與封裝組件300之間的間隙,從而保護多個導電元件142及多個導電接墊140,這會增强疊層封裝結構20與封裝組件300之間的接合强度;由此提高圖5所示封裝結構的可靠性。
圖6是根據本公開一些替代實施例的封裝結構的示意性剖視圖。圖6中所示的封裝結構40類似於圖1L中所示的封裝結構10,因此相同的參考編號用於指代相同或相似的部分,並且此處將省略其詳細說明。下面將闡述圖6所示的封裝結構40與圖1L所示的封裝結構10之間的差異。
參考圖6,在封裝結構40中,多個導電柱400設置在多個導電層134的最頂層的被暴露的頂表面上。在一些實施例中,導電柱400的材料例如可包括導電材料,例如銅、鋁、鈦、鎳、鎢、錫、焊料或其組合。在某些實施例中,導電柱400可為鍍銅柱。此外,參考圖6及圖1L,導電柱400用於代替導電接墊140,以提供導電元件142與重佈線層130之間的電連接。
在圖1L所示的封裝結構10中,僅一個晶粒110設置在多個導電穿孔100之間。然而,本公開不限於此。在一些替代實施例中,可在多個導電穿孔100之間設置多於一個晶粒110。在下文中,將參考圖7闡述其他實施例。
圖7是根據本公開一些替代實施例的封裝結構的示意性剖視圖。圖7中所示的封裝結構50類似於圖1L中所示的封裝結構10,因此相同的參考編號用於指代相同或相似的部分,並且此處將省略其詳細說明。參考圖7及圖1L,圖7所示的封裝結構50與圖1L所示的封裝結構10之間的差異在於,兩個晶粒110設置在封裝結構50中的多個導電穿孔100之間。然而,本公開不限於此。在一些替代實施例中,可基於設計要求形成更多數目的晶粒110。
圖8是根據本公開一些替代實施例的封裝結構的示意性剖視圖。圖8中所示的封裝結構60類似於圖1L中所示的封裝結構10,因此相同的參考編號用於指代相同或相似的部分,並且此處將省略其詳細說明。下面將闡述圖8所示的封裝結構60與圖1L所示的封裝結構10之間的差異。
參考圖8,封裝結構60中包括另一個重佈線層600。在一些實施例中,如圖8所示,重佈線層600及重佈線層130分別設置在包封體120’的兩個相對的表面上。也就是說,晶粒110設置在重佈線層600與重佈線層130之間。在一些實施例中,如圖8所示,形成重佈線層600包括交替地依序形成一個或多個介電層602及一個或多個導電層604。儘管圖8示出重佈線層600包括兩個介電層602及一個導電層604,其中導電層604夾在兩個介電層602之間,但是本公開不限於此。在其他實施例中,介電層602的數目及導電層604的數目可基於產品要求來調整。在一些實施例中,多個導電穿孔100電連接到重佈線層600的導電層604。也就是說,在封裝結構60中,多個導電穿孔100可用於提供重佈線層130與重佈線層600之間的電連接。在一些實施例中,重佈線層600的介電層602及導電層604的材料類似於針對重佈線層130提到的介電層132及導電層134的材料。因此,此處將省略介電層602及導電層604的詳細說明。此外,參考圖8及圖1L兩者,重佈線層600設置在包封體120’上,以代替緩衝層BL。
圖9是根據本公開一些替代實施例的封裝結構的示意性剖視圖。圖9中所示的封裝結構70類似於圖1L中所示的封裝結構10,因此相同的參考編號用於指代相同或相似的部分,並且此處將省略其詳細說明。下面將闡述圖9所示的封裝結構70與圖1L所示的封裝結構10之間的差異。
參考圖9及圖1L,封裝結構70與封裝結構10之間的主要區別在於晶粒700更包括在封裝結構70中。在示例性實施例中,晶粒700包括半導體基底701、多個導電接墊702、鈍化層703、後鈍化層704、多個導電柱705及保護層706。晶粒700的這些元件可類似於晶粒110的半導體基底111、多個導電接墊112、鈍化層113、後鈍化層114、多個導電柱115及保護層116,因此晶粒700的所述元件的詳細說明可參考晶粒110的該些元件的詳細說明。簡單來說,多個導電接墊702位於半導體基底701上,鈍化層703及後鈍化層704依序位於半導體基底701及多個導電接墊702上,保護層706位於後鈍化層704上,多個導電柱705嵌入後鈍化層704及保護層706中,且多個導電柱705與多個導電接墊702電連接。如圖9所示,晶粒700沿著方向Z位於晶粒110之上。
在一些實施例中,如圖9所示,形成包封體710來包封晶粒700。包封體710可類似於包封體120’,因此包封體710的詳細說明可參考包封體120’的詳細說明。在一些實施例中,如圖9所示,多個導電穿孔720嵌入包封體710內。導電穿孔720可類似於導電穿孔100,因此導電穿孔720的詳細說明可參考導電穿孔100的詳細說明。簡單來說,如上所述,通過在剝除製程中施加包含鹼性化合物以及含有非質子溶劑及質子溶劑的非二甲亞碸溶劑的剝除溶液,具有高縱橫比的導電穿孔720可被形成為具有顯著提高的製造良率。此外,如上所述,通過在剝除製程中施加包含鹼性化合物以及含有非質子溶劑及質子溶劑的非二甲亞碸溶劑的剝除溶液,導電穿孔720可被形成為具有高分佈密度。
在一些實施例中,如圖9所示,包封體710與包封體120’之間設置有內連層730。在一些實施例中,內連層730包括層間介電層732及多個導電層734。在一些實施例中,多個導電層734嵌入層間介電層732中。為簡單起見,在圖9中,層間介電層732被示為單一龐大(bulky)的層,但是應理解,層間介電層732可由多個介電層構成,且層間介電層732中的介電層的數目可根據產品要求來調整。此外,多個導電層734及層間介電層732的多個介電層可交替堆疊。應注意,圖9中所示的導電層734的數目僅是說明,並且本公開不受限制。在一些替代實施例中,導電層734的數目可基於產品要求來調整。
在一些實施例中,層間介電層732的材料可為PI、PBO、BCB、例如氮化矽等氮化物、例如氧化矽等氧化物、PSG、BSG、BPSG、其組合等,其可使用微影和/或蝕刻製程而被圖案化。在一些實施例中,層間介電層732的材料可通過例如旋塗、CVD、HDPCVD、PECVD、ALD等合適的製作技術來形成。在一些實施例中,導電層734的材料可由通過電鍍或沉積形成的導電材料(例如鋁、鈦、銅、鎳、鎢和/或其合金)製成,其可使用微影及蝕刻製程來圖案化。在一些實施例中,導電層734可為圖案化銅層或其他適合的圖案化金屬層。
在一些實施例中,如圖9所示,內連層730電連接到多個導電穿孔100、晶粒110的多個導電柱115及多個導電穿孔720。在一些實施例中,晶粒110通過內連層730電連接到多個導電穿孔100。在一些實施例中,如圖9所示,晶粒700通過接合膜D1貼合(或黏附)到內連層730中的層間介電層732。在一些實施例中,接合膜D1可為黏合膜,例如晶粒貼合膜(DAF)。在一些替代實施例中,接合膜D1可為用於熔融接合的任何材料。例如,接合膜D1可為用於氧化物-氧化物熔融接合的氧化物系膜(例如,氧化矽膜)。在一些實施例中,如圖9所示,重佈線層130電連接到晶粒700的多個導電柱705及多個導電穿孔720。此外,在一些實施例中,晶粒110與晶粒700可具有不同的大小(例如,不同的高度和/或表面積)。在一些替代實施例中,晶粒110與晶粒700可具有相同的大小(例如,相同的高度和/或表面積)。
圖10是根據本公開一些替代實施例的封裝結構的示意性剖視圖。圖10中所示的封裝結構80類似於圖1L中所示的封裝結構10,因此相同的參考編號用於指代相同或相似的部分,並且此處將省略其詳細說明。下面將闡述圖10所示的封裝結構80與圖1L所示的封裝結構10之間的差異。
參考圖10及圖1L,封裝結構80與封裝結構10之間的主要區別在於從封裝結構80中省略了晶粒110。詳細來說,參考圖10及圖1L,封裝800被包封體120’包封以代替晶粒110。在示例性實施例中,封裝800包括第一晶粒810、第二晶粒820、包封體830及多個導電穿孔840。如圖10所示,第二晶粒820沿著方向Z堆疊在第一晶粒810上。換句話說,多個晶粒(即第一晶粒810、第二晶粒820)被積體到單個封裝800中。因此,封裝800可被稱為「積體電路上系統(system on integrated circuit,SOIC)封裝」在一些實施例中,如圖10所示,封裝800通過接合膜D2貼合(或黏附)到緩衝層BL。在一些實施例中,接合膜D2可為黏合膜,例如晶粒貼合膜(DAF)。在一些替代實施例中,接合膜D2可為用於熔融接合的任何材料。例如,接合膜D2可為用於氧化物-氧化物熔融接合的氧化物系膜(例如,氧化矽膜)。
在一些實施例中,第一晶粒810可包括半導體基底811、多個導電接墊812、鈍化層813、後鈍化層814、導電層815及介電層816,如圖10所示。第一晶粒810的半導體基底811、導電接墊812、鈍化層813及後鈍化層814可類似於晶粒110的半導體基底111、導電接墊112、鈍化層113及後鈍化層114,因此所述元件的詳細說明可參考晶粒110的該些元件的詳細說明。簡單來說,多個導電接墊812位於半導體基底811上,且鈍化層813及後鈍化層814依序位於半導體基底811及多個導電接墊812上。在一些實施例中,如圖10所示,導電層815設置在後鈍化層814上,並通過後鈍化層814的接觸開口與多個導電接墊812電連接。在一些實施例中,導電層815的材料例如可包括導電材料,例如銅、鋁、鈦、鎳、鎢、錫、焊料或其組合。在一些實施例中,導電層815可通過例如電鍍、沉積和/或微影及蝕刻來形成。在一些實施例中,如圖10所示,介電層816設置在導電層815上。在一些實施例中,介電層816的材料可為PI、PBO、BCB、例如氮化矽等氮化物、例如氧化矽等氧化物、PSG、BSG、BPSG、其組合等,其可使用微影和/或蝕刻製程而被圖案化。在一些實施例中,介電層816的材料可通過例如旋塗、CVD、HDPCVD、PECVD、原子層沉積(ALD)等合適的製作技術來形成。介電層816的與接觸導電層815的圖示底表面相對的圖示頂表面可被整平,且可具有高平面度。
在一些實施例中,第二晶粒820可包括半導體基底821、多個導電接墊822、鈍化層823、後鈍化層824、多個導電柱825及保護層826,如圖10所示。第二晶粒820的這些元件可類似於晶粒110的半導體基底111、多個導電接墊112、鈍化層113、後鈍化層114、多個導電柱115及保護層116,因此第二晶粒820的所述元件的詳細說明可參考晶粒110的該些元件的詳細說明。簡單來說,多個導電接墊822位於半導體基底821上,鈍化層823及後鈍化層824依序位於半導體基底821及多個導電接墊822上,保護層826位於後鈍化層824上,多個導電柱825嵌入後鈍化層824及保護層826中,且多個導電柱825與多個導電接墊822電連接。此外,在一些實施例中,如圖10所示,第二晶粒820通過接合膜D3貼合(或黏附)到第一晶粒810上的介電層816。在一些實施例中,接合膜D3可為黏合膜,例如晶粒貼合膜(DAF)。在一些替代實施例中,接合膜D3可為用於熔融接合的任何材料。例如,接合膜D3可為用於氧化物-氧化物熔融接合的氧化物系膜(例如,氧化矽膜)。
在一些實施例中,如圖10所示,形成包封體830來包封晶粒820。包封體830可類似於包封體120’,因此包封體830的詳細說明可參考包封體120’的詳細說明。在一些實施例中,如圖10所示,多個導電穿孔840嵌入包封體830內。在一些實施例中,每個導電穿孔840被形成為具有圓形俯視形狀。然而,本公開不限於此。在一些替代實施例中,從俯視圖看,每個導電穿孔840可表現為多邊形形狀或其他合適的形狀。在一些實施例中,在方向Z上,每個導電穿孔840的高度H
2介於約15 μm與約360 μm之間的範圍內。在一些實施例中,在垂直於方向Z的方向X上,每個導電穿孔840的寬度W
2介於約5 μm與約120 μm之間的範圍內。在每個導電穿孔840具有圓形俯視形狀的情况下,則寬度W
2可為直徑。在每個導電穿孔840從俯視圖看具有多邊形形狀的情况下,則寬度W
2可為最大尺寸。在一些實施例中,每個導電穿孔840的縱橫比(即,高度H
2與寬度W
2的比率)介於大於約3到約15的範圍內。根據關於圖1A到圖1L及圖3A到圖3E的說明,可推斷出上面結合圖3A到圖3E闡述的方法可應用於包括導電穿孔(甚至具有高縱橫比的導電穿孔)的任何封裝結構的製造製程。因此,本領域中的技術人員應理解,以上結合圖3A到圖3E闡述的方法可應用於製造導電穿孔840,由此無論導電穿孔840是否具有高縱橫比,導電穿孔840都可被形成為具有顯著提高的製造良率。然而,本公開不限於此。
在一些實施例中,如圖10所示,多個導電穿孔840電連接到第一晶粒810的導電層815。在一些實施例中,如圖10所示,重佈線層130電連接到多個導電穿孔100、第二晶粒820的多個導電柱825及多個導電穿孔840。在一些實施例中,第二晶粒820通過重佈線層130及多個導電穿孔840電連接到第一晶粒810。在一些實施例中,封裝800通過重佈線層130電連接到多個導電穿孔100。
圖11是根據本公開一些替代實施例的封裝結構的示意性剖視圖。
參考圖11,封裝結構90可包括封裝P、載體晶粒950、底部填充膠960、包封體970、重佈線層980、多個導電接墊990及多個導電元件992。在示例性實施例中,封裝P包括層級(tier)結構T
1、層級結構T
2、層級結構T
3、層級結構T
4及多個導電端子940。儘管圖11示出封裝P包括四個層級結構(即,層級結構T
1到T
4),但是本公開不限於此。在其他實施例中,封裝P中的層級結構的數目可基於產品要求來調整。
如圖11所示,層級結構T
1、層級結構T
2、層級結構T
3及層級結構T
4中的每一者包括晶粒900、包封體910及重佈線層930。此外,如圖11所示,層級結構T
1、層級結構T
2、層級結構T
3及層級結構T
4中的每一者包括多個導電穿孔920。在一些實施例中,如圖11所示,每個晶粒900可包括半導體基底901、多個導電柱905及保護層906。晶粒900的這些元件可類似於晶粒110的半導體基底111、多個導電柱115及保護層116,因此晶粒900的所述元件的詳細說明可參考晶粒110的該些元件的詳細說明。在一些實施例中,每個晶粒900更可包括內連線結構(未示出)、多個導電接墊(未示出)、鈍化層(未示出)及後鈍化層(未示出)。在一些實施例中,每個晶粒900可為記憶體晶粒(例如,DRAM晶粒、SRAM晶粒、同步動態隨機存取記憶體(synchronous dynamic random access memory,SDRAM)、反及(NAND)閃存等)。儘管圖11示出層級結構T
1、層級結構T
2、層級結構T
3及層級結構T
4中的每一者包括兩個晶粒900,但是本公開不限於此。在其他實施例中,包括在層級結構中的晶粒900的數目可基於產品要求來調整。此外,如圖11所示,層級結構T
1包括兩個分離的晶粒900。然而,本公開不限於此。在一些替代實施例中,層級結構T
1可包括單個晶粒900。
在一些實施例中,如圖11所示,在層級結構T
1、層級結構T
2、層級結構T
3及層級結構T
4中的每一者中,形成包封體910來包封晶粒900。包封體910可類似於包封體120’,因此包封體910的詳細說明可參考包封體120’的詳細說明。
在一些實施例中,如圖11所示,在層級結構T
2、層級結構T
3及層級結構T
4中的每一者中,多個導電穿孔920嵌入包封體910內。在一些實施例中,每個導電穿孔920被形成為具有圓形俯視形狀。然而,本公開不限於此。在一些替代實施例中,從俯視圖看,每個導電穿孔920可表現為多邊形形狀或其他合適的形狀。在一些實施例中,在方向Z上,每個導電穿孔920的高度H
3介於約15 μm與約360 μm之間的範圍內。在一些實施例中,在垂直於方向Z的方向X上,每個導電穿孔920的寬度W
3介於約5 μm與約120 μm之間的範圍內。在每個導電穿孔920具有圓形俯視形狀的情况下,則寬度W
3可為直徑。在每個導電穿孔920從俯視圖看具有多邊形形狀的情况下,則寬度W
3可為最大尺寸。在一些實施例中,每個導電穿孔920的縱橫比(即,高度H
3與寬度W
3的比率)大於約3,即,導電穿孔920被形成為具有高縱橫比。根據關於圖1A到圖1L及圖3A到圖3E的說明,可推斷出上面結合圖3A到圖3E闡述的方法可應用於包括具有高縱橫比的導電穿孔的任何封裝結構的製造製程。因此,本領域中的技術人員應理解,以上結合圖3A到圖3E闡述的方法可應用於製造導電穿孔920,由此具有高縱橫比的導電穿孔920可被形成為具有顯著提高的製造良率。
在一些實施例中,如圖11所示,在層級結構T
1、層級結構T
2、層級結構T
3及層級結構T
4中的每一者中,重佈線層930形成在包封體910及多個晶粒900上。在示例性實施例中,重佈線層930包括介電層932及多個導電層934。重佈線層930的這些元件可類似於重佈線層130的介電層132及導電層134,因此重佈線層930的所述元件的詳細說明可參考對重佈線層130的該些元件的詳細說明。為簡單起見,在圖11中,介電層932被示為單一龐大的層,但是應理解,介電層932可由多個介電層構成,且介電層932中的介電層的數目可根據產品要求來調整。此外,多個導電層934及介電層932的多個介電層可交替堆疊。應注意,圖11中所示的導電層934的數目僅是說明,並且本公開不受限制。在一些替代實施例中,導電層934的數目可基於產品要求來調整。
在一些實施例中,如圖11所示,層級結構T
1的重佈線層930電連接到層級結構T
1的多個晶粒900及層級結構T
2的多個導電穿孔920;層級結構T
2的重佈線層930電連接到層級結構T
2的多個晶粒900、層級結構T
2的多個導電穿孔920及層級結構T
3的多個導電穿孔920;層級結構T
3的重佈線層930電連接到層級結構T
3的多個晶粒900、層級結構T
3的多個導電穿孔920及層級結構T
4的多個導電穿孔920;層級結構T
4的重佈線層930電連接到層級結構T
4的多個晶粒900及層級結構T
4的多個導電穿孔920。在一些實施例中,如圖11所示,層級結構T
2中的每個晶粒900通過接合膜D4貼合(或黏附)到層級結構T
1的重佈線層930;層級結構T
3中的每個晶粒900通過接合膜D5貼合(或黏附)到層級結構T
2的重佈線層930;層級結構T
4中的每個晶粒900通過接合膜D6貼合(或黏附)到層級結構T
3的重佈線層930。在一些實施例中,接合膜D4、接合膜D5及接合膜D6中的每一者可為黏合膜,例如晶粒貼合膜(DAF)。在一些替代實施例中,接合膜D4、接合膜D5及接合膜D6中的每一者可為用於熔融接合的任何材料。例如,接合膜D4、接合膜D5及接合膜D6中的每一者可為用於氧化物-氧化物熔融接合的氧化物系膜(例如,氧化矽膜)。
在一些實施例中,如圖11所示,多個導電端子940形成在層級結構T
4中的重佈線層930的被暴露的表面處。導電端子940可通過使用例如濺鍍、印刷、鍍覆、沉積等來形成。導電端子940可由導電材料(包括銅、鋁、金、鎳、銀、鈀、錫、焊料、金屬合金等或其組合)來形成。在示例性實施例中,多個導電端子940中的每一者包括凸塊942及形成在凸塊942上的金屬頂蓋944,如圖11所示。凸塊942可為微凸塊、金屬柱、ENEPIG形成的凸塊、C4凸塊、BGA凸塊等。在凸塊942是微凸塊的實施例中,兩個相鄰凸塊942之間的凸塊節距介於約20 μm到約140 μm的範圍內。凸塊942可為無焊料的,且可具有實質上垂直的側壁。在一些實施例中,金屬頂蓋944通過例如鍍覆、印刷等形成。例如,金屬頂蓋944的材料包括鎳、錫、錫-鉛、金、銀、鈀、鎳-鈀-金、鎳-金等,或者這些的任意組合。
在一些實施例中,載體晶粒950可為邏輯晶粒(例如,CPU、微控制器、系統芯片(system-on-a-chip,SoC)、圖形處理單元(graphics processing unit,GPU)等)。在一些實施例中,載體晶粒950可用於為層級結構T
1到T
4中的晶粒900提供控制功能。在示例性實施例中,載體晶粒950包括半導體基底952、多個導電穿孔954及多個導電接墊956。半導體基底952可類似於晶粒110的半導體基底111,因此半導體基底952的詳細說明可參考半導體基底111的詳細說明。如圖11所示,多個導電穿孔954穿透半導體基底952。多個導電穿孔954可通過以下步驟形成。首先,通過例如蝕刻、銑削、雷射技術或其組合在半導體基底952中形成多個開口。然後,可通過使用例如氧化技術在多個開口中形成薄介電材料。然後,可在半導體基底952之上及多個開口中共形地沉積阻擋層。阻擋層的材料可包括氮化物或氮氧化物,例如氮化鈦、氮氧化鈦、氮化鉭、氮氧化鉭、氮化鎢或其組合。接下來,可在阻擋層之上及多個開口中沉積導電材料。導電材料可通過電化學鍍覆製程、CVD、ALD、PVD或其組合來形成。導電材料的實例是銅、鎢、鋁、銀、金或其組合。之後,通過例如CMP從半導體基底952移除多個開口外部的導電材料及阻擋層。因此,導電穿孔954可包含導電材料及導電材料與半導體基底952之間的阻擋層。
在一些實施例中,如圖11所示,封裝P的多個導電端子940通過倒裝芯片接合(flip-chip bonding)物理連接載體晶粒950的多個導電接墊956(例如接合接墊),以提供封裝P與載體晶粒950之間的電連接。也就是說,封裝P通過導電端子940及導電接墊956物理及電連接到載體晶粒950。在一些實施例中,如圖11所示,導電穿孔954電連接到導電接墊956。
在一些實施例中,如圖11所示,提供底部填充膠960以填充封裝P與載體晶粒950之間的間隙。如圖11所示,底部填充膠960可沿著封裝P的側壁向上延伸。由於底部填充膠960,封裝P與載體晶粒950之間的接合强度增强,由此提高圖11所示的封裝結構90的可靠性。在一些實施例中,如圖11所示,形成包封體970來包封封裝P及底部填充膠960。包封體970可類似於包封體120’,因此包封體970的詳細說明可參考包封體120’的詳細說明。
在一些實施例中,如圖11所示,重佈線層980形成在載體晶粒950的半導體基底952上且與封裝p相對。重佈線層980可以類似於重佈線層130的方式形成,因此重佈線層980的詳細說明可參考重佈線層130的詳細說明。在一些實施例中,如圖11所示,多個導電接墊990及多個導電元件992形成在重佈線層980上且與載體晶粒950相對。導電接墊990及導電元件992可類似於導電接墊140及導電元件142,因此導電接墊990及導電元件992的詳細說明可參考導電接墊140及導電元件142的詳細說明。在一些實施例中,重佈線層980用於提供導電接墊990與導電穿孔954之間的電連接。
根據本公開的一些實施例,提供一種包括以下步驟的移除抗蝕劑層的方法。在材料層上形成圖案化抗蝕劑層。對所述圖案化抗蝕劑層施加剝除溶液以溶解所述圖案化抗蝕劑層而不溶解所述材料層,其中所述剝除溶液包含非二甲亞碸溶劑及鹼性化合物,所述非二甲亞碸溶劑包含非質子溶劑及質子溶劑。
根據本公開的替代性實施例,提供一種包括以下步驟的製造半導體結構的方法。形成晶種層。在所述晶種層上形成圖案化罩幕層,其中所述圖案化罩幕層具有暴露出所述晶種層的多個開口。在所述多個開口中形成多個金屬圖案。通過施加剝除溶液以使所述圖案化罩幕層斷裂成碎片並將所述圖案化罩幕層的所述碎片溶解在所述剝除溶液中,對所述圖案化罩幕層執行剝除製程,其中所述剝除溶液包含非二甲亞碸溶劑及鹼性化合物,所述非二甲亞碸溶劑包含非質子溶劑及質子溶劑。
根據本公開的又一些替代性實施例,提供一種包括以下步驟的製造半導體結構的方法。在載體上形成多個導電穿孔。在所述載體上設置晶粒。用包封體在側向上包封所述晶粒及所述多個導電穿孔,其中在所述載體上形成所述多個導電穿孔包括:在所述載體上依序形成晶種層及抗蝕劑層;對所述抗蝕劑層進行圖案化以形成暴露出所述晶種層的多個開口;在所述多個開口中形成多個金屬圖案;以及用剝除溶液執行剝除製程以移除經圖案化的所述抗蝕劑層,其中所述剝除溶液包含非二甲亞碸溶劑及鹼性化合物,所述非二甲亞碸溶劑包含非質子溶劑及質子溶劑。
以上概述了若干實施例的特徵,以使所屬領域中的技術人員可更好地理解本公開的各個方面。所屬領域中的技術人員應理解,其可容易地使用本公開作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的和/或實現與本文中所介紹的實施例相同的優點。所屬領域中的技術人員更應認識到,此種等效構造並不背離本公開的精神及範圍,而且他們可在不背離本公開的精神及範圍的條件下對其作出各種改變、代替及變更。
10、30、40、50、60、70、80、90:封裝結構
20:疊層封裝(PoP)結構
100、720、840、920、954:導電穿孔
102:金屬圖案
104:晶種層圖案
110、700、900:晶粒
111、701、811、821、901、952:半導體基底
112、140、208、212、302、702、812、822、956、990:導電接墊
113、703、813、823:鈍化層
114、704、814、824:後鈍化層
115、400、705、825、905:導電柱
116、706、826、906:保護層
120、120’、210、710、830、910、970:包封體
130、600、930、980:重佈線層
132、602、816、932:介電層
134、604、734、815、934:導電層
142、214、992:導電元件
200:第二封裝
202:基底
204:半導體晶粒
206:接合線
216、960:底部填充膠
300:封裝組件
730:內連層
732:層間介電層
800、P:封裝
810:第一晶粒
820:第二晶粒
940:導電端子
942:凸塊
944:金屬頂蓋
950:載體晶粒
A:穿孔密集區
B:穿孔稀疏區
BL:緩衝層
C:載體
D、D1、D2、D3、D4、D5、D6:接合膜
DB:剝離層
DL:切分線
F:框架
H
1、H
2、H
3、Hc:高度
O:開口
P
1、Pc:節距
PR:抗蝕劑層
PR’:圖案化抗蝕劑層
SL:晶種層
T:膠帶
T
1、T
2、T
3、T
4:層級結構
W
1、W
2、W
3、Wc:寬度
X、Z:方向
接合附圖閱讀以下詳細說明,會最好地理解本公開的各個方面。應注意,根據本行業中的標準慣例,各種特徵並非按比例繪製。事實上,為論述清晰起見,可任意增大或減小各種特徵的尺寸。
圖1A到圖1L是根據本公開一些實施例的製造封裝結構的方法中的各個階段的示意性剖視圖。
圖2A是示出根據本公開一些實施例的圖1E的階段中的結構的一部分的示意性俯視圖。
圖2B是示出根據本公開一些實施例的圖1F的階段中的結構的一部分的示意性俯視圖。
圖3A到圖3E是根據本公開一些實施例的圖1D中的圖案化抗蝕劑層的剝除製程中的各個步驟的示意性剖視圖。
圖4是根據本公開一些替代實施例的封裝結構的示意性剖視圖。
圖5是根據本公開一些替代實施例的封裝結構的示意性剖視圖。
圖6是根據本公開一些替代實施例的封裝結構的示意性剖視圖。
圖7是根據本公開一些替代實施例的封裝結構的示意性剖視圖。
圖8是根據本公開一些替代實施例的封裝結構的示意性剖視圖。
圖9是根據本公開一些替代實施例的封裝結構的示意性剖視圖。
圖10是根據本公開一些替代實施例的封裝結構的示意性剖視圖。
圖11是根據本公開一些替代實施例的封裝結構的示意性剖視圖。
102:金屬圖案
BL:緩衝層
C:載體
DB:剝離層
SL:晶種層
PR’:圖案化抗蝕劑層
Claims (20)
- 一種移除抗蝕劑層的方法,包括: 在材料層上形成圖案化抗蝕劑層;以及 對所述圖案化抗蝕劑層施加剝除溶液以溶解所述圖案化抗蝕劑層而不溶解所述材料層,其中所述剝除溶液包含非二甲亞碸溶劑及鹼性化合物,所述非二甲亞碸溶劑包含非質子溶劑及質子溶劑。
- 如請求項1所述的移除抗蝕劑層的方法,其中所述非質子溶劑包括N-甲基吡咯烷酮(NMP)、四氫呋喃(THF)、二甲基甲醯胺(DMF)、乙腈(MeCN)或二氯甲烷(DCM)。
- 如請求項1所述的移除抗蝕劑層的方法,其中所述質子溶劑包括烷醇胺溶劑。
- 如請求項1所述的移除抗蝕劑層的方法,其中所述鹼性化合物包括四甲基氫氧化銨(TMAH)、氫氧化鉀(KOH)、氫氧化鈉(NaOH)或其組合。
- 如請求項1所述的移除抗蝕劑層的方法,其中以所述剝除溶液的總重量計,所述非質子溶劑的量為20重量%到70重量%,所述質子溶劑的量為20重量%到70重量%,所述鹼性化合物的量為0.5重量%到5.5重量%。
- 如請求項1所述的移除抗蝕劑層的方法,其中所述非質子溶劑的量與所述質子溶劑的量的比率介於1:3.5到3.5:1範圍內。
- 一種製造半導體結構的方法,包括: 形成晶種層; 在所述晶種層上形成圖案化罩幕層,其中所述圖案化罩幕層具有暴露出所述晶種層的多個開口; 在所述多個開口中形成多個金屬圖案;以及 通過施加剝除溶液以使所述圖案化罩幕層斷裂成碎片並將所述圖案化罩幕層的所述碎片溶解在所述剝除溶液中,對所述圖案化罩幕層執行剝除製程,其中所述剝除溶液包含非二甲亞碸溶劑及鹼性化合物,所述非二甲亞碸溶劑包括非質子溶劑及質子溶劑。
- 如請求項7所述的製造半導體結構的方法,其中所述非質子溶劑包括N-甲基吡咯烷酮(NMP)、四氫呋喃(THF)、二甲基甲醯胺(DMF)、乙腈(MeCN)或二氯甲烷(DCM),所述質子溶劑包括乙醇胺(MEA)、甲基乙醇胺、2-(2-氨基乙基氨基)乙醇或二乙醇胺,所述鹼性化合物包括四甲基氫氧化銨(TMAH)、氫氧化鉀(KOH)、氫氧化鈉(NaOH)或其組合,且以所述剝除溶液的總重量計,所述非質子溶劑的量為20重量%到70重量%,所述質子溶劑的量為20重量%到70重量%,所述鹼性化合物的量為0.5重量%到5.5重量%。
- 如請求項7所述的製造半導體結構的方法,其中所述多個金屬圖案被形成為具有介於30 μm到120 μm範圍內的兩個相鄰金屬圖案的節距。
- 如請求項7所述的製造半導體結構的方法,其中所述圖案化罩幕層的材料包括含酯基的抗蝕劑材料。
- 如請求項7所述的製造半導體結構的方法,其中在所述剝除製程期間,所述鹼性化合物滲透到所述圖案化罩幕層中,以使所述圖案化罩幕層的交聯結構斷裂。
- 如請求項7所述的製造半導體結構的方法,其中所述非質子溶劑的量與所述質子溶劑的量的比率介於1:3.5到3.5:1範圍內。
- 如請求項7所述的製造半導體結構的方法,其中所述多個金屬圖案中的至少一者被形成為具有大於3的縱橫比。
- 一種製造半導體結構的方法,包括: 在載體上形成多個導電穿孔; 在所述載體上設置晶粒;以及 用包封體在側向上包封所述晶粒及所述多個導電穿孔,其中在所述載體上形成所述多個導電穿孔包括: 在所述載體上依序形成晶種層及抗蝕劑層; 對所述抗蝕劑層進行圖案化以形成暴露出所述晶種層的多個開口; 在所述多個開口中形成多個金屬圖案;以及 用剝除溶液執行剝除製程以移除經圖案化的所述抗蝕劑層,其中所述剝除溶液包含非二甲亞碸溶劑及鹼性化合物,所述非二甲亞碸溶劑包含非質子溶劑及質子溶劑。
- 如請求項14所述的製造半導體結構的方法,其中所述非質子溶劑包括N-甲基吡咯烷酮(NMP)、四氫呋喃(THF)、二甲基甲醯胺(DMF)、乙腈(MeCN)或二氯甲烷(DCM),所述質子溶劑包括乙醇胺(MEA)、甲基乙醇胺、2-(2-氨基乙基氨基)乙醇或二乙醇胺,所述鹼性化合物包括四甲基氫氧化銨(TMAH)、氫氧化鉀(KOH)或其組合,且以所述剝除溶液的總重量計,所述非質子溶劑的量為20重量%到70重量%,所述質子溶劑的量為20重量%到70重量%,所述鹼性化合物的量為0.5重量%到5.5重量%。
- 如請求項14所述的製造半導體結構的方法,其中在所述載體上形成所述多個導電穿孔更包括: 在移除經圖案化的所述抗蝕劑層之後,移除所述晶種層的被所述多個金屬圖案暴露出的一部分。
- 如請求項14所述的製造半導體結構的方法,其中在所述剝除製程期間,通過浸漬施加所述剝除溶液。
- 如請求項14所述的製造半導體結構的方法,其中所述非質子溶劑的量與所述質子溶劑的量的比率介於1:3.5到3.5:1範圍內。
- 如請求項14所述的製造半導體結構的方法,其中所述開口中的至少一者被形成為具有大於3的縱橫比。
- 如請求項14所述的製造半導體結構的方法,其中所述剝除製程的製程時間介於1分鐘到180分鐘範圍內,且所述剝除製程的製程溫度介於25℃到100℃範圍內。
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