CN113745120A - 微电子装置及其制造方法 - Google Patents

微电子装置及其制造方法 Download PDF

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Publication number
CN113745120A
CN113745120A CN202110591716.3A CN202110591716A CN113745120A CN 113745120 A CN113745120 A CN 113745120A CN 202110591716 A CN202110591716 A CN 202110591716A CN 113745120 A CN113745120 A CN 113745120A
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chip
circuit board
printed circuit
film
semiconductor chip
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克里斯托夫·兰德斯伯格
克里斯托夫·库特
彼得·拉姆
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Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
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Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
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Abstract

实施例提供了一种用于制造微电子装置的方法。该方法包括提供具有半导体芯片和该半导体芯片被布置在其上的膜衬底的芯片膜模块的步骤，其中，芯片膜模块包括与半导体芯片间隔开并且电耦合到半导体芯片的至少一个端子的至少一个耦合元件。此外，该方法包括将芯片膜模块嵌入到印刷电路板中的步骤，其中，在将芯片膜模块嵌入到印刷电路板中时，芯片膜模块的至少一个耦合元件竖直地[例如，沿竖直方向[例如，相对于印刷电路板]][例如，垂直于印刷电路板的表面]耦合到印刷电路板的至少一个耦合对应元件。

Description

微电子装置及其制造方法
技术领域
实施例涉及一种用于制造微电子装置的方法，尤其涉及一种具有芯片膜模块(例如，芯片膜内插器)的微电子装置。其他实施例涉及这种微电子装置。一些实施例涉及芯片膜内插器的模块化集成。
背景技术
微电子技术的基本目标是以总是更小、更薄和更轻的方式制造功能组件，从而使便携式电子设备(例如，智能电话、膝上型电脑、智能手表、身体传感器系统)能够得到越来越多的使用，或者在集成系统的体积减小的情况下提高计算速度或存储容量。
已知多种不同的三维集成技术。它们通常基于垂直穿过晶片衬底的导电接触部(例如，硅通孔(TSV))的使用。半导体晶片本身(例如，具有IC元件(IC＝集成电路))可以是衬底，或者由硅或玻璃制成的附加的所谓内插器晶片可以是衬底。这里的内插器是指从一个端子焊盘或一个连接到另一个端子焊盘或另一个连接的电路由接口。例如，内插器的目的是将端子焊盘路由到更大的端子焊盘或将一个连接重定向到另一个连接。在硅衬底的情况下，导电通孔(或直通连接)与周围的衬底绝缘。用于在晶片衬底上制造这些通孔的技术非常复杂，并且只能在特殊的半导体工厂中执行。在玻璃内插器的情况下，省略了对绝缘的要求。然而，复杂的工艺顺序仍然存在；此外，非常薄的玻璃内插器晶片非常易于破损。
所谓的晶片到晶片集成技术的另一个缺点是三维堆叠中的成品率损失，因为所有芯片组件通常都在晶片上接触，即使是那些不具有电功能的组件。
对此的备选方案是所谓的芯片到晶片集成，其中预先选择已经测试的集成电路(IC)。呈芯片到晶片配置的衬底具有大的形貌。这导致在每个平面中都需要精细平面化的缺点。
例如，从DE102017208435A1中已知一种用于制造芯片膜内插器的方法。
另外，已知所谓的嵌入技术，其中未封装的半导体组件(例如，集成电路(IC))被嵌入到印刷电路板中并且与印刷电路板技术的工艺电接触。这里存在一个大障碍：芯片上的接触焊盘的表面积很小，使得它们实际上不能使用PCB(印刷电路板)工业的结构化工艺来选择性地和以所要求的高成品率接触和布线。因此，传统上，首先在半导体晶片上实现再分布(例如，通过再分布层(RDL))，其目的是将通常位于芯片布局的边缘处的非常小的接触焊盘分布在跨整个芯片表面积的附加上金属化平面中并且将焊盘表面积另外扩展到大于200μm×200μm的大小。另外，这些再分布的接触区域必须被提供有稳定的金属化层(例如，镍或金)，其厚度为几微米，因为稍后在半导体工厂的通孔制造中使用激光以便向下打开接触孔到芯片接触部。通常，激光会在印刷电路板材料中产生直径大于100μm的孔(即，大于集成电路(IC)上的原始小接触焊盘)，并且还损坏接触焊盘上的金属表面。因此，接触焊盘必须变得更大(通过再分布)以及面对激光辐射更稳定(因此添加Ni/Au涂层)。这两种工艺都很复杂且成本高。另一个问题是在印刷电路板工厂中处理未封装的芯片；通常，在这些场所，没有用于处理易于破损的非常小的半导体元件的机器。
将封装的组件(例如，硅芯片和具有大约1mm厚度的所谓的模具封装)集成到印刷电路板中没有意义，因为印刷电路板将甚至变得更厚并且布线(布局)的实施方式中的几何自由度将受到限制；因此，在更大的集成密度或更小的结构形状方面没有优势。
另外，已知在每个平面中包括层压层(例如，“预浸料坯”：具有铜涂层的环氧树脂层)的多层印刷电路板。传统上，铜层以湿化学方式构造，以便创建导体路径。在这种情况下，利用光刻掩模或光刻胶的数字直接光刻。
因此，本发明的目的在于改善现有情况。
发明内容
该目的通过独立专利权利要求来解决。
有利的进一步发展可以在从属专利权利要求中找到。
实施例提供了一种用于制造微电子装置的方法。该方法包括提供具有半导体芯片和该半导体芯片被布置在其上的膜衬底的芯片膜模块[例如，膜内插器]的步骤，其中，芯片膜模块包括与半导体芯片间隔开并且电耦合到半导体芯片的至少一个端子的至少一个耦合元件。此外，该方法包括将芯片膜模块嵌入到印刷电路板中的步骤，其中，在将芯片膜模块嵌入到印刷电路板中时，芯片膜模块的至少一个耦合元件竖直地[例如，沿竖直方向[例如，相对于印刷电路板]][例如，垂直于印刷电路板的表面]耦合到印刷电路板的至少一个耦合对应元件。
本发明基于以下思想：首先将(薄)半导体芯片(例如，半导体组件)集成到薄的、基于膜的模块(例如，封装)中，然后将该芯片膜模块(例如，膜内插器)永久地集成在印刷电路板中，并且实现相应的(例如，电、光学、电容、电感、电磁)连接。
在实施例中，基本上，芯片膜模块(例如，芯片膜封装或膜内插器)的功能是通过在薄膜载体上进行接触和再分布(再布线)将半导体芯片上的接触焊盘的非常小的几何形状(例如，焊盘的表面积当前是大约60μm×60μm；焊盘的距离：20-60μm)扩展到与标准印刷电路板生产的典型几何形状兼容的度量。也就是说，芯片膜模块上的外部接触部的焊盘大小和焊盘距离然后可以大于100μm，优选地大于200μm。
在实施例中，然后可以将具有集成半导体芯片(例如，半导体组件)的(薄)芯片膜模块(例如，膜内插器)插入到印刷电路板的内部位置，并且其可以被永久地连接。印刷电路板组件中可以包含一个或多个这样的嵌入式芯片膜模块，芯片膜模块还可以作为三维堆叠集成到印刷电路板中。
在实施例中，芯片膜模块的至少一个耦合元件中的至少一个耦合元件是电端子(电连接器)，其中，印刷电路板的至少一个耦合对应元件中的至少一个耦合对应元件是通孔(直通接触)。
在实施例中，芯片膜模块的端子的端子面积大于半导体芯片的端子的端子面积[例如，至少1.5或2倍]和/或其中，芯片膜模块的端子之间的距离大于半导体芯片的端子之间的距离[例如，至少1.5或2倍]。
在实施例中，芯片膜模块的至少一个耦合元件中的至少一个耦合元件是光学耦合元件[例如，LED、光电二极管或光电探测器]，其中，印刷电路板的至少一个耦合对应元件中的至少一个耦合对应元件是光学耦合对应元件[例如，光电探测器、光电二极管或LED]。
在实施例中，芯片膜模块的至少一个耦合元件中的至少一个耦合元件是电感或电容耦合元件[例如，线圈/导体环或电容器板]，其中，印刷电路板的至少一个耦合对应元件中的至少一个耦合对应元件是电感或电容耦合对应元件[例如，线圈/导体环或电容器板]。
在实施例中，半导体芯片[例如，完全地]嵌入到芯片膜模块中[例如，通过嵌入层和膜衬底]。
在实施例中，至少一个耦合元件布置在膜衬底上或膜衬底中，并且经由形成在膜衬底上或膜衬底中的至少一条导体路径连接到半导体芯片的至少一个端子。
在实施例中，半导体芯片布置在膜衬底上，使得半导体芯片的至少一个端子背对膜衬底，其中，至少一个耦合元件布置在芯片膜模块的半导体芯片嵌入其中的嵌入层中或嵌入层上，其中，至少一个耦合元件经由竖直电连接来连接到半导体芯片的至少一个端子。
在实施例中，膜衬底包括经由形成在膜衬底中或膜衬底上的至少两条导体路径连接到半导体芯片的至少两个端子的至少两个端子元件，其中，芯片膜模块包括位于彼此上方或以堆叠方式设置的至少两个嵌入层，其嵌入半导体芯片和/或膜衬底，其中，芯片膜模块包括布置在该至少两个嵌入层中的不同嵌入层中或不同嵌入层上的至少两个耦合元件，其中，该至少两个耦合元件经由竖直电连接来连接到膜衬底的至少两个端子元件。
在实施例中，印刷电路板包括芯片膜模块[例如，完全地]嵌入其中的至少两个层压平面。
在实施例中，半导体芯片经由芯片膜模块的至少一个耦合元件和印刷电路板的至少一个耦合对应元件连接到印刷电路板的至少一个电路组件。
在实施例中，提供芯片膜模块的步骤包括：
-提供半导体芯片；
-提供膜衬底；
-将半导体芯片连接到膜衬底。
在实施例中，提供芯片膜模块的步骤还包括：
-将半导体芯片嵌入到嵌入层中。
在实施例中，将芯片膜模块嵌入到印刷电路板中的步骤包括：
-提供印刷电路板的至少一个层压平面，
-将芯片膜模块布置在印刷电路板的至少一个层压平面上或印刷电路板的至少一个层压平面内，
-在印刷电路板的至少一个层压平面上和/或下提供印刷电路板的至少一个另外的层压平面，使得芯片膜模块嵌入到印刷电路板中。
在实施例中，膜衬底包括与半导体芯片间隔开并且经由形成在膜衬底中或膜衬底上的两条导体路径连接到半导体芯片的至少两个端子的至少两个耦合元件，其中，该至少两个耦合元件是电端子，其中，印刷电路板的导体路径经由作为对应耦合元件的至少两个通孔连接到膜衬底的端子。
在实施例中，在布置在膜衬底上的嵌入层中将半导体芯片嵌入到芯片膜模块中。
在实施例中，该至少两个通孔竖直地延伸穿过膜衬底或穿过嵌入层到膜衬底的至少两个端子。
在实施例中，从印刷电路板的第一平面开始，该至少两个通孔中的第一通孔竖直地延伸穿过膜衬底到膜衬底的该至少两个端子中的第一端子，和/或其中，从印刷电路板的第二平面开始，该至少两个通孔中的第二通孔竖直地延伸穿过芯片膜模块的嵌入层到膜衬底的该至少两个端子中的第二端子。
在实施例中，至少一个耦合元件布置在膜衬底上或膜衬底中并且经由形成在膜衬底上或膜衬底中的至少一条导体路径连接到半导体芯片的至少一个端子，其中，膜接口衬底的至少一个耦合元件中的至少一个耦合元件是光学耦合元件，其中，印刷电路板的至少一个耦合对应元件中的至少一个耦合对应元件是光学耦合对应元件，其中，该光学耦合元件和该光学耦合对应元件沿竖直方向彼此光学地耦合。
在实施例中，该至少一个耦合元件中的至少一个另外的耦合元件布置在膜衬底上或膜衬底中并且经由形成在膜衬底上或膜衬底中的至少一条另外的导体路径连接到半导体芯片的至少一个另外的端子，其中，该至少一个另外的耦合元件是电感或电容耦合元件，其中，印刷电路板的至少一个耦合对应元件中的至少一个另外的耦合对应元件是电感或电容耦合对应元件，其中，该电感或电容耦合元件和该电感或电容耦合对应元件沿竖直方向彼此电感或电容地耦合。
在实施例中，芯片膜模块包括至少两个耦合元件，其中，半导体芯片包括至少两个端子，其中，半导体芯片布置在膜衬底上，使得半导体芯片的至少两个端子背对膜衬底，其中，至少两个耦合元件布置在芯片膜模块的半导体芯片嵌入其中的嵌入层中或嵌入层上，其中，该至少两个耦合元件经由竖直电连接来连接到半导体芯片的至少两个端子，其中，该至少两个耦合元件是电端子，其中，印刷电路板的导体路径经由作为对应耦合元件的至少两个通孔连接到芯片膜模块的至少两个端子。
在实施例中，膜衬底是导热膜衬底，其中，印刷电路板包括与导热膜衬底相邻的热通孔，其被配置为将热能从导热膜衬底传导到印刷电路板的周围区域。
在实施例中，膜衬底包括经由形成在膜衬底中或膜衬底上的至少两条导体路径连接到半导体芯片的至少两个端子的两个端子元件，其中，芯片膜模块包括位于彼此上方或以堆叠方式设置的嵌入半导体芯片和/或膜衬底的两个嵌入层，其中，芯片膜模块包括布置在该至少两个嵌入层中的不同嵌入层中或不同嵌入层上的至少两个耦合元件，其中，该至少两个耦合元件经由竖直电连接来连接到膜衬底的至少两个端子元件，其中，该至少两个耦合元件是电端子，其中，印刷电路板的导体路径经由作为对应耦合元件的至少两个通孔连接到芯片膜模块的至少两个端子，其中，从印刷电路板的第一平面开始，该至少两个通孔中的第一通孔竖直地延伸到芯片膜模块的至少两个端子中的第一端子，其中，从印刷电路板的第二平面开始，该至少两个通孔中的第二通孔竖直地延伸到膜衬底的至少两个端子中的第二端子。
在实施例中，该方法包括提供具有另外的半导体芯片和该另外的半导体芯片被布置在其上的另外的膜衬底的另外的芯片膜模块[例如，膜内插器]的步骤，其中，该另外的芯片膜模块包括与另外的半导体芯片间隔开并且耦合到另外的半导体芯片的至少一个端子的至少一个耦合元件，并且其中，该方法包括将该另外的芯片膜模块嵌入到印刷电路板中的步骤，其中，在将另外的芯片膜模块嵌入到印刷电路板中时，另外的芯片膜模块的至少一个耦合元件竖直地耦合到印刷电路板的至少一个另外的耦合对应元件，其中，芯片膜模块和另外的芯片膜模块在印刷电路板的竖直方向上堆叠。
在实施例中，印刷电路板包括至少两个导体路径平面，其中，芯片膜模块布置在该至少两个导体路径平面之间，其中，在将芯片膜模块嵌入到印刷电路板中时，穿过该芯片膜模块形成竖直通孔，用于连接该至少两个导体路径平面的导体路径。
另外的实施例提供了一种具有印刷电路板和芯片膜模块的微电子装置，其中，芯片膜模块包括半导体芯片和该半导体芯片被布置在其上的膜衬底，其中，芯片膜模块包括与半导体芯片间隔开并且电耦合到半导体芯片的至少一个端子的至少一个耦合元件，其中，芯片膜模块[例如，完全地]嵌入到印刷电路板中，其中，芯片膜模块的至少一个耦合元件竖直地[例如，沿竖直方向[例如，相对于印刷电路板]][例如，垂直于印刷电路板的表面]耦合到印刷电路板的至少一个耦合对应元件。
另外的实施例提供了一种芯片膜模块，该芯片膜模块具有膜衬底、布置在膜衬底上的半导体芯片以及与半导体芯片间隔开并且布置在膜衬底上或膜衬底中的至少一个耦合元件，其中，该至少一个耦合元件经由形成在膜衬底上或膜衬底中的至少一条导体路径电耦合到半导体芯片的至少一个端子，其中，该至少一个耦合元件被配置为耦合到至少一个外部对应耦合元件，其中，芯片膜模块包括布置在膜衬底上的嵌入层，其中，该嵌入层完全地嵌入半导体芯片和至少一个耦合元件，其中，该至少一个耦合元件是电端子[例如，电端子区域[例如，焊盘]]。
另外的实施例提供了一种芯片膜模块，该芯片膜模块具有膜衬底、布置在膜衬底上的半导体芯片以及与半导体芯片间隔开并且布置在膜衬底上或膜衬底中的至少一个耦合元件，其中，该至少一个耦合元件经由形成在膜衬底上或膜衬底中的至少一条导体路径电耦合到半导体芯片的至少一个端子，其中，该至少一个耦合元件被配置为耦合到至少一个外部对应耦合元件，其中，芯片膜模块包括布置在膜衬底上的嵌入层，其中，该嵌入层完全地嵌入半导体芯片和至少一个耦合元件，其中，该至少一个耦合元件是光学耦合元件。
另外的实施例提供了一种芯片膜模块，该芯片膜模块具有膜衬底、布置在膜衬底上的半导体芯片、与半导体芯片间隔开的至少两个耦合元件，其中，膜衬底包括经由形成在膜衬底中或膜衬底上的至少两条导体路径连接到半导体芯片的至少两个端子的至少两个端子元件，其中，芯片膜模块包括位于彼此上方或以堆叠方式设置的嵌入半导体芯片和/或膜衬底的至少两个嵌入层，其中，至少两个耦合元件布置在该至少两个嵌入层中的不同嵌入层中或不同嵌入层上，其中，该至少两个耦合元件经由竖直电连接来连接到膜衬底的至少两个端子元件，其中，该至少两个耦合元件被配置为耦合到至少两个外部对应耦合元件。
另外的实施例提供了一种微电子装置，该微电子装置具有印刷电路板和根据本文描述的任何实施例的芯片膜模块，其中，芯片膜模块[例如，完全地]嵌入到印刷电路板中，其中，芯片膜模块的至少一个耦合元件竖直地[例如，沿竖直方向[例如，相对于印刷电路板]][例如，垂直于印刷电路板的表面]耦合到印刷电路板的至少一个耦合对应元件。
另外的实施例提供了一种用于制造三维电子系统(特别是三维集成电路)的方法。三维集成被理解为组件的(机械的和电的)竖直连接。三维集成电子系统的优点尤其在于，与二维系统(平面技术)相比，尤其可以实现更高的封装密度和开关速度[由更短的传导距离导致]。
另外的实施例提供了一种多层电路载体，该多层电路载体在其内部中或其表面上包括膜内插器，其特征在于，在膜内插器上实现导体路径结构，包括电路载体的导体路径结构与膜内插器的导电结构之间的电(通电地耦合)或电磁或光学耦合。
另外的实施例提供了一种多层电路载体，该多层电路载体在其内部中或其表面上包括膜内插器，其特征在于，在膜内插器上安装至少一个电功能组件(例如，IC组件(IC＝集成电路))。
另外的实施例提供了一种多层电路载体，该多层电路载体在其内部中或其表面上包括膜内插器，其特征在于，在膜内插器上布置至少一个电功能组件(例如，IC组件(IC＝集成电路))，其中，半导体组件电连接到电路载体的导体路径。
另外的实施例提供了一种电路载体中的膜内插器，该膜内插器包括穿过膜内插器的接触孔(通孔)，其中，不存在到膜内插器的导体路径结构的电接触，然而，通孔可以用于电路载体上的布线。
另外的实施例提供了一种基于导热膜(例如，铜膜)的内插器，该内插器包括到多层电路载体中的导热层的形状锁定接触部。
另外的实施例提供了一种包括多个膜内插器的电路载体，其中，该多个膜内插器也沿竖直方向位于彼此上方(印刷电路板(PCB)中的膜内插器的三维堆叠)，并且导体路径被电连接。
附图说明
将参考附图更详细地描述本发明的实施例，附图中：
图1示出了根据本发明的实施例的用于制造微电子装置的方法的流程图；
图2a示出了根据本发明的实施例的在提供芯片膜模块的步骤之后的芯片膜模块的示意性横截面视图；
图2b示出了根据本发明的实施例的在提供芯片膜模块的步骤之后的芯片膜模块的示意性横截面视图；
图2c示出了根据本发明的实施例的在将芯片膜模块嵌入到印刷电路板中之后的微电子装置的示意性横截面视图；
图3示出了根据第一实施例的芯片膜模块的示意性横截面视图；
图4示出了根据第二实施例的芯片膜模块的示意性横截面视图；
图5示出了根据第三实施例的芯片膜模块的示意性横截面视图；
图6示出了根据第四实施例的芯片膜模块的示意性横截面视图；
图7示出了根据第五实施例的芯片膜模块的示意性横截面视图；
图8示出了根据第六实施例的芯片膜模块的示意性横截面视图；
图9示出了根据第七实施例的芯片膜模块的示意性横截面视图；
图10a、10b示出了根据第一实施例的具有印刷电路板和嵌入到印刷电路板中的图3的芯片膜模块的微电子装置的示意性横截面视图；
图11示出了根据第二实施例的具有印刷电路板和嵌入到印刷电路板中的图4的芯片膜模块的微电子装置的示意性横截面视图；
图12示出了根据第三实施例的具有印刷电路板和嵌入到印刷电路板中的图5的芯片膜模块的微电子装置的示意性横截面视图；
图13示出了根据第四实施例的具有印刷电路板和嵌入到印刷电路板中的图6的芯片膜模块的微电子装置的示意性横截面视图；
图14示出了根据第五实施例的具有印刷电路板和嵌入到印刷电路板中的图7的芯片膜模块的微电子装置的示意性横截面视图；
图15a、15b示出了根据第六实施例的具有印刷电路板和嵌入到印刷电路板中的图8的芯片膜模块的微电子装置的示意性横截面视图；
图16示出了根据第七实施例的具有印刷电路板和嵌入到印刷电路板中的任意芯片膜模块的微电子装置的示意性横截面视图；
图17示出了根据第八实施例的具有印刷电路板和嵌入到印刷电路板中的两个任意芯片膜模块的微电子装置的示意性横截面视图；
图18示出了根据第九实施例的具有印刷电路板和嵌入到印刷电路板中的图9的芯片膜模块的微电子装置的示意性横截面视图。
具体实施方式
在本发明的实施例的后续描述中，对相同的元件或具有相同效果的元件提供有相同的附图标记，因此，它们的描述是可互换的。
图1示出了根据本发明的实施例的用于提供微电子装置的方法100的流程图。方法100包括提供具有半导体芯片和该半导体芯片被布置在其上的膜衬底的芯片膜模块的步骤102，其中，芯片膜模块包括与半导体芯片间隔开并且电耦合到半导体芯片的至少一个端子的至少一个耦合元件。方法100还包括将芯片膜模块嵌入到印刷电路板中的步骤104，其中，在将芯片膜模块嵌入到印刷电路板中时，芯片膜模块的至少一个耦合元件竖直地耦合到印刷电路板的至少一个耦合对应元件。
在实施例中，芯片膜模块可以是膜内插器。内插器通常是指从例如用于半导体芯片的端子的至少一个端子焊盘到至少一个其他端子焊盘或连接元件的电接口路由。在实施例中，内插器是指从例如用于半导体芯片的端子的至少一个端子焊盘到作为连接元件的至少一个耦合元件(例如，电、光学、电感、电容或电磁耦合元件)的电接口路由，使得能够经由相应的对应耦合元件将耦合元件最终地与半导体芯片的至少一个端子相耦合。
下面基于图2a、图2b和图2c更详细地描述图1所示的方法100的优选实施例，图2a、图2b和图2c示出了在方法100的不同步骤之后的芯片膜模块或具有集成到印刷电路板中的芯片膜模块的微电子装置的示意性横截面视图。
图2a示出了根据本发明的实施例的在提供芯片膜模块120的步骤102之后的芯片膜模块120的示意性横截面视图。如可以在图2a中看出的，芯片膜模块120可以包括半导体芯片122和膜衬底124，其中，半导体芯片122布置在膜衬底124上，其中，芯片膜模块120包括与半导体芯片122间隔开并且电耦合到半导体芯片122的至少一个端子128的至少一个耦合元件126。
如可以在图2a中进一步看出的，半导体芯片122可以可选地(例如，完全地)嵌入到芯片膜模块120中，例如通过嵌入层132和膜衬底124。
图2a所示的实施例示例性地假设至少一个耦合元件126布置在膜衬底124上或膜衬底124中，并且经由形成在膜衬底124上或膜衬底124中的至少一条导体路径130连接到半导体芯片122的至少一个端子128。
图2b示出了根据本发明的另外的实施例的在提供芯片膜模块120的步骤102之后的芯片膜模块120的示意性横截面视图。与图2a所示的实施例相比，图2b所示的实施例假设半导体芯片122布置在膜衬底124上，使得半导体芯片的至少一个端子128背对膜衬底124，其中，至少一个耦合元件126布置在芯片膜模块120的半导体芯片122嵌入其中的嵌入层132中或嵌入层132上，其中，该至少一个耦合元件经由电连接130连接到半导体芯片的至少一个端子。
在实施例中，图2a和图2b所示的芯片膜模块可以通过使用以下步骤来制造：
-提供半导体芯片122；
-提供膜衬底124；
-将半导体芯片122连接到膜衬底124；以及可选地
-将半导体芯片122嵌入到嵌入层132中。
图2c示出了在将芯片膜模块120嵌入到印刷电路板142中之后的微电子装置140的示意性横截面视图。如可以在图2c中看出的，在将芯片膜模块120嵌入到印刷电路板142中时，芯片膜模块120的至少一个耦合元件126可以竖直地耦合到印刷电路板142的至少一个耦合对应元件144。在这种情况下，半导体芯片122可以经由芯片膜模块120的至少一个耦合元件132和印刷电路板142的至少一个耦合对应元件144连接到印刷电路板142的至少一个电路组件150。
例如，芯片膜模块120的至少一个耦合元件126可以是电端子，其中，印刷电路板142的至少一个耦合元件144可以是通孔。例如，芯片膜模块120的电端子126的端子面积可以大于半导体芯片的端子128的端子面积(例如，至少1.5或2倍)和/或其中，芯片膜模块的端子126之间的距离可以大于半导体芯片122的端子128之间的距离(例如，至少1.5或2倍)。
例如，芯片膜模块120的至少一个耦合元件126可以是光学耦合元件，例如LED、光电二极管或光电探测器，而印刷电路板142的至少一个耦合对应元件144可以是光学耦合对应元件，例如光电探测器、光电二极管或LED。
例如，芯片膜模块120的至少一个耦合元件126可以是电感或电容耦合元件，例如线圈或导体环或电容器板，而印刷电路板142的至少一个耦合对应元件144可以是电感或电容耦合对应元件，例如线圈或导体环或电容器板。
在实施例中，如图2c示例性示出的印刷电路板142可以可选地包括芯片膜模块120(例如，完全地)嵌入其中的两个层压平面146_1和146_2。
在实施例中，芯片膜模块120可以通过以下步骤嵌入到印刷电路板142中：
-提供印刷电路板142的至少一个层压平面146_2；
-将芯片膜模块120布置在印刷电路板142的至少一个层压平面146_2上或印刷电路板142的至少一个层压平面146_2内；以及
-在印刷电路板142的至少一个层压平面146_2上和/或下提供印刷电路板142的至少一个另外的层压平面146_1，使得芯片膜模块120嵌入到印刷电路板142中。
在实施例中，半导体芯片122(例如，半导体组件)的厚度可以是10-250μm，优选地是20至100μm。
在实施例中，膜衬底124的厚度(膜厚度)可以是10至200μm，优选地是15至50μm。
在实施例中，膜衬底可以是以下衬底之一：聚酰亚胺、PET(聚对苯二甲酸乙二醇酯)、PEN(聚萘二甲酸乙二醇酯)、FR4(一类环氧树脂和玻璃纤维织物的难燃和阻燃复合物)、PEI(聚醚酰亚胺)、LCP(液晶聚合物)、PC(聚碳酸酯)。
在实施例中，接触半导体芯片(或例如，集成电路(IC))可以通过ACA或ACF倒装芯片接合或焊料组装和底部填充剂来在膜片上执行。
在实施例中，在半导体芯片(或例如，集成电路(IC))的所谓“面朝上”的组装中，可以例如通过溅射(例如，物理气相沉积(PVD))执行直接接触。
下面，基于图3至图9更详细地描述芯片膜模块120的详细实施例，图3至图9示出了芯片膜模块120的不同实施例的示意性横截面视图。在这种情况下，芯片膜模块120包括半导体芯片122、半导体芯片122被布置在其上的膜衬底124以及与半导体芯片122间隔开并且均电耦合到半导体芯片的至少一个端子128的至少一个耦合元件126。
图3示出了根据第一实施例的芯片膜模块120的示意性横截面视图。如可以在图3中看出的，膜衬底124包括与半导体芯片122间隔开并且经由形成在膜衬底124中或膜衬底124上的两条导体路径130_1和130_2连接到半导体芯片122的至少两个端子128_1和128_2的至少两个耦合元件126_1和126_2，其中，该至少两个耦合元件126_1和126_2是电端子。
换句话说，图3示出了其中半导体芯片122通过所谓的倒装芯片组装安装在衬底膜124上的芯片膜模块(例如，芯片膜内插器)的实施方式。芯片接触部128_1和128_2连接到膜衬底124(例如，内插器膜)上的导体路径130_1和130_2，并且芯片膜模块120包括另外的接触区域126_1和126_2。芯片膜模块120上的接触区域126_1和126_2(所谓的扇出外部接触部)优选地显著大于半导体芯片122(例如，半导体组件)上的接触区域。
图4示出了根据第二实施例的芯片膜模块120的示意性横截面视图。与图3所示的实施例相比，半导体芯片122和芯片膜模块120(例如，完全地)嵌入到布置在膜衬底124上的嵌入层132中。
换句话说，图4示出了芯片膜模块120(例如，内插器)，其中，半导体芯片122嵌入到电绝缘材料132(例如，聚合物)中，从而创建了基本上平面平行的封装。半导体芯片122在内部得到良好的保护。图4所示的芯片膜模块120不包括任何外部的电接触部。外部接触部仅在稍后集成到印刷电路板(PCB)中之后才可用(参见图11)。
图5示出了根据第三实施例的芯片膜模块120的示意性横截面视图。与图4所示的实施例相比，芯片膜模块120还包括至少两个通孔134_1和134_2，其中，该至少两个通孔134_1和134_2竖直地延伸穿过膜衬底124或穿过嵌入层132到膜衬底124的至少两个端子126_1和126_2。
换句话说，图5示出了在膜外壳(例如，膜封装)处还包括外部接触部的芯片膜模块120(例如，内插器)。例如，这可以通过穿过衬底膜124或穿过封装材料132的导电通孔134_1和134_2来实现。
图6示出了根据第四实施例的芯片膜模块120的示意性横截面视图。如可以在图6中看出的，膜衬底124可以包括与半导体芯片122间隔开并且经由形成在膜衬底124中或膜衬底124上的至少两条导体路径130_1和130_2连接到半导体芯片122的至少两个端子128_1和128_2的至少两个耦合元件126_1和126_2。该耦合元件可以是光学耦合元件，例如LED和/或光电二极管。附加地或备选地，耦合元件可以是电感、电容或电磁耦合元件，例如导体环、线圈、电容器板和/或天线。
换句话说，图6示出了不包括可通电接触的外部接触部的芯片膜模块120(例如，内插器)。经由电磁或光学连接路径的无线连接用于创建到半导体芯片122的信号连接。第一种情况可以通过天线(例如，线圈或偶极天线)来完成，第二种情况可以通过从外部接收外部信号的光电管来完成，然而，放置在芯片模块120上的LED也可以朝向外部发送信号。通电也可以通过以线圈中的电磁波耦合来执行。
图7示出了根据第五实施例的芯片膜模块120的示意性横截面视图。如可以在图7中看出的，半导体芯片122可以布置在膜衬底124上，使得半导体芯片122的至少两个端子128_1和128_2背对膜衬底124，其中，该至少两个端子128_1和128_2经由布置在芯片膜模块120的嵌入层132中或嵌入层132上的两个竖直电连接131_1和131_2(例如，导电接触孔或通孔)连接到至少两条导体路径130_1和132_2。在这种情况下，该至少两条导体路径可以形成至少两个电耦合元件(电端子)。
换句话说，图7示出了其中半导体芯片以所谓的“面朝上”的取向放置在衬底膜124上的芯片膜模块120(例如，内插器)。这里，优点是不需要在芯片膜模块120上进行凸块金属化。半导体芯片122(例如，半导体组件)上的接触焊盘128_1和128_2经由气相沉积的或溅射(例如，物理气相沉积(PVD))的金属层直接接触。
图8示出了根据第六实施例的芯片膜模块120的示意性横截面视图。与图7所示的实施例相比，膜衬底124是导热膜衬底。这里，半导体芯片122可以经由导热粘合剂层127(例如，焊料或粘合剂)连接到导热膜衬底124。
换句话说，图8示出了其衬底膜124是金属膜(例如，铜膜)的的芯片膜模块(例如，内插器)。如果半导体芯片122(例如，半导体组件)以其背面通过焊料连接或导热粘合剂层安装在铜膜上，则半导体芯片122中可能产生的热量可以经由背面非常高效地消散。
图9示出了根据第七实施例的芯片膜模块120的示意性横截面视图。如可以在图9中看出的，膜衬底124可以包括经由形成在膜衬底中或膜衬底上的两条导体路径130_1和130_2连接到半导体芯片122的至少两个端子128_1和128_2的至少两个端子元件125_1和125_2，其中，芯片膜模块120包括位于彼此上方或以堆叠方式设置的嵌入半导体芯片122和/或膜衬底124的至少两个嵌入层132_1-132_3，其中，芯片膜模块120包括布置在该至少两个嵌入层132_1-132_3中的不同嵌入层132_1-132_2中或不同嵌入层132_1-132_2上的至少两个耦合元件126_1和126_2，其中，该至少两个耦合元件经由竖直电连接134_1-134_3连接到至少两个耦合元件126_1和126_2(例如，电端子)。显然，芯片膜模块还可以包括另外的再分布135_1和135_2。
换句话说，图9示出了包括多层再分布的芯片膜模块(例如，内插器)，其可以是单面的或双面的。换句话说，图9示出了具有多层再分布的膜封装。
下面，基于图10a至图18更详细地描述通过将图3至图9所示的芯片膜模块120集成(例如，嵌入)到印刷电路板(PCB)中而得到的微电子装置的详细实施例。当将各个芯片膜模块120集成到印刷电路板中时，芯片膜模块120的至少一个耦合元件126竖直地耦合到印刷电路板142的至少一个耦合对应元件144。
在这种情况下，虽然仅在图10a至图16中的一些图中示例性地绘制了导体路径平面，但是应当注意，它们通常可以是可用的，并且印刷电路板的各片上的再分布也可以具有若干层。
图10a示出了根据第一实施例的具有印刷电路板142和嵌入到印刷电路板142中的图3的芯片膜模块(集成到PCB中的图3的芯片膜内插器)的微电子装置140的示意性横截面视图。如可以在图10a中看出的，印刷电路板142可以包括芯片膜模块120(例如，完全地)嵌入到其中的若干层压平面146_1-146_4。如可以在图10a中进一步看出的，芯片膜模块120的至少两个端子126_1和126_2(耦合元件)可以连接到印刷电路板142的至少两个通孔144_1和144_2(对应耦合元件)。这里，通孔144_1和144_2可以连接到印刷电路板142的导体路径148_1，如图10b所示。另外，印刷电路板142可以包括多层再分布150_1和150_2。
换句话说，图10a和图10b示出了将图3的芯片膜模块120集成到印刷电路板142中。这里，图10a示出了嵌入到印刷电路板142中的芯片膜模块(例如，内插器)。图10b示例性地示出了如何将导体路径路由到印刷电路板142中的不同平面以及如何在各个导体路径平面之间实现电接触(通孔)。
在图10a和图10b所示的实施例中，印刷电路板技术的通孔接触部144_1和144_2终止于芯片膜模块120(例如，膜内插器)的接触焊盘126_1和126_2上。例如，这些通孔144_1和144_2可以通过机械钻孔或激光钻孔产生。然后，为该开口通孔提供金属化层，并且通常通过电镀工艺用铜对其进行填充。
图11示出了根据第二实施例的具有印刷电路板142和嵌入到印刷电路板142中的图4的芯片膜模块(集成到PCB中的图4的芯片膜内插器)的微电子装置140的示意性横截面视图。如可以在图11中看出的，印刷电路板142可以包括芯片膜模块120(例如，完全地)嵌入到其中的若干层压平面146_1-146_4。如可以在图11中看出的，芯片膜模块120的至少两个端子126_1和126_2(耦合元件)可以连接到印刷电路板142的至少两个通孔144_1和144_2(对应耦合元件)。这里，该至少两个通孔144_1和144_2可以竖直地延伸穿过膜衬底124或穿过嵌入层132到膜衬底124的至少两个端子126_1和126_2。
换句话说，图11示出了将图4所示的芯片膜模块120集成到印刷电路板中。在这种情况下，印刷电路板技术的通孔144_1和144_2可以穿透印刷电路板的层压平面和芯片膜模块120(膜内插器)的芯片嵌入材料132或芯片膜模块120(例如，内插器)的衬底膜124(当从下侧接触时)。
图12示出了根据第三实施例的具有印刷电路板142和嵌入到印刷电路板142中的图5的芯片膜模块(集成到PCB中的图5的芯片膜内插器)的微电子装置140的示意性横截面视图。如可以在图12中看出的，印刷电路板142可以包括芯片膜模块120(例如，完全地)嵌入到其中的若干层压平面146_1-146_4。如可以在图12中进一步看出的，经由至少两个通孔134_1和134_2朝向外部路由的芯片膜模块120的至少两个端子126_1和126_2(耦合元件)可以连接到印刷电路板142的至少两个通孔144_1和144_2(对应耦合元件)。
换句话说，图12示出了图5所示的芯片膜模块120(例如，内插器)的集成。在这种情况下，印刷电路板技术的通孔144_1和144_2终止于芯片膜模块120的外部接触区域134_1和134_2上。
图13示出了根据第四实施例的具有印刷电路板142和嵌入到印刷电路板142中的图6的芯片膜模块(集成到PCB中的图6的芯片膜内插器)的微电子装置140的示意性横截面视图。如可以在图13中看出的，印刷电路板142可以包括芯片膜模块120(例如，完全地)嵌入到其中的若干层压平面146_1-146_4。如可以在图13中进一步看出的，印刷电路板可以包括竖直地耦合到芯片膜模块120的至少两个耦合元件126_1和126_2的至少两个耦合对应元件144_1和144_2。耦合对应元件可以是光学耦合元件，例如LED和/或光电二极管。附加地或备选地，耦合对应元件可以是电感、电容或电磁耦合元件，例如导体环、线圈、电容器板和/或天线。
换句话说，图13示出了图6所示的芯片膜模块120(例如，内插器)的集成。在这种情况下，在印刷电路板142的导体路径与半导体芯片122(例如，芯片组件)之间没有通电耦合。相反，提供在印刷电路板142的导体路径与芯片膜模块120的导体路径之间的天线或光电信号耦合。耦合装置(耦合元件126_1和126_2以及耦合对应元件144_1和144_2)将以互补的方式来实现，即，天线对天线，以及LED对光电管。
图14示出了根据第五实施例的具有印刷电路板142和嵌入到印刷电路板142中的图7的芯片膜模块(集成到PCB中的图7的芯片膜内插器)的微电子装置140的示意性横截面视图。如可以在图14中看出的，印刷电路板142可以包括芯片膜模块120(例如，完全地)嵌入到其中的若干层压平面146_1-146_4。如可以在图14中进一步看出的，芯片膜模块120的形成至少两个电端子的至少两条导体路径130_1和130_2可以由印刷电路板142的至少两个通孔144_1和144_2耦合。
换句话说，图14示出了图7所示的芯片膜模块120(例如，内插器)的集成。
图15a示出了根据第六实施例的具有印刷电路板142和嵌入到印刷电路板142中的图8的芯片膜模块(集成到PCB中的图8的芯片膜内插器)的微电子装置140的示意性横截面视图。如可以在图15a中看出的，芯片膜模块120的形成至少两个电端子的至少两条导体路径130_1和130_2可以由印刷电路板142的至少两个通孔144_1和144_2耦合。如可以在图15a中进一步看出的，印刷电路板142可以包括若干层压平面146_1-146_3，芯片膜模块120嵌入到这些层压平面中，使得芯片膜模块120的导热膜衬底124被暴露出，即，不被嵌入(例如，基本上以与印刷电路板142的表面(例如，底面)齐平的方式终止)。备选地，芯片膜模块120也可以例如通过另外的层压平面146_4完全地嵌入到印刷电路板142中，如图15b所示，其中，印刷电路板142包括与导热膜衬底124相邻的(例如，在第四层压平面146_4内)热通孔137，其被配置为将热能从导热膜衬底124传导到印刷电路板142的周围区域。
换句话说，图15a和图15b示出了图8所示的芯片膜模块120(例如，内插器)的集成，其中，基膜124是导热膜，例如铜膜。为此，示出了两种可能的变型：在完全集成到印刷电路板142(PCB)中之后，芯片膜模块120(例如，内插器)的导热膜(例如，Cu膜)在其背面处保持开口；因此，它可以焊接到另外的衬底(这里未示出)上或可以与空气冷却器或液体冷却器接触。第二实施方式：芯片膜模块120完全地嵌入到印刷电路板142(PCB)中。为了仍然保持尽可能高的热消散，优选地利用金属连接技术(焊接、烧结)或诸如石墨、氮化铝等的高导热材料在芯片膜模块120(例如，内插器)下创建所谓的热通孔137。
图16示出了根据第七实施例的具有印刷电路板142和嵌入到印刷电路板142中的任意芯片膜模块120的微电子装置140的示意性横截面视图。如可以在图16中看出的，印刷电路板142可以包括芯片膜模块120(例如，完全地)嵌入到其中的若干层压平面146_1-146_5。如可以在图16中进一步看出的，印刷电路板142可以包括至少两个导体路径平面149_1和149_2，其中，芯片膜模块120布置在该至少两个导体路径平面149_1和149_2之间，其中，在将芯片膜模块120嵌入到印刷电路板142中时，形成穿过芯片膜模块120的竖直通孔139，用于连接至少两个导体路径平面149_1和149_2的导体路径147_1和147_2。
换句话说，图16示出了将任意芯片膜模块120(例如，图3至图9所示的芯片膜模块)集成到印刷电路板142中。在图16所示的实施例中，将印刷电路板(PCB)技术的通孔139路由穿过芯片膜模块120(例如，膜内插器)而不与芯片膜模块120的导体路径电接触。芯片膜模块上的不与半导体芯片122(例如，半导体组件)接触的布线路径也可以与印刷电路板142的布线路径相组合。这具有以下优点：例如，芯片膜模块120的表面积对于实现布线(也被称为“路由”)而言没有损失。即使有芯片膜模块120，也可以在印刷电路板142(PCB)上实现高密度布线。另外，可以在电路架构中规划和实现安全布线构思，例如通过在芯片膜模块120上映射整个系统的布线的一部分以及在印刷电路板(PCB)布局中映射另一部分。这提供了关于系统的虚假安全的新的可能性。例如：IC设计、内插器设计和PCB设计由不同的提供商实现；只有客户对整个系统的必要接触路径和功能有充分的了解。因此，严重地阻碍了整个电系统的再现或复制。
图17示出了根据第八实施例的具有印刷电路板142和嵌入到印刷电路板142中的两个任意芯片膜模块120的微电子装置140的示意性横截面视图。如可以在图17中看出的，两个芯片膜模块120可以沿印刷电路板142的竖直方向堆叠，并且可以通过若干层压平面146_1-146_8完全地嵌入到印刷电路板142中。
换句话说，图17示出了芯片膜模块120(例如，膜内插器)三维多重地集成到印刷电路板142中的可能性。这仅在因为基于薄膜的芯片膜模块120具有良好的可集成性和可堆叠性时是可能的。
图18示出了根据第九实施例的具有印刷电路板142和嵌入到印刷电路板142中的图9的芯片膜模块120(集成到PCB中的图9的芯片膜内插器)的微电子装置140的示意性横截面视图。如可以在图18中看出的，芯片膜模块120可以例如通过若干层压平面146_1-146_6完全地嵌入到印刷电路板120中。如可以在图18中进一步看出的，印刷电路板142可以包括若干多层的再分布152_1-152_4。
换句话说，图18示出了将图9所示的芯片膜模块120(例如，内插器)集成到印刷电路板142中，印刷电路板142本身已经包括膜内插器上或膜内插器中的多层再分布。
图9或图18的芯片膜模块120是特别有利的，因为它可以用于将具有芯片上的许多接触焊盘的半导体组件(例如，处理器)集成到芯片膜模块120中。继而，这是芯片膜模块120的特定特征，因为在聚合物层上可以容易地在技术上实现若干层的结构。
下面描述本发明的实施例的优点。
在实施例中，半导体芯片(例如，半导体组件)上的非常小的接触焊盘的所需扩展在芯片膜模块(膜内插器)上实现，并且具有足够稳定(＝厚)的金属化的接触焊盘的实现(例如，厚度为2-5μm的铜焊盘，还可能具有作为氧化保护的镀金)也是如此。因此，省略的是在晶片工厂中半导体芯片的起始晶片上的再分布平面的技术实现，传统情况即是如此。
在具有成本效益的大幅面衬底膜上制造芯片膜模块(例如，膜内插器)所需的附加方法步骤继而可以在洁净实验室中用简化的工艺技术(而不是在晶片工厂的昂贵超净间中用亚微米工艺技术)大规模地执行，并且因此以具有成本效益的多用途和自动化的方式执行。特别地，卷对卷工艺技术可以用于在膜衬底上制造导体路径以及用于安装未封装的芯片(从晶片复合物中自动拾取和放置)。在某种程度上，该中间步骤是洁净实验室(不一定是晶片工厂的超净间)中的高分辨率光刻工艺和传统印刷电路板生产中相当简单的工艺环境之间的折衷。
印刷电路板工厂中的薄半导体芯片(例如，半导体组件)的处理存在极大的挑战，因为未封装的薄芯片非常易于破损。另一方面，芯片膜模块(例如，膜内插器)为半导体芯片(例如，IC组件)提供了良好的保护，因此，可以在PCB制造中使用快速且鲁棒地实现的工艺和机器。
芯片膜模块(例如，内插器)上和印刷电路板平面上的布线结构(布局)的组合实现了需要保护的电子设备的新的安全特征(例如，密码服务器、编码方法、复制保护、原创性证明)。另请参见关于图16的说明。
该方法在系统架构中实现了更高的集成密度，因为它实现了若干半导体芯片(例如，IC组件)之间的更短的连接路径，特别是在三维堆叠的芯片膜模块中。
为了三维集成/高集成密度的目的，相比于基于晶片工厂基础结构及其昂贵的工艺技术的基于晶片的集成技术，该方法使用更简单、更便宜且容易获得的工艺技术。
即使已经在设备的上下文中描述了一些方面，也应当理解，所述方面还表示对相应方法的描述，使得设备的框或结构组件也将被理解为相应的方法步骤或方法步骤的特征。以此类推，在方法步骤的上下文中或作为方法步骤已经描述的方面也表示对相应设备的相应框或细节或特征的描述。可以在使用硬件设备(例如，微处理器、可编程计算机或电子电路)时执行一些或全部方法步骤。在一些实施例中，一些或若干最重要的方法步骤可以由这样的设备执行。
上述实施例仅表示对本发明的原理的说明。应当理解，本领域的其他技术人员将认识到本文描述的布置和细节的修改和变化。这即是意图本发明仅由所附权利要求的范围限制，而不由本文通过实施例的描述和讨论而给出的具体细节限制的原因。

Claims (30)

1.一种用于制造微电子装置(140)的方法(100)，包括：
提供(102)具有半导体芯片(122)和膜衬底(124)的芯片膜模块(120)，所述半导体芯片(122)被布置在所述膜衬底(124)上，其中，所述芯片膜模块(120)包括与所述半导体芯片(122)间隔开并且电耦合到所述半导体芯片(122)的至少一个端子(128；128_1-128_2)的至少一个耦合元件(126；126_1、126_2)；以及
将所述芯片膜模块(120)嵌入(104)到印刷电路板(142)中，其中，在将所述芯片膜模块(120)嵌入到所述印刷电路板(142)中时，所述芯片膜模块(120)的所述至少一个耦合元件(126；126_1、126_2)竖直地耦合到所述印刷电路板(142)的至少一个耦合对应元件(144；144_1、144_2)。
2.根据权利要求1所述的方法(100)，
其中，所述芯片膜模块(120)的所述至少一个耦合元件(126；126_1、126_2)中的至少一个耦合元件是电端子，
其中，所述印刷电路板(142)的所述至少一个耦合对应元件(144；144_1、144_2)中的至少一个耦合对应元件是通孔。
3.根据权利要求2所述的方法(100)，
其中，所述芯片膜模块(120)的所述端子的端子面积大于所述半导体芯片(122)的所述端子(128；128_1-128_2)的端子面积，
和/或其中，所述芯片膜模块(120)的端子之间的距离大于所述半导体芯片(122)的端子(128；128_1-128_2)之间的距离。
4.根据权利要求1所述的方法(100)，
其中，所述芯片膜模块(120)的所述至少一个耦合元件(126；126_1、126_2)中的至少一个耦合元件是光学耦合元件，
其中，所述印刷电路板(142)的所述至少一个耦合对应元件(144；144_1、144_2)中的至少一个耦合对应元件是光学耦合对应元件。
5.根据权利要求1所述的方法(100)，
其中，所述芯片膜模块(120)的所述至少一个耦合元件(126；126_1、126_2)中的至少一个耦合元件是电感或电容耦合元件，
其中，所述印刷电路板(142)的所述至少一个耦合对应元件(144；144_1、144_2)中的至少一个耦合对应元件是电感或电容耦合对应元件。
6.根据权利要求1所述的方法(100)，其中，所述半导体芯片(122)嵌入到所述芯片膜模块(120)中。
7.根据权利要求1所述的方法(100)，
其中，所述至少一个耦合元件(126；126_1、126_2)布置在所述膜衬底(124)上或所述膜衬底(124)中并且经由形成在所述膜衬底(124)上或所述膜衬底(124)中的至少一条导体路径(130；130_1-130_2)连接到所述半导体芯片(122)的所述至少一个端子(128；128_1-128_2)。
8.根据权利要求1所述的方法(100)，
其中，所述半导体芯片(122)布置在所述膜衬底(124)上，使得所述半导体芯片(122)的所述至少一个端子(128；128_1-128_2)背对所述膜衬底(124)，
其中，所述至少一个耦合元件(126；126_1、126_2)布置在所述芯片膜模块(120)的所述半导体芯片(122)被嵌入的嵌入层(132)中或嵌入层(132)上，
其中，所述至少一个耦合元件(126；126_1、126_2)经由竖直电连接(131_1-131_2)连接到所述半导体芯片(122)的所述至少一个端子(128；128_1-128_2)。
9.根据权利要求1所述的方法(100)，
其中，所述膜衬底(124)包括经由形成在所述膜衬底(124)中或所述膜衬底(124)上的至少两条导体路径(130_1、130_2)连接到所述半导体芯片(122)的至少两个端子(128_1-128_2)的至少两个端子元件(125_1-125_2)，
其中，所述芯片膜模块(120)包括位于彼此上方或以堆叠方式设置的至少两个嵌入层(130_1、130_2、……)，所述嵌入层中嵌入所述半导体芯片(122)和/或所述膜衬底(124)，
其中，所述芯片膜模块(120)包括布置在所述至少两个嵌入层(130_1、130_2、……)中的不同嵌入层中或不同嵌入层上的至少两个耦合元件(126_1、126_2)，
其中，所述至少两个耦合元件(126_1、126_2)经由竖直电连接(134_1-124_2)连接到所述膜衬底(124)的所述至少两个端子元件(125_1-125_2)。
10.根据权利要求1所述的方法(100)，
其中，所述印刷电路板(142)包括所述芯片膜模块(120)被嵌入的至少两个层压平面(144_1、144_2、……)。
11.根据权利要求1所述的方法(100)，
其中，所述半导体芯片(122)经由所述芯片膜模块(120)的所述至少一个耦合元件(126；126_1、126_2)和所述印刷电路板(142)的所述至少一个耦合对应元件(144；144_1、144_2)连接到所述印刷电路板(142)的至少一个电路组件(50)。
12.根据权利要求1所述的方法(100)，
其中，提供(102)所述芯片膜模块(120)的步骤包括：
提供所述半导体芯片(122)；
提供所述膜衬底(124)；
将所述半导体芯片(122)连接到所述膜衬底(124)。
13.根据权利要求12所述的方法(100)，
其中，提供(102)所述芯片膜模块(120)的步骤还包括：
将所述半导体芯片(122)嵌入到嵌入层中。
14.根据权利要求1所述的方法(100)，
其中，将所述芯片膜模块(120)嵌入(104)到所述印刷电路板(142)中的步骤包括：
提供所述印刷电路板(142)的至少一个层压平面；
将所述芯片膜模块(120)布置在所述印刷电路板(142)的所述至少一个层压平面上或所述印刷电路板(142)的所述至少一个层压平面内；
在所述印刷电路板(142)的所述至少一个层压平面上和/或下提供所述印刷电路板(142)的至少一个另外的层压平面，使得所述芯片膜模块(120)嵌入到所述印刷电路板(142)中。
15.根据权利要求1所述的方法(100)，
其中，所述膜衬底(124)包括与所述半导体芯片(122)间隔开并且经由形成在所述膜衬底(124)中或所述膜衬底(124)上的两条导体路径(130_1、130_2)连接到所述半导体芯片(122)的至少两个端子(128_1、128_2)的至少两个耦合元件(126_1、126_2)，
其中，所述至少两个耦合元件(126_1、126_2)是电端子，
其中，所述印刷电路板(142)的导体路径经由作为对应耦合元件(144_1、144_2)的至少两个通孔连接到所述膜衬底(124)的所述端子。
16.根据权利要求15所述的方法(100)，
其中，所述半导体芯片(122)在布置在所述膜衬底(124)上的嵌入层(132)中嵌入到所述芯片膜模块(120)中。
17.根据权利要求16所述的方法(100)，
其中，所述至少两个通孔竖直地延伸穿过所述膜衬底(124)或穿过所述嵌入层(132)到所述膜衬底(124)的所述至少两个端子。
18.根据权利要求16所述的方法(100)，
其中，从所述印刷电路板(142)的第一平面开始，所述至少两个通孔中的第一通孔竖直地延伸穿过所述膜衬底(124)到所述膜衬底(124)的所述至少两个端子(125_1、125_2)中的第一端子(125_1)，
和/或其中，从所述印刷电路板(142)的第二平面开始，所述至少两个通孔中的第二通孔竖直地延伸穿过所述芯片膜模块(120)的所述嵌入层到所述膜衬底(124)的所述至少两个端子(125_1、125_2)中的第二端子(125_2)。
19.根据权利要求1所述的方法(100)，
其中，所述至少一个耦合元件(126；126_1、126_2)布置在所述膜衬底(124)上或所述膜衬底(124)中并且经由形成在所述膜衬底(124)上或所述膜衬底(124)中的至少一条导体路径(130_1)连接到所述半导体芯片(122)的所述至少一个端子(128；128_1-128_2)，
其中，所述膜衬底(124)的所述至少一个耦合元件(126；126_1、126_2)中的至少一个耦合元件(126_1)是光学耦合元件，其中，所述印刷电路板(142)的所述至少一个耦合对应元件(144；144_1、144_2)中的至少一个耦合对应元件(144_1)是光学耦合对应元件，其中，所述光学耦合元件和所述光学耦合对应元件沿竖直方向彼此光学地耦合。
20.根据权利要求19所述的方法(100)，
其中，所述至少一个耦合元件(126；126_1、126_2)中的至少一个另外的耦合元件(126_2)布置在所述膜衬底(124)上或所述膜衬底(124)中并且经由形成在所述膜衬底(124)上或所述膜衬底(124)中的至少一条另外的导体路径(130_2)连接到所述半导体芯片(122)的至少一个另外的端子(128_2)，
其中，所述至少一个另外的耦合元件(126_2)是电感或电容耦合元件，其中，所述印刷电路板(142)的所述至少一个耦合对应元件(144；144_1、144_2)中的至少一个另外的耦合对应元件(144_2)是电感或电容耦合对应元件，其中，所述电感或电容耦合元件和所述电感或电容耦合对应元件沿所述竖直方向彼此电感或电容地耦合。
21.根据权利要求1所述的方法(100)，
其中，所述芯片膜模块(120)包括至少两个耦合元件(126_1、126_2)，
其中，所述半导体芯片(122)包括至少两个端子(128_2、128_2)，
其中，所述半导体芯片(122)布置在所述膜衬底(124)上，使得所述半导体芯片(122)的所述至少两个端子(128_2、128_2)背对所述膜衬底(124)，
其中，所述至少两个耦合元件(126_1、126_2)布置在所述芯片膜模块(120)的所述半导体芯片(122)被嵌入的嵌入层(132)中或嵌入层(132)上，
其中，所述至少两个耦合元件(126_1、126_2)经由竖直电连接(131_1-131_2)连接到所述半导体芯片(122)的所述至少两个端子，
其中，所述至少两个耦合元件(126_1、126_2)是电端子，
其中，所述印刷电路板(142)的导体路径经由作为对应耦合元件(144_1、144_2)的至少两个通孔连接到所述芯片膜模块(120)的所述至少两个端子。
22.根据权利要求21所述的方法(100)，
其中，所述膜衬底(124)是导热膜衬底(124)，
其中，所述印刷电路板(142)包括与所述导热膜衬底(124)相邻的热通孔(137)，其被配置为将热能从所述导热膜衬底(124)传导到所述印刷电路板(142)的周围区域。
23.根据权利要求1所述的方法(100)，
其中，所述膜衬底(124)包括经由形成在所述膜衬底(124)中或所述膜衬底(124)上的至少两条导体路径(130_1、130_2)连接到所述半导体芯片(122)的至少两个端子(128_1、128_2)的两个端子元件(125_1-125_2)，
其中，所述芯片膜模块(120)包括位于彼此上方或以堆叠方式设置的两个嵌入层(130_1、130_2、……)，所述嵌入层中嵌入所述半导体芯片(122)和/或所述膜衬底(124)，
其中，所述芯片膜模块(120)包括布置在所述至少两个嵌入层(130_1、130_2、……)中的不同嵌入层中或不同嵌入层上的至少两个耦合元件(126_1、126_2)，
其中，所述至少两个耦合元件(126_1、126_2)经由竖直电连接(134_1-134_2)连接到所述膜衬底(124)的所述至少两个端子元件(125_1-125_2)，
其中，所述至少两个耦合元件(126_1、126_2)是电端子，
其中，所述印刷电路板(142)的导体路径经由作为对应耦合元件(144_1、144_2)的至少两个通孔连接到所述芯片膜模块(120)的所述至少两个端子，
其中，从所述印刷电路板(142)的第一平面开始，所述至少两个通孔中的第一通孔竖直地延伸到所述芯片膜模块(120)的所述至少两个端子中的第一端子，
其中，从所述印刷电路板(142)的第二平面开始，所述至少两个通孔中的第二通孔竖直地延伸到所述膜衬底(124)的所述至少两个端子中的第二端子。
24.根据权利要求1所述的方法(100)，
其中，所述方法(100)包括提供具有另外的半导体芯片(122)和另外的膜衬底(124)的另外的芯片膜模块(120)的步骤，所述另外的半导体芯片(122)被布置在所述另外的膜衬底(124)上，其中，所述另外的芯片膜模块(120)包括与所述另外的半导体芯片(122)间隔开并且耦合到所述另外的半导体芯片(122)的至少一个端子(128；128_1-128_2)的至少一个耦合元件(126；126_1、126_2)，以及
其中，所述方法(100)包括将所述另外的芯片膜模块(120)嵌入到所述印刷电路板(142)中的步骤，其中，在将所述另外的芯片膜模块(120)嵌入到所述印刷电路板(142)中时，所述另外的芯片膜模块(120)的所述至少一个耦合元件(126；126_1、126_2)竖直地耦合到所述印刷电路板(142)的所述至少一个另外的耦合对应元件(144；144_1、144_2)，
其中，所述芯片膜模块(120)和所述另外的芯片膜模块(120)在所述印刷电路板(142)的竖直方向上堆叠。
25.根据权利要求1所述的方法(100)，
其中，所述印刷电路板(142)包括至少两个导体路径平面，
其中，所述芯片膜模块(120)布置在所述至少两个导体路径平面(149_1、149_2)之间，
其中，在将所述芯片膜模块(120)嵌入到所述印刷电路板(142)中时，穿过所述芯片膜模块(120)形成竖直通孔，用于连接所述至少两个导体路径平面(149_1、149_2)的导体路径。
26.一种微电子装置(140)，包括：
印刷电路板(142)；以及
芯片膜模块(120)，
其中，所述芯片膜模块(120)包括半导体芯片(122)和膜衬底(124)，所述半导体芯片(122)被布置在所述膜衬底(124)上，
其中，所述芯片膜模块(120)包括与所述半导体芯片(122)间隔开并且电耦合到所述半导体芯片(122)的所述至少一个端子(128；128_1-128_2)的至少一个耦合元件(126；126_1、126_2)，
其中，所述芯片膜模块(120)嵌入到所述印制电路板(142)中，
其中，所述芯片膜模块(120)的所述至少一个耦合元件(126；126_1、126_2)竖直地耦合到所述印刷电路板(142)的至少一个耦合对应元件(144；144_1、144_2)。
27.一种芯片膜模块(120)，包括：
膜衬底(124)；
布置在所述膜衬底(124)上的半导体芯片；
与所述半导体芯片(122)间隔开并且布置在所述膜衬底(124)上或所述膜衬底(124)中的至少一个耦合元件，
其中，所述至少一个耦合元件(126；126_1、126_2)经由形成在所述膜衬底(124)上或所述膜衬底(124)中的至少一条导体路径电耦合到所述半导体芯片(122)的至少一个端子(128；128_1-128_2)，
其中，所述至少一个耦合元件(126；126_1、126_2)被配置为耦合到至少一个外部对应耦合元件(144；144_1、144_2)，
其中，所述芯片膜模块(120)包括布置在所述膜衬底(124)上的嵌入层，其中，所述嵌入层中完全地嵌入所述半导体芯片(122)和所述至少一个耦合元件(126；126_1、126_2)，
其中，所述至少一个耦合元件(126；126_1、126_2)是电端子。
28.一种芯片膜模块(120)，包括：
膜衬底(124)；
布置在所述膜衬底(124)上的半导体芯片；
与所述半导体芯片(122)间隔开并且布置在所述膜衬底(124)上或所述膜衬底(124)中的至少一个耦合元件，
其中，所述至少一个耦合元件(126；126_1、126_2)经由形成在所述膜衬底(124)上或所述膜衬底(124)中的至少一条导体路径电耦合到所述半导体芯片(122)的至少一个端子(128；128_1-128_2)，
其中，所述至少一个耦合元件(126；126_1、126_2)被配置为耦合到至少一个外部对应耦合元件(144；144_1、144_2)，
其中，所述芯片膜模块(120)包括布置在所述膜衬底(124)上的嵌入层，其中，所述嵌入层中完全地嵌入所述半导体芯片(122)和所述至少一个耦合元件(126；126_1、126_2)，
其中，所述至少一个耦合元件(126；126_1、126_2)是光学耦合元件(126；126_1、126_2)。
29.一种芯片膜模块(120)，包括：
膜衬底(124)；
布置在所述膜衬底(124)上的半导体芯片；
与所述半导体芯片(122)间隔开的至少两个耦合元件，
其中，所述膜衬底(124)包括经由形成在所述膜衬底(124)中或所述膜衬底(124)上的至少两条导体路径连接到所述半导体芯片(122)的至少两个端子的至少两个端子元件，
其中，所述芯片膜模块(120)包括位于彼此上方或以堆叠方式设置的至少两个嵌入层，所述嵌入层中嵌入所述半导体芯片(122)和/或所述膜衬底(124)，
其中，所述至少两个耦合元件布置在所述至少两个嵌入层中的不同嵌入层中或不同嵌入层上，
其中，所述至少两个耦合元件经由竖直电连接来连接到所述膜衬底(124)的所述至少两个端子元件，
其中，所述至少两个耦合元件(126；126_1、126_2)被配置为耦合到至少两个外部对应耦合元件。
30.一种微电子装置(140)，包括：
印刷电路板(142)以及根据权利要求27所述的芯片膜模块(120)，
其中，所述芯片膜模块嵌入到所述印刷电路板(142)中，
其中，所述芯片膜模块(120)的所述至少一个耦合元件(126；126_1、126_2)竖直地耦合到所述印刷电路板(142)的至少一个耦合对应元件(144；144_1、144_2)。
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