CN113614912A - 封装结构、电子设备及其制备方法 - Google Patents
封装结构、电子设备及其制备方法 Download PDFInfo
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- CN113614912A CN113614912A CN201980094673.9A CN201980094673A CN113614912A CN 113614912 A CN113614912 A CN 113614912A CN 201980094673 A CN201980094673 A CN 201980094673A CN 113614912 A CN113614912 A CN 113614912A
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- auxiliary
- pads
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- 230000003014 reinforcing effect Effects 0.000 claims abstract description 106
- 238000000034 method Methods 0.000 claims abstract description 104
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- 238000005192 partition Methods 0.000 claims description 128
- 238000004891 communication Methods 0.000 claims description 41
- 239000000463 material Substances 0.000 claims description 30
- 238000004519 manufacturing process Methods 0.000 claims description 28
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- 125000006850 spacer group Chemical group 0.000 claims description 18
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- 230000002349 favourable effect Effects 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
本申请实施例提供一种封装结构，包括封装基板和芯片，所述封装基板包括相对设置的封装面和底面，所述芯片设置于所述封装面上，所述底面上设置有N个焊盘，至少两个相邻且电气属性相同的所述焊盘之间通过导电片连接，以形成加强焊盘。上述封装结构与电路板组装时，与所述加强焊盘相对应的焊球受热变形彼此连接形成覆盖所述加强焊盘的大体积焊球，大体积焊球具有较好的疲劳强度，在所述封装结构和电路板组装后在进行温度循环测试或者使用过程中，大体积焊球能均匀地分散其所承受的应力，不易产生疲劳裂纹而断裂，有效提高了所述封装结构和电路板组装后的板级可靠性。本申请实施例还提供一种电子设备及其制备方法。
Description
PCT国内申请，说明书已公开。
Claims (33)
- PCT国内申请，权利要求书已公开。
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2019/080669 WO2020199039A1 (zh) | 2019-03-29 | 2019-03-29 | 封装结构、电子设备及其制备方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113614912A true CN113614912A (zh) | 2021-11-05 |
Family
ID=72664838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201980094673.9A Pending CN113614912A (zh) | 2019-03-29 | 2019-03-29 | 封装结构、电子设备及其制备方法 |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN113614912A (zh) |
| WO (1) | WO2020199039A1 (zh) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114512463A (zh) * | 2022-02-18 | 2022-05-17 | 维沃移动通信有限公司 | 芯片组件及电子设备 |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112271170B (zh) * | 2020-10-27 | 2024-08-09 | 苏州通富超威半导体有限公司 | 封装基板、倒装芯片封装结构及其制作方法 |
| CN116888728A (zh) * | 2021-04-29 | 2023-10-13 | 华为技术有限公司 | 电路板装配件和电子设备 |
| CN116705740B (zh) * | 2022-09-05 | 2024-08-16 | 荣耀终端有限公司 | 一种芯片、芯片封装结构、芯片封装方法及电子设备 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000243775A (ja) * | 1999-02-22 | 2000-09-08 | Motorola Inc | 半導体素子におけるはんだ接合部の疲労寿命を延長させる方法および装置 |
| US20020104874A1 (en) * | 2001-02-05 | 2002-08-08 | Samsung Electronics Co., Ltd. | Semiconductor chip package comprising enhanced pads |
| CN104952746A (zh) * | 2014-02-27 | 2015-09-30 | 英飞凌科技股份有限公司 | 将半导体封装连接到板的方法 |
| CN108260277A (zh) * | 2018-01-10 | 2018-07-06 | 广东欧珀移动通信有限公司 | 背光电路、电路板及电子设备 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100720143B1 (ko) * | 2005-12-13 | 2007-05-18 | 삼성전자주식회사 | 디스플레이장치 |
| CN202931666U (zh) * | 2012-10-26 | 2013-05-08 | 比亚迪股份有限公司 | 一种印刷电路板及应用其的移动终端 |
| CN205720974U (zh) * | 2016-06-13 | 2016-11-23 | 创维液晶器件(深圳)有限公司 | 一种散热式fpc组件、液晶显示屏及智能终端 |
-
2019
- 2019-03-29 CN CN201980094673.9A patent/CN113614912A/zh active Pending
- 2019-03-29 WO PCT/CN2019/080669 patent/WO2020199039A1/zh active Application Filing
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000243775A (ja) * | 1999-02-22 | 2000-09-08 | Motorola Inc | 半導体素子におけるはんだ接合部の疲労寿命を延長させる方法および装置 |
| US20020104874A1 (en) * | 2001-02-05 | 2002-08-08 | Samsung Electronics Co., Ltd. | Semiconductor chip package comprising enhanced pads |
| CN104952746A (zh) * | 2014-02-27 | 2015-09-30 | 英飞凌科技股份有限公司 | 将半导体封装连接到板的方法 |
| CN108260277A (zh) * | 2018-01-10 | 2018-07-06 | 广东欧珀移动通信有限公司 | 背光电路、电路板及电子设备 |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114512463A (zh) * | 2022-02-18 | 2022-05-17 | 维沃移动通信有限公司 | 芯片组件及电子设备 |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020199039A1 (zh) | 2020-10-08 |
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