CN113363318A - N沟道的平面型vdmos和平面型igbt - Google Patents

N沟道的平面型vdmos和平面型igbt Download PDF

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CN113363318A
CN113363318A CN202010148530.6A CN202010148530A CN113363318A CN 113363318 A CN113363318 A CN 113363318A CN 202010148530 A CN202010148530 A CN 202010148530A CN 113363318 A CN113363318 A CN 113363318A
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王学良
闵亚能
刘建华
郎金荣
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GTA Semiconductor Co Ltd
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Abstract

本发明公开了一种N沟道的平面型VDMOS和平面型IGBT，其中，N沟道的平面型VDMOS包括p阱区，所述p阱区的沟道内埋有至少一个n岛，所述n岛为n型区，所述n型区采用n型半导体元素形成。本发明提供的N沟道的平面型VDMOS和平面型IGBT，通过在器件的p阱区的沟道内埋设n岛，能够有效调整器件的Vth的范围并且一致性更好。n岛的数量取决于具体的应用需求，相对而言，埋入的n岛的数量越多，器件的Vth值越低。

Description

N沟道的平面型VDMOS和平面型IGBT
技术领域
本发明属于集成电路技术领域，特别涉及一种N沟道的平面型VDMOS(verticaldouble-diffused metal oxide semiconductor field effect transistor，垂直双扩散金属氧化物半导体场效应晶体管)和平面型IGBT(Insulated Gate Bipolar Transistor，绝缘栅双极型晶体管)。
背景技术
图1为现有技术中N沟道的平面型VDMOS的元胞结构的切面示意图，包括Gate(栅极)、Source(源级)、Drain(漏极)。另外，从下至上还依次包括n+区、n-drift(n-漂移区)、对称的p+体区，位于p+体区中的p阱以及n+源区。
图2为现有技术中N沟道的平面型IGBT的元胞结构的切面示意图，包括Gate(栅极)、Cathode(阴极)、Anode(阳极)，从下至上还依次包括p+区、n-drift、对称的p+体区，位于p+体区中的p阱以及n+阴极区。
Vth(开启电压)是VDMOS器件和IGBT器件的一个重要参数，当栅源电压大于Vth时，栅极下面的p阱表面的电子浓度会高于空穴浓度，使得P型半导体反型为N型而形成反型层，从而进一步形成N沟道。如何调节器件的Vth的大小及一致性一直是业界关注的问题。
现有技术中调控Vth大小多从p阱的浓度和栅氧厚度着手。从p阱的浓度调整，其Vth的可调范围受限于LATCH UP(抗闩锁)能力；而从栅氧厚度调节的方式其Vth的可调范围受限于栅氧工艺技术。如何有效调整N沟道的平面型VDMOS和平面型IGBT的Vth的可控范围以及一致性是急需解决的问题。
发明内容
本发明要解决的技术问题是为了克服现有技术中调整N沟道的平面型VDMOS和平面型IGBT的Vth的可控范围以及一致性有待提高的缺陷，提供一种能够有效调整器件的Vth的范围并且一致性更好的N沟道的平面型VDMOS和平面型IGBT。
本发明是通过下述技术方案来解决上述技术问题：
本发明第一方面提供了一种N沟道的平面型VDMOS，包括p阱区，所述p阱区的沟道内埋有至少一个n岛，所述n岛为n型区，所述n型区采用n型半导体元素形成。
本方案中，通过在p阱区的沟道内埋设n岛，能够有效调整器件的Vth的范围并且一致性更好。可以利用器件的不同层的光刻板在适当层制作时形成n岛，也就是说，本方案对n岛的具体制作步骤不作限定，只要最终生成的n岛的位置处于p阱区的沟道内即可。n岛的数量取决于具体的应用需求，相对而言，埋入的n岛的数量越多，N沟道的平面型VDMOS的Vth值越低。一致性一方面体现在同一个晶圆上的N沟道的平面型VDMOS的Vth趋于一致，另外一方面体现在加入n岛的N沟道的平面型VDMOS的Vth值更加符合预期值。
较佳地，所述n型半导体元素包括氢元素、五族元素中的至少一种。
本方案中，n型半导体元素可以为五族元素，如磷、砷等；也可以为氢元素。
较佳地，所述p阱区的沟道内埋有多个所述n岛，多个所述n岛间隔设置。
本方案中，n岛的数量有多个，多个n岛成间隔设置。通过调节n岛之间的间距、元素的剂量以及结深实现对需要的Vth的值的范围及一致性的调节。
较佳地，每个所述n岛采用氢元素、五族元素中的至少一种形成。
本方案中，多个n岛中每个采用的元素可以相同，也可以不相同。
本发明第二方面提供了一种N沟道的平面型IGBT，包括p阱区，所述p阱区的沟道内埋有至少一个n岛，所述n岛为n型区，所述n型区采用n型半导体元素形成。
本方案中，通过在p阱区的沟道内埋设n岛，能够有效调整器件的Vth的范围并且一致性更好。可以利用器件的不同层的光刻板在适当层制作时形成n岛，也就是说，本方案对n岛的具体制作步骤不作限定，只要最终生成的n岛的位置处于p阱区的沟道内即可。n岛的数量取决于具体的应用需求，相对而言，埋入的n岛的数量越多，N沟道的平面型IGBT的Vth值越低。一致性一方面体现在同一个晶圆上的N沟道的平面型IGBT的Vth趋于一致，另外一方面体现在加入n岛的N沟道的平面型IGBT的Vth值更加符合预期值。
较佳地，所述n型半导体元素包括氢元素、五族元素中的至少一种。
本方案中，n型半导体元素可以为五族元素，如磷、砷等；也可以为氢元素。
较佳地，所述p阱区的沟道内埋有多个所述n岛，多个所述n岛间隔设置。
本方案中，n岛的数量有多个，多个n岛成间隔设置。通过调节n岛之间的间距、元素的剂量以及结深实现对需要的Vth的值的范围及一致性的调节。
较佳地，每个所述n岛采用氢元素、五族元素中的至少一种形成。
本方案中，多个n岛中每个采用的元素可以相同，也可以不相同。
本发明的积极进步效果在于：
本发明提供的N沟道的平面型VDMOS和平面型IGBT，通过在器件的p阱区的沟道内埋设n岛，能够有效调整器件的Vth的范围并且一致性更好。n岛的数量取决于具体的应用需求，相对而言，埋入的n岛的数量越多，器件的Vth值越低。
附图说明
图1为现有技术中N沟道的平面型VDMOS的元胞结构的切面示意图。
图2为现有技术中N沟道的平面型IGBT的元胞结构的切面示意图。
图3为本发明实施例1的N沟道的平面型VDMOS的元胞结构的切面示意图。
图4为本发明实施例2的N沟道的平面型IGBT的元胞结构的切面示意图。
具体实施方式
下面通过实施例的方式进一步说明本发明，但并不因此将本发明限制在所述的实施例范围之中。
实施例1
本实施例提供了一种N沟道的平面型VDMOS，图3为该N沟道的平面型VDMOS的元胞结构的切面示意图，包括Gate、Source和Drain，从下至上还依次包括n+区1、n-drift、对称的p+体区2，位于p+体区2中的p阱以及n+源区3。本实施例中，p阱区的沟道内埋有至少一个n岛4，n岛4为n型区，n型区采用n型半导体元素形成。其中，n型半导体元素包括氢元素、五族元素中的至少一种。
本实施例中，n型半导体元素可以为五族元素，如磷、砷等；也可以为氢元素。
本实施例中，p阱区的沟道内埋有多个n岛4，多个n岛4间隔设置。每个n岛4采用氢元素、五族元素中的至少一种形成。通过调节n岛4之间的间距、元素的剂量以及结深实现对需要的Vth的值的范围及一致性的调节。本实施例中，多个n岛4中每个采用的元素可以相同，也可以不相同。
本实施例中，通过在p阱区的沟道内埋设n岛4，能够有效调整器件的Vth的范围并且一致性更好。可以利用器件的不同层的光刻板在适当层制作时形成n岛4，也就是说，本实施例对n岛4的具体制作步骤不作限定，只要最终生成的n岛4的位置处于p阱区的沟道内即可。n岛4的数量取决于具体的应用需求，相对而言，埋入的n岛4的数量越多，N沟道的平面型VDMOS的Vth值越低。一致性一方面体现在同一个晶圆上的N沟道的平面型VDMOS的Vth趋于一致，另外一方面体现在加入n岛4的N沟道的平面型VDMOS的Vth值更加符合预期值。
实施例2
本实施例提供了一种N沟道的平面型IGBT，图4为该N沟道的平面型IGBT的元胞结构的切面示意图，包括Gate、Cathode和Anode，从下至上还依次包括p+区5、n-drift、对称的p+体区6，位于p+体区6中的p阱以及n+阴极区7。本实施例中，p阱区的沟道内埋有至少一个n岛8，n岛8为n型区，n型区采用n型半导体元素形成。其中，n型半导体元素包括氢元素、五族元素中的至少一种。
本实施例中，n型半导体元素可以为五族元素，如磷、砷等；也可以为氢元素。
本实施例中，p阱区的沟道内埋有多个n岛8，多个n岛8间隔设置。每个n岛8采用氢元素、五族元素中的至少一种形成。通过调节n岛8之间的间距、元素的剂量以及结深实现对需要的Vth的值的范围及一致性的调节。本实施例中，多个n岛8中每个采用的元素可以相同，也可以不相同。
本实施例中，通过在p阱区的沟道内埋设n岛8，能够有效调整器件的Vth的范围并且一致性更好。可以利用器件的不同层的光刻板在适当层制作时形成n岛8，也就是说，本实施例对n岛8的具体制作步骤不作限定，只要最终生成的n岛8的位置处于p阱区的沟道内即可。n岛8的数量取决于具体的应用需求，相对而言，埋入的n岛8的数量越多，N沟道的平面型IGBT的Vth值越低。一致性一方面体现在同一个晶圆上的N沟道的平面型IGBT的Vth趋于一致，另外一方面体现在加入n岛8的N沟道的平面型IGBT的Vth值更加符合预期值。
虽然以上描述了本发明的具体实施方式，但是本领域的技术人员应当理解，这仅是举例说明，本发明的保护范围是由所附权利要求书限定的。本领域的技术人员在不背离本发明的原理和实质的前提下，可以对这些实施方式做出多种变更或修改，但这些变更和修改均落入本发明的保护范围。

Claims (8)

1.一种N沟道的平面型VDMOS，包括p阱区，其特征在于，所述p阱区的沟道内埋有至少一个n岛，所述n岛为n型区，所述n型区采用n型半导体元素形成。
2.如权利要求1所述的N沟道的平面型VDMOS，其特征在于，所述n型半导体元素包括氢元素、五族元素中的至少一种。
3.如权利要求1所述的N沟道的平面型VDMOS，其特征在于，所述p阱区的沟道内埋有多个所述n岛，多个所述n岛间隔设置。
4.如权利要求3所述的N沟道的平面型VDMOS，其特征在于，每个所述n岛采用氢元素、五族元素中的至少一种形成。
5.一种N沟道的平面型IGBT，包括p阱区，其特征在于，所述p阱区的沟道内埋有至少一个n岛，所述n岛为n型区，所述n型区采用n型半导体元素形成。
6.如权利要求5所述的N沟道的平面型IGBT，其特征在于，所述n型半导体元素包括氢元素、五族元素中的至少一种。
7.如权利要求5所述的N沟道的平面型IGBT，其特征在于，所述p阱区的沟道内埋有多个所述n岛，多个所述n岛间隔设置。
8.如权利要求7所述的N沟道的平面型IGBT，其特征在于，每个所述n岛采用氢元素、五族元素中的至少一种形成。
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