CN113302718B - 硅外延晶片的制造方法和硅外延晶片 - Google Patents

硅外延晶片的制造方法和硅外延晶片 Download PDF

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CN113302718B
CN113302718B CN201980086166.0A CN201980086166A CN113302718B CN 113302718 B CN113302718 B CN 113302718B CN 201980086166 A CN201980086166 A CN 201980086166A CN 113302718 B CN113302718 B CN 113302718B
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epitaxial layer
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epitaxial
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石桥昌幸
M·吉田
丸冈大介
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Abstract

为了提供可抑制DIC缺陷的硅外延晶片的制造方法和硅外延晶片，本发明提供硅外延晶片的制造方法，所述制造方法是使外延层在以{110}面或自{110}面的偏离角小于1度的面为主面的单晶硅晶片的上述主面上进行气相生长，其中，将上述单晶硅晶片的温度设为1140℃～1165℃，以0.5μm/分钟～1.7μm/分钟的生长速度使上述外延层进行气相生长。

Description

硅外延晶片的制造方法和硅外延晶片
技术领域
本发明涉及硅外延晶片的制造方法和硅外延晶片。
背景技术
已知若使用以{110}面为主面的硅晶片，则在pMOS晶体管中载流子迁移率较以{100}面为主面的晶片高，因此可使pMOS晶体管高速化。另一方面，外延晶片因外延层的缺陷非常少，而被用作高性能器件的原材料。因此，以{110}面为主面的外延晶片被期待作为MPU等的高性能器件的原材料(专利文献1)。
现有技术文献
专利文献
专利文献1：日本特开2009-302140号公报。
发明内容
发明所要解决的课题
然而，在以{110}面为主面的外延晶片中，存在以下问题：容易产生因外延生长而形成的宽度为100μm左右、高度为10nm左右的表面凹凸形状的台阶状微小缺陷，通过微分干涉相衬(Differential Interference Contrast，DIC)法检测出的DIC缺陷变大。需要说明的是，DIC法是可检测出晶片表面的高度或深度超过规定的阈值、例如2nm的凹凸形状的台阶状微小缺陷的个数的方法，这种台阶状微小缺陷是宽度为30～200μm、高度为2～90nm左右的缺陷，是在其他检测模式下不易检测出的缺陷。
本发明所要解决的课题在于：提供可抑制DIC缺陷的硅外延晶片的制造方法和硅外延晶片。
用于解决课题的手段
本发明为硅外延晶片的制造方法，所述硅外延晶片的制造方法是使外延层在以{110}面或自{110}面的偏离角(off angle)小于1度的面为主面的单晶硅晶片的上述主面上进行气相生长，
其中，将上述单晶硅晶片的温度设为1140℃～1165℃，以0.5μm/分钟～1.7μm/分钟的生长速度使上述外延层进行气相生长。
单晶硅晶片的主面更优选为自{110}面的偏离角超过0度且小于1度的面。
在使上述外延层进行气相生长之后，可对上述外延层的表面进行镜面抛光。这种情况下，更优选使用包含粒径为20nm以下的磨粒的抛光液，使抛光量(研磨代)超过0且为0.2μm以下，进行镜面抛光。
本发明为硅外延晶片，其是使外延层在以{110}面或自{110}面的偏离角小于1度的面为主面的单晶硅基板上生长而得的外延晶片，
其中，利用微分干涉相衬法观察的上述外延层表面的微小台阶缺陷为1.5个/300mm晶片以下，
利用白色显微镜观察的上述外延层的表面粗糙度的PV值小于10nm。
单晶硅晶片的主面更优选为自{110}面的偏离角超过0度且小于1度的面。
上述外延层表面的雾度水平(SP2、以DWO模式测定)更优选为0.4ppm以下。
上述单晶硅晶片更优选为添加硼、且电阻率调整至1mΩ·cm～100mΩ·cm而得的晶片。
发明效果
根据本发明，可提供能够抑制DIC缺陷的硅外延晶片的制造方法和硅外延晶片。
附图说明
[图1]是显示本发明的实施例1～6和比较例1～6的生长速度和生长温度(晶片温度)的图。
[图2]是显示晶片的温度和生长速度与DIC缺陷的关系的图。
具体实施方式
以下，根据附图来说明本发明的实施方式。图1是显示本发明的实施例1～6和比较例1～6的生长速度和生长温度(晶片温度)的图。
本实施方式的硅外延晶片的制造方法是使外延层在以{110}面或自{110}面的偏离角小于1度的面为主面的单晶硅晶片的上述主面上进行气相生长的方法。主面的自{110}面的偏离角为1度以上的晶片，其载流子迁移率高的器件特性不充分，因此优选适用本实施方式的制造方法的晶片是以自{110}面的偏离角为0度的面为主面的单晶硅晶片、或以自{110}面的偏离角超过0度且小于1度的面为主面的单晶硅晶片。特别是，若使用以自{110}面的偏离角超过0度且小于1度的面为主面的单晶硅晶片，则不仅可进一步减小DIC缺陷，还可进一步减小外延层的表面粗糙度的PV值。
关于本实施方式的硅外延晶片的制造方法，在使外延层在上述的具有晶面的单晶硅晶片的主面上进行气相生长时，在将晶片的温度和外延层的生长速度设为晶片的温度为1140℃～1165℃、外延层的生长速度为0.5μm/分钟～1.7μm/分钟的条件下来进行。更具体而言，是图1的实施例1～实施例6所示的范围，是1140℃×0.5μm/分钟～1165℃×1.7μm/分钟的范围。晶片的温度是指投入至气相生长装置的腔室内的晶片的实际温度，通过对加热灯的供给电力等来控制。另外，外延层的生长速度是指形成于晶片主面的外延层的每单位时间的膜厚，通过供给至气相生长装置的腔室内的反应气体(例如四氯化硅SiCl4或三氯硅烷SiHCl3等)的每单位时间的浓度(原料气体的浓度和流量)来控制。
本发明人在研究晶片的温度和生长速度与DIC缺陷的关系时，得到了图2所示的见解。图2是显示将外延层的生长速度设为相对慢的条件和相对快的条件这2个水准，在这2个水准下分别将晶片的温度设为相对高的温度和相对低的温度这2个水准的条件下形成外延层的情况下的DIC缺陷的结果的图。基于此，在将外延层的生长速度设定为相对快的情况下，晶片的温度设定得越低则DIC缺陷越少，反之，在将外延层的生长速度设定为相对慢的情况下，晶片的温度设定得越高则DIC缺陷越少。因此，在将外延层的生长速度设为相对慢的速度的0.5μm/分钟～1.7μm/分钟的条件下来进行的情况下，优选将晶片温度设为相对高的1140℃～1165℃。若在这样的条件下进行制造，则可得到利用微分干涉相衬法观察的外延层表面的微小台阶缺陷为1.5个/300mm晶片以下、且使用白色显微镜观察的外延层的表面粗糙度的PV值小于10nm的硅外延晶片。
在本实施方式的硅外延晶片的制造方法中，在使外延层进行气相生长之后，可对外延层的表面进行镜面抛光。这种情况下，例如可使用包含粒径为20nm以下的磨粒的抛光液，使抛光量超过0且为0.2μm以下，进行镜面抛光。通过对外延层的表面进行镜面抛光，可得到外延层表面的雾度水平(SP2，以DWO模式测定)为0.4ppm以下的硅外延晶片。
需要说明的是，为了得到吸气效应(gettering effect，吸杂效应)，单晶硅晶片可以是添加硼、且电阻率调整至1mΩ·cm～100mΩ·cm而得的晶片。
以下，通过本发明的实施例1～6和比较例1～6进一步详细地说明本发明。
利用采用了CZ(Czochralski)法的单晶硅提拉装置，制造主轴取向为＜110＞、直径为305mm的p型单晶硅锭。对该锭进行外周磨削至直径300mm后，施行切口加工，切取多个电阻率为1～100mΩcm的块。使用线锯将该块切片，使{110}面的倾斜相对于倾斜取向＜100＞的偏离角为0度和0.35度。
对该晶片以倒角(chamfering)、磨光(lapping)、精加工倒角、蚀刻、双面抛光、带倒角、边缘的镜面抛光、表面的单面抛光的顺序进行加工，得到了镜面抛光晶片。需要说明的是，虽然省略对工序间的洗涤处理的阐述，但与常规的晶片加工工艺同样地进行洗涤处理。在如此操作而得到的单晶硅晶片的表面，使用单片式CVD装置(Applied Materials公司制造的Centura)使厚度为4μm的单晶硅外延层生长。此时的实施例1～6和比较例1～6的生长速度和生长温度(晶片温度)的各条件如表1所示进行设定。
对于由CVD装置切取的晶片，立即使用SC-1洗涤液进行钝化处理。所得的外延晶片的一部分用单面抛光装置和包含粒径为20nm以下的磨粒的抛光液进行抛光，使外延面的表面超过0且为0.2μm以下。
对所得的外延晶片分别测定DIC缺陷密度、表面粗糙度的PV值、雾度值。其结果见表1。
[表1]
《DIC缺陷密度》
外延层表面的微小台阶缺陷密度的测定通过微分干涉相衬(DifferentialInterference Contrast、DIC)法进行测定。具体而言，使用晶片表面检查装置(KLA-Tencor公司制造、Surfscan SP3)，以DIC模式(基于DIC法的测定模式)进行测定。在测定时，将凹凸形状的台阶状微小缺陷的高度的阈值设定为3nm，求出超过该阈值的台阶状微小缺陷的个数(每1片300mm的晶片)。
《表面粗糙度PV值》
表示外延层的表面粗糙度的PV值(Peak to Valley，峰-谷值)使用白色显微镜来求出。白色显微镜用半反射镜将LED光束分开，对参照面和样品面进行照射，同时边将其沿Z方向振动边以从参照面返回的光束与从样品面返回的光束的干渉达到最强的位置作为焦点位置进行成像，得到3D图像。
《雾度值》
外延层的表面雾度值的测定使用表面检查装置(KLA-Tencor公司制造、SurfscanSP2)，以DWO模式(Dark Field Wide Oblique模式：暗视野-宽-斜入射模式)进行测定。
《考察》
如表1的实施例1～6所示，使外延层在上述的具有晶面的单晶硅晶片的主面上进行气相生长时，若在晶片的温度和外延层的生长速度设为晶片的温度为1140℃～1165℃、外延层的生长速度为0.5μm/分钟～1.7μm/分钟的条件下来进行，则可使每1片300mm的晶片的DIC缺陷密度为1.5个以下，同时可使表面粗糙度的PV值小于10nm。此时，对于单晶硅晶片的主面为自{110}面的偏离角超过0度且小于1度的面、具体而言0.35度的晶片，可使表面粗糙度的PV值进一步提高至4nm以下。
而且，关于对外延层的表面进行镜面抛光而得的晶片，其镜面抛光前的雾度水平为0.4ppm左右，相对于此，可将雾度水平提高至0.03ppm左右，因此可利用颗粒计数仪进行LPD(Light Point Defects、亮点缺陷)等质量管理。
相对于此，外延层的生长条件中晶片的温度低于1140℃的比较例1～4、或外延层的生长速度快于1.7μm/分钟的比较例5～6的DIC缺陷密度显著变大。

Claims (8)

1.硅外延晶片的制造方法，所述硅外延晶片的制造方法是使外延层在以{110}面或自{110}面的偏离角小于1度的面为主面的单晶硅晶片的上述主面上进行气相生长，
其中，将上述单晶硅晶片的温度设为1140℃～1165℃，以0.5μm/分钟～1.7μm/分钟的生长速度使上述外延层进行气相生长，使用微分干涉相衬法观察的外延层表面的凹凸形状的台阶状微小缺陷设为1.5个/300mm晶片以下，所述台阶状微小缺陷的高度超过3nm。
2.权利要求1所述的硅外延晶片的制造方法，其中，单晶硅晶片的主面为自{110}面的偏离角超过0度且小于1度的面。
3.权利要求1或2所述的硅外延晶片的制造方法，其中，在使上述外延层进行气相生长之后，对上述外延层的表面进行镜面抛光。
4.权利要求3所述的硅外延晶片的制造方法，其中，使用包含粒径为20nm以下的磨粒的抛光液，使抛光量超过0且为0.2μm以下，进行镜面抛光。
5.硅外延晶片，其是使外延层在以{110}面或自{110}面的偏离角小于1度的面为主面的单晶硅基板上生长而得的硅外延晶片，
其中，利用微分干涉相衬法观察的上述外延层表面的微小台阶缺陷为1.5个/300mm晶片以下，
利用白色显微镜观察的上述外延层的表面粗糙度的PV值小于10nm。
6.权利要求5所述的硅外延晶片，其中，上述单晶硅基板的主面为自{110}面的偏离角超过0度且小于1度的面。
7.权利要求5或6所述的硅外延晶片，其中，上述外延层表面的以DWO模式测定的雾度水平SP2为0.4ppm以下。
8.权利要求5或6所述的硅外延晶片，其中，上述单晶硅基板为添加硼、且电阻率调整至1mΩ·cm～100mΩ·cm而得的晶片。
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