CN113223568B - 一种锁存结构和锁存方法 - Google Patents
一种锁存结构和锁存方法 Download PDFInfo
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- CN113223568B CN113223568B CN202110534867.5A CN202110534867A CN113223568B CN 113223568 B CN113223568 B CN 113223568B CN 202110534867 A CN202110534867 A CN 202110534867A CN 113223568 B CN113223568 B CN 113223568B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
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CN202110534867.5A CN113223568B (zh) | 2021-05-17 | 2021-05-17 | 一种锁存结构和锁存方法 |
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CN202110534867.5A CN113223568B (zh) | 2021-05-17 | 2021-05-17 | 一种锁存结构和锁存方法 |
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CN113223568A CN113223568A (zh) | 2021-08-06 |
CN113223568B true CN113223568B (zh) | 2022-04-22 |
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Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS58205906A (ja) * | 1982-05-26 | 1983-12-01 | Victor Co Of Japan Ltd | メモリ回路への書き込み方式 |
JP4565883B2 (ja) * | 2004-04-27 | 2010-10-20 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置 |
EP1748344A3 (en) * | 2005-07-29 | 2015-12-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US7532147B2 (en) * | 2007-01-24 | 2009-05-12 | Panasonic Corporation | Analog voltage latch |
JP2016171493A (ja) * | 2015-03-13 | 2016-09-23 | セイコーエプソン株式会社 | 回路装置、電子機器及び移動体 |
CN111541453B (zh) * | 2017-10-11 | 2023-09-29 | 科技创意有限公司 | 时域a/d转换器组 |
US10878857B2 (en) * | 2018-11-02 | 2020-12-29 | Bitmain Inc. | Dynamic data storage element, and integrated circuit having the same |
CN109861535B (zh) * | 2019-03-28 | 2023-08-25 | 杭州雄迈集成电路技术股份有限公司 | 一种芯片嵌入式同步整流dcdc防过压击穿的电路系统 |
US10749531B1 (en) * | 2019-09-16 | 2020-08-18 | Synopsys, Inc. | Multi-modulus frequency divider circuit |
CN111064470B (zh) * | 2019-12-12 | 2022-08-02 | 中国电子科技集团公司第五十八研究所 | 一种应用于dds的数据合成电路 |
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PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: A Latch Structure and Latch Method Effective date of registration: 20230308 Granted publication date: 20220422 Pledgee: Fuyang sub branch of Bank of Hangzhou Co.,Ltd. Pledgor: Hangzhou xiongmai integrated circuit technology Co.,Ltd. Registration number: Y2023330000470 |
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Address after: 311422 4th floor, building 9, Yinhu innovation center, 9 Fuxian Road, Yinhu street, Fuyang District, Hangzhou City, Zhejiang Province Patentee after: Zhejiang Xinmai Microelectronics Co.,Ltd. Address before: 311400 4th floor, building 9, Yinhu innovation center, No.9 Fuxian Road, Yinhu street, Fuyang District, Hangzhou City, Zhejiang Province Patentee before: Hangzhou xiongmai integrated circuit technology Co.,Ltd. |
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