CN113169159A - 用于微电子器件的直接接合的界面中的电容性耦合 - Google Patents

用于微电子器件的直接接合的界面中的电容性耦合 Download PDF

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Publication number
CN113169159A
CN113169159A CN201980080676.7A CN201980080676A CN113169159A CN 113169159 A CN113169159 A CN 113169159A CN 201980080676 A CN201980080676 A CN 201980080676A CN 113169159 A CN113169159 A CN 113169159A
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Prior art keywords
die
capacitive
dielectric
microelectronic device
bonding interface
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CN201980080676.7A
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B·哈巴
A·R·西塔拉姆
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Adeia Semiconductor Technologies LLC
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Invensas LLC
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Priority claimed from US16/212,248 external-priority patent/US10811388B2/en
Application filed by Invensas LLC filed Critical Invensas LLC
Publication of CN113169159A publication Critical patent/CN113169159A/zh
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Abstract

提供了用于微电子器件的直接接合的界面中的电容性耦合。在一实施方式中，微电子器件包括在接合界面处直接接合在一起的第一管芯和第二管芯、通过金属‑金属直接接合在接合界面处形成的第一管芯和第二管芯之间的导电互连件、以及在接合界面处形成的第一管芯和第二管芯之间的电容性互连件。直接接合工艺在两个管芯的介电表面之间产生直接接合，在两个管芯的相应导电互连件之间产生直接接合，以及在接合界面处在两个管芯之间产生电容性耦合。在一实施方式中，每条信号线在接合界面处的电容性耦合包括每条信号线在接合界面处形成电容器的介电材料。电容性耦合产生于相同的直接接合工艺，该相同的直接接合工艺在相同的接合界面处产生直接接合在一起的导电互连件。

Description

用于微电子器件的直接接合的界面中的电容性耦合
相关申请的交叉引用
本申请要求2018年12月6日提交的美国专利申请第16/212,248号的优先权的权益，该美国专利申请第16/212,248号是2018年6月27日提交的申请第16/020,654号的部分继续申请，该申请第16/020,654号是要求了2015年9月28日提交的美国临时专利申请第62/234,022号的优先权的权益的2016年8月25日提交的美国专利申请第15/247,705号(现在是2018年7月24日公布的美国专利第10,032,751号)的分案申请，所有这些申请通过引用全部并入本文。
背景技术
直接接合和直接混合接合有时需要临界公差。当可以设计在接合界面处耦合电源、地线和信号线的各种方式时，这些工艺可以变得更加宽容，例如，允许一些未对准，并允许较低的临界公差，以便以更高的接合成品率提供更可靠的封装件。
此外，晶片级封装件和微电子元件的尺寸减小有时会被难以小型化的组件的必要包含所抑制。例如，有时封装件依赖于分立电容的相对较大尺寸。如果封装件不必依赖于大的组件，则封装件可以做得更小。在其它情况下，集成电路设计中需要一定值的电容，并且如果可以将电容内置到晶片级封装件设计中，则可以简化构造过程。
发明内容
提供了微电子器件的直接接合的界面中的电容性耦合。在一实施方式中，微电子器件包括在接合界面处直接接合在一起的第一管芯和第二管芯、通过金属-金属直接接合在接合界面处形成的第一管芯和第二管芯之间的导电互连件、以及第一管芯和第二管芯之间的在接合界面处形成的电容性互连件。直接接合工艺在两个管芯的介电表面之间产生直接接合，在两个管芯的相应导电互连件之间产生直接接合，以及在接合界面处在两个管芯之间产生电容性耦合。在一实施方式中，每条信号线在接合界面处的电容性耦合包括每条信号线在接合界面处形成电容器的介电材料。电容性耦合产生于相同的直接接合工艺，该相同的直接接合工艺在相同的接合界面处产生直接接合在一起的导电互连件。
本发明内容不旨在识别所要求保护的主题的关键或基本特征，也不旨在用作限制所要求保护的主题的范围的辅助。
附图说明
下文将参照附图描述本公开的某些实施方式，其中相同的附图标记表示相同的元件。然而，应当理解，附图示出了本文中描述的各种实施方式，并且不意味着限制本文中描述的各种技术的范围。
图1是包括与超薄介电层的示例电容性耦合的示例晶片级封装结构100的图。
图2是示例晶片级封装结构的示图，其中超薄介电层包括两个组件介电层。
图3是另一示例晶片级封装结构的示图，其中超薄介电层包括多个组件介电层。
图4是包括具有交错导电板的电容性界面的示例晶片级封装件的图。
图5是用于制作包括电容性界面的耦合的电容性晶片级封装件的示例工艺的示图。
图6是第一管芯和第二管芯之间的示例直接接合的界面的示图，其包括与通过相同直接接合工艺形成的一个或多个电容性互连件在相同接合平面中的一个或多个直接接合的导电互连件。
图7是第一管芯和第二管芯之间的另一示例直接接合的界面的示图，其包括与通过相同直接接合工艺形成的一个或多个电容性互连件在相同接合平面中的一个或多个直接接合的导电互连件。
图8是第一管芯和第二管芯之间的示例直接接合的界面的另一示图，其包括与通过相同直接接合工艺形成的一个或多个电容性互连件在相同接合平面中的一个或多个直接接合的导电互连件。
图9是示例直接接合的界面的示图，其包括在接合界面处直接接合在一起的导电互连件，以及也在接合界面处耦合的示例电容性互连件。
图10是示例直接接合的界面的示图，其包括在接合界面处直接接合在一起的导电互连件以及也在相同接合界面处耦合的示例电容性互连件，在相同接合界面处具有一个或多个导电通孔。
图11是在微电子器件的直接接合的界面中创建电容性耦合的示例方法的流程图。
具体实施方式
概述
本公开描述了用于微电子器件的直接接合的界面中的电容性耦合。用于微电子管芯和晶片的直接混合接合工艺也为接合界面处的每条单独信号线创建电容性耦合。在一实施方式中，直接混合接合工艺在两个管芯的介电表面之间产生直接接合，在两个管芯的相应电源互连件之间产生直接接合，在两个管芯的相应接地互连件之间产生直接接合，并且在直接混合接合工艺的接合界面处针对每条信号线产生电容性耦合。
介电表面之间的直接接合可以是氧化物-氧化物的直接接合。相应电源互连件之间的直接接合是金属-金属的直接接合。相应接地互连件之间的直接接合也是金属-金属的直接接合。每条信号线在接合界面处的电容性耦合包括介电材料，介电材料针对每条信号线在接合界面处形成电容器，这是由直接混合接合工艺产生的。
示例技术在封装结构中实现具有非常精细间距的电容性耦合。通过连接两个相对的表面，可以在两个导电区(板或焊盘，即来自每个管芯的一个)之间实现纳米量级的非常薄的介电层。两个板或焊盘结合在一起，形成一个具有间隔的电容器，例如，在50纳米以下。
在示例实施方式中，要耦合的每个组件具有包括至少一个导电区的表面，例如金属焊盘或板(即，电容器板)。在至少一个要耦合的表面上形成超薄的介电层。当两个组件永久接触在一起时，超薄的介电层保留在两个表面之间，在每个相应组件的导电区之间形成电容性界面。在一实施方式中，超薄的介电层可以由多个不同的介电层组成，但是这种多层的组合厚度小于或等于大约50纳米。所形成的电容性界面的每单位面积的电容取决于超薄层中使用的介电材料的特定介电常数k、超薄层中单个介电层的相应厚度(如果使用一个以上的介电层)以及组合的超薄介电层的总厚度。
在一实施方式中，电连接和接地连接可以在耦合叠层的边缘处，即，围绕电容性界面的边缘进行。因此，在表面之间的电容性界面的表面积内，在一实施方式中，可以不存在穿过超薄介电层的导电连接件或极少的导电连接件。如果在具有电容性界面的表面的区域内使用导电连接件，则将这种导电连接件放置在附近没有参与电容性界面的金属板的地方。
本文中描述的示例电容性耦合技术提供了许多优点，例如较小尺寸的晶片级封装件、所用材料的节省、以及由于较薄的电介质和相对高的每单位面积介电常数k而潜在地较低的电压要求。对于某些应用，例如使用小尺寸电池的移动设备，可以实现显著较低的工作电压。
示例系统
图1示出了示例晶片级封装结构100，其包括第一集成电路管芯102和第二集成电路管芯104。每个集成电路管芯102和104具有半导体106和108(例如硅)，以及底部填充层110和112，底部填充层110和112由绝缘或电介质(例如二氧化硅)构成，以固定导电区114和116以及118和120。每个集成电路管芯102和104具有相应的表面122和124，其包括导电区114和116以及118和120中的至少一个。
厚度小于或等于约50纳米的超薄介电层126形成在集成电路管芯102和104中的至少一个的表面122和124中的至少一个上。超薄介电层可以是涂层、薄膜、残留物、膜、沉积物等。耦合叠层100形成电容性界面128，该电容性界面128包括超薄介电层126，以及在超薄介电层126的相对侧上的第一集成电路管芯102和第二集成电路管芯104的至少一对相应的导电区，例如114和118或116和120。
超薄介电层126的厚度可以在大约2-50纳米的范围内。例如，超薄介电层126可以是5-6纳米厚。在一实施方式中，超薄介电层126的厚度小于2纳米。
在一实施方式中，超薄介电层126可以由氧化硅(二氧化硅SiO2)构成。或者，超薄介电层126可以由电介质例如一氧化硅、三氧化硅、氧化铝、氧化铪、高k离子金属氧化物、杂化氧等离子体生长的金属氧化物和烷基膦酸自组装单层(SAM)、聚合物膜或离子金属氧化物膜组成。
例如，超薄介电层126可以是氧化铪的原子层沉积，其精确控制超薄介电层126的厚度至1-2纳米。
在另一实施方式中，超薄介电层126可以是金属氧化物和烷基膦酸自组装单层(SAM)的层，其具有大约5-6纳米的厚度和大约500-800nF/cm2的每单位面积电容。
在一个示例中，通过在堆叠件100的边缘处机械地将两个集成电路管芯102和104固定在一起，两个集成电路管芯102和104可以在堆叠件中耦合在一起。在另一示例中，集成电路管芯102和104中的至少一个的表面122和124中的至少一个上的超薄介电层126可以具有用于将集成电路管芯102和104彼此粘附的粘接质量。
两个集成电路管芯102和104之间的电源连接件130和电接地连接件132可以位于堆叠件100的边缘处。
图2示出了示例晶片级封装结构200，其中超薄介电层206包括多个组件介电层202和204。在该示例中，在其中一个集成电路管芯102上形成第一组件介电层202，并且在另一个集成电路管芯104上形成第二组件介电层204。多组件介电层202和204可以由相同的介电材料(例如氧化硅)或不同的介电材料组成。在该示例中，每个组件介电层202和204具有小于或等于25纳米的厚度。当两个集成电路管芯102和104耦合时，得到的整个超薄介电层206具有小于或等于约50纳米的厚度。形成的电容性界面208包括超薄介电层206以及在超薄介电层206的相对侧上的第一集成电路管芯102和第二集成电路管芯104的相应导电区114和116以及118和120。
图3示出了示例晶片级封装结构300，其中超薄介电层310包括多个组件介电层302和304以及306和308。在此示例中，第一组组件介电层302和304形成在其中一个集成电路管芯102上，而第二组组件介电层306和308形成在另一个集成电路管芯104上。例如，每组超薄介电层302和304或306和308具有小于或等于约25纳米的厚度。或者，当两个集成电路管芯102和104耦合时，得到的整个超薄介电层310的具有例如小于或等于约50纳米的厚度。不需要多层厚度的对称性。所形成的电容性界面312包括超薄介电层302和304以及306和308以及在超薄介电层310的相对侧上的第一集成电路管芯102和第二集成电路管芯104的相应导电区114和116以及118和120。
当多层超薄介电材料用于整个超薄介电层310的不同层(例如302和304或306和308)时，多层可由不同介电材料组成，例如一层或多层氧化硅，以及一层或多层除氧化硅以外的高k电介质，例如一氧化硅、三氧化硅、氧化铝、氧化铪、高k离子金属氧化物、杂化氧等离子体生长的金属氧化物和烷基膦酸自组装单层(SAM)或聚合物。
当多层超薄介电材料用于整个超薄介电层310的不同层(例如，302和304或306和308)时，多层可以相对于多层的平行中心平面不对称。不对称性可包括多层的平行中心平面的任一侧上的多层中的一个或多个层的数量、布置、厚度或组分的差异。
图4示出包括具有超薄介电层402的电容性界面404的晶片级封装件400的示例实施方式。如图4所示，第一集成电路管芯102和第二集成电路管芯104的相应导电区114和116和118和120不必在电容性界面404的超薄介电层402的相对侧上完美对准。第一集成电路管芯102和第二集成电路管芯104的相应导电区114和116以及118和120可以相对于彼此交错，并且交错对准可以用于获得特定电容，例如，在电容性界面404的相对侧上的第一导电区114和第二导电区118之间。
图5示出了用于制造包括电容性界面510的耦合电容晶片级封装件500的示例过程。在一实施方式中，集成电路管芯102和102'具有半导体106(例如硅)，和底部填充层110，底部填充层110由绝缘或电介质(例如二氧化硅)组成，以固定一个或多个导电区114和116。每个集成电路管芯102和102'具有相应的表面122，其包括导电区114和116。在该过程中，表面122在这一点上不必是平坦的。
在表面122上形成介电层502，例如氧化硅或高k介电层，包括一个或多个导电区114和116和底部填充层110的暴露部分。在一实施方式中，介电层502被磨(ground)、蚀刻、研磨(lapped)、或抛光、(或沉积)等至小于或等于约50纳米的厚度。对于电介质502的给定层要实现的厚度可取决于构成整个超薄介电层508的层数以及所需的每单位面积的电容的值。介电层502被蚀刻或以其他方式去除，例如，向下至底部填充层110的暴露部分，以形成平坦表面122。
现在可以耦合同一集成电路管芯102和102'的两个实例以形成堆叠件506，每个集成电路管芯现在具有光滑的平坦表面504。由耦合产生的电容性界面510包括超薄介电层508和在超薄介电层508的相对侧上的至少一对导电区114和118或116和120。
在一个变型中，蚀刻停止层512或研磨-抛光停止层可施加到初始表面122以保护下面的结构并以超细间距辅助超薄介电层508的形成。因此，蚀刻停止512或研磨-抛光停止被沉积在下面的结构上，例如暴露的底部填充110和导电区114和116，以保护蚀刻停止层512下面的结构(110和114和116)免受蚀刻工艺造成的损坏。一旦超薄介电层508的期望厚度已经通过蚀刻工艺实现，蚀刻停止层512终止蚀刻工艺。
蚀刻停止可以是二氧化硅蚀刻停止、硼蚀刻停止、氧化铝蚀刻停止、多晶硅蚀刻停止、氧化钛蚀刻停止或氮化硅蚀刻停止。
蚀刻或研磨工艺可以是干式化学蚀刻工艺、湿式蚀刻工艺、例如使用诸如CF4、CHF3、CH2F2、NF3或O2的氧化物蚀刻气体的气态蚀刻工艺、或者例如使用电化学蚀刻速率调制的电化学蚀刻工艺。在一实施方式中，超薄介电层508或其组件层通过沉积形成，例如电介质如氧化铪(HfO2)的原子层沉积。
氧等离子体生长的金属氧化物(例如氧化铝)和高质量烷基膦酸自组装单层(SAM)的组合可以在不超过约100℃的工艺温度下获得，并且不仅可以在玻璃(氧化硅)衬底上形成，而且可以在市售的柔性塑料衬底上形成，例如聚萘二甲酸乙二醇酯或聚对苯二甲酸乙二醇酯。这样的超薄介电层508可以具有大约5-6纳米的总厚度和大约500-800nF/cm2的每单位面积电容。
在一个变型中，在通过蚀刻介电层502获得平滑平坦表面504之后，可在平滑平坦表面504上方形成额外的超薄介电层514，例如由氧化硅或其它高k介电层构成。一旦集成电路管芯102和102'已耦合到堆叠件506中，形成电容性界面510，则附加的超薄介电层514可用于调谐所产生的电容性界面510的厚度，从而调谐所产生的电容性界面510的电容。附加的超薄介电层514还可用于增加电容性界面510对电荷和电压泄漏或介电击穿的电阻。
图6示出了第一管芯602和第二管芯604之间的示例直接接合的界面600，其包括与通过相同直接接合工艺形成的一个或多个电容性互连件608在相同接合平面600中的一个或多个直接接合的导电互连件606。直接接合在一起以实现具有导电互连件606和电容性互连件608的直接接合的界面600的两个表面可以属于管芯-管芯(D2D)工艺中的两个管芯602和604，可以是管芯-晶片(D2W)工艺中的管芯602和晶片上的管芯604，或者可以是晶片-晶片(W2W)工艺中的两个晶片上的管芯602和604。
在用于制造器件或封装件的微制造工艺中，示例第一管芯602和示例第二管芯604在接合界面600处直接接合在一起。还通过直接接合工艺形成金属-金属的直接接合，以在第一管芯602和第二管芯604之间形成导电互连件606，导电互连件606形成在接合界面600处。第一管芯602和第二管芯604之间的电容性互连件608通过相同的一个或多个直接接合工艺在接合界面600处形成。
在一实施方式中，第一管芯602和第二管芯604在接合界面600处通过在第一管芯602和第二管芯604的相应非金属表面之间的介电-介电直接接合610直接接合在一起。
第一管芯602和第二管芯604的相应非金属表面之间的介电-介电直接接合610(例如，氧化物-氧化物直接接合)还产生电容性互连件608的电容性耦合612。电容性互连件608的电容性耦合612包括第一管芯602中的第一金属614和第二管芯604中的第二金属616。第一金属614和第二金属616由介电介质618分开。
图7示出了第一管芯602和第二管芯604之间的示例直接接合的界面700，其包括与通过相同直接接合工艺形成的一个或多个电容性互连件702在相同接合平面700中的一个或多个直接接合的导电互连件606。
在一实施方式中，第一管芯602中的电容性互连件702的第一金属614从接合界面700凹入具有介电介质618的空间，而第二管芯604中的电容性互连件702的第二金属616与接合界面700齐平。
图8示出了第一管芯602和第二管芯604之间的示例直接接合的界面800，其包括与通过相同直接接合工艺形成的一个或多个电容性互连件802在相同接合平面800中的一个或多个直接接合的导电互连件606。
在一实施方式中，第一管芯602中的电容性互连件802的第一金属614从接合界面800凹入，而第二管芯604中的电容性互连件802的第二金属616也从相同的接合界面800沿相反的方向凹入。一个或多个介电材料804和806可以构成金属614和616之间的介电介质618，其创建电容性互连件802的电容性耦合(或电容器)。图8中所示的介电材料804和806被示出为至少一种固体介电材料，而图6中所示的介电材料被示出为间隙(例如空气填充的间隙)。
电容性互连件802的介电介质618可以由二氧化硅、氮化硅、空气或高介电材料(例如)、或这些和可用于半导体微制造的其它介电材料、气体和物质的混合物或组合制成。
电容性互连件802的介电介质618可以是相对于第一管芯602和第二管芯604之间的接合界面800的水平面的介电材料的非对称组合。
可以选择第一管芯602中的第一金属614和第二管芯604中的第二金属616之间的间隔距离以为给定的电容性互连件802或一组电容性互连件802提供特定的电容值或电容范围。
在一实施方式中，电容性互连件608、702和802的介电介质618可以是介电材料的至少一个超薄层。介电材料的超薄层可以是涂层、薄膜、残留物、膜、沉积物或间隙(例如，空气空间)。介电材料的超薄层的厚度和介电常数可以确定电容性互连件608、702和802的电容或电容效用。介电材料的超薄层可以具有例如小于或等于约50纳米的厚度。介电材料的超薄层也可以由多层制成。在一实施方式中，组合的多层的厚度例如小于25纳米。在一实施方式中，介电材料的多层中的至少一层可以是聚合物。电容性互连件608和702和802的电容可由一个或多个聚合物层的厚度确定。
图9示出了示例直接接合的界面900，其包括在接合界面900处直接接合在一起的导电互连件902，以及也在接合界面900处耦合的示例电容性互连件904。例如，导电互连件902可以是直接接合的电源互连件或直接接合的接地互连件。电容性互连件904例如可以是第一管芯602和第二管芯604之间的信号线。接合界面本身900也直接接合在一起，例如通过非金属-非金属的直接接合。将每个管芯602和604的相应接合表面连接到直接接合的界面900中，在接合界面900处针对每个单独的电容性互连件904产生电容性耦合(图6中的612)。
直接接合的一种类型是直接混合接合，其包括(非金属)电介质的直接接合和金属导电互连件902在相同的接合界面900处的直接接合。在接合界面900的任一侧上的第一管芯602和第二管芯604的介电表面通过氧化物-氧化物的直接接合而直接接合在一起，而不使用任何粘合剂。
对于导电互连件902，在接合界面900的任一侧上的金属焊盘，例如焊盘906和908，通过金属-金属接触接合直接接合在一起，而不使用焊料或粘合剂。在一实施方案中，“直接接合互连”(
Figure BDA0003102039480000111
品牌)直接混合接合用于直接混合接合工艺，其在室温下将两个管芯602和604的介电表面直接接合在一起，然后在更高的退火温度下将金属焊盘906和908直接接合在一起(Invensas股份有限公司，Xperi公司的子公司，San Jose，CA)。
Figure BDA0003102039480000112
直接混合接合可每平方mm提供100,000-1,000,000个连接，其中每个连接的间距平均为<1μm-40μm。对于间距小于1μm的连接，甚至更大的连接密度是可行的。
在一实施方式中，电源和接地互连件902可以是冗余实例，使得如果一个或多个焊盘906未接合或未垂直对齐，则电源或接地连接仍然经由冗余导电互连件902的其他实例进行。直接接合互连件902可具有相对较大的金属焊盘，以提供更好的接合良率并允许在示例直接混合接合工艺期间的一些水平不对准，同时确保金属焊盘906和908的足够表面积跨越接合界面900彼此接触以传导所需电流。
用于信号线和数据线的电容性互连件904不在直接混合接合工艺中接合，而是形成电容性耦合612，该电容性耦合612构成管芯602和604之间的每个电容性互连件904的信号传递接口。
在一实施方式中，使用电容性互连件904的信号线可包括用于使信号通过接合界面900的冗余电路。冗余电路可以在制造期间提供更好的良率和/或在使用期间提供高可用性。还可以使用冗余信号线来实现给定信号电路的电容性耦合的特定总电容，给定信号电路跨越所连接的电接口602。
图10示出了示例直接接合的界面1000，其包括在接合界面1000处直接接合在一起的导电互连件1002，以及也在相同接合界面1000处耦合的示例电容性互连件1004。一个或多个导电通孔1006和1008，例如硅通孔(TSV)或介电通孔(TDV)，也在示例直接接合的第一管芯602和第二管芯604中实现。
例如，导电通孔1006或1008可以在过孔最后工艺中制造。示例导电通孔1008可以被实现为完全或至少部分地穿透一个管芯604。或者，示例通孔1006可以被实现为完全或至少部分地穿透直接接合的管芯602和604。过孔最后导电通孔1006和1008可为工艺集成提供优点，以减少工艺影响和对后端线(BEOL)处理的热预算。例如，能够实现直接混合接合的相同的后到前侧(back-to-front)晶片对准可以提供用于过孔最后图案化的光刻对准，以集成导电通孔1006和1008。
示例方法
图11示出了在微电子器件的直接接合的界面中产生电容性耦合的示例方法1100。在图11的流程图中，示例方法1100的操作被示为单独的框。
在框1102处，在接合界面处在两个管芯的相应介电表面之间产生第一直接接合。
在框1104处，在接合界面处在两个管芯的相应导电互连件之间产生第二直接接合。
在框1106处，针对两个管芯之间的电容性互连件在接合界面处产生电容性耦合。
通常，示例方法1100包括在相同的直接接合操作期间产生第一(非金属)直接接合和第二(金属)直接接合，这也在相同的操作中形成电容性耦合，所有这些在相同的直接接合操作期间(例如直接混合接合操作)发生在相同的接合界面处。
例如，在接合界面处的介电表面之间的直接接合包括氧化物-氧化物的直接接合。相应导电互连件之间的直接接合包括金属-金属的直接接合。电容性耦合包括至少一种介电材料，该介电材料位于两个管芯的两个相应金属之间的接合界面处，该两个管芯通过完成氧化物-氧化物直接接合和金属-金属直接接合的相同直接接合操作而被耦合。
在一实施方式中，示例方法可包括在管芯上产生接合表面，接合表面包括用于直接混合接合的平坦介电材料,制造与接合表面相关联的电源互连件的第一金属焊盘，第一金属焊盘适于直接混合接合，制造与接合表面相关联的接地互连件的第二金属焊盘，第二金属焊盘适于直接混合接合，制造与接合表面相关联的信号线的至少一个凹入金属焊盘，凹入焊盘用于在直接混合接合期间形成跨越接合表面的信号线的电容性耦合，以及在信号线的凹入金属焊盘与接合表面之间的凹入空间中设置适于制造电容性耦合的介电材料。如上所述，至少一种适于制造电容性耦合的介电材料可以是空气，或者可以是二氧化硅、氮化硅、高介电材料等等。
在示例直接混合接合工艺中，将第一管芯和第二管芯的相应介电材料直接接合在一起，以将第一管芯和第二管芯接合在一起，并在第一管芯和第二管芯的相应金属焊盘之间形成信号线的电容性耦合。
然后在示例的直接混合接合操作中退火第一管芯和第二管芯，以直接接合相应的第一金属焊盘以形成电源互连件，并直接接合相应的第二金属焊盘以形成接地互连件。
虽然已经针对有限数量的实施方式公开了本公开，但受益于本公开的本领域技术人员将理解对本文提供的描述的许多修改和变化。所附权利要求书旨在覆盖落入本公开的真正精神和范围内的这些修改和变化。

Claims (23)

1.一种微电子器件，包括：
第一管芯和第二管芯，在接合界面处直接接合在一起；
导电互连件，位于所述第一管芯和所述第二管芯之间，通过金属-金属直接接合形成在所述接合界面处；以及
电容性互连件，位于所述第一管芯和所述第二管芯之间，形成在所述接合界面处。
2.根据权利要求1所述的微电子器件，其中所述第一管芯和所述第二管芯利用所述第一管芯和所述第二管芯的相应非金属表面之间的介电-介电直接接合在所述接合界面处直接接合在一起。
3.根据权利要求2所述的微电子器件，其中所述第一管芯与所述第二管芯之间的所述介电-介电直接接合产生所述电容性互连件的电容性耦合。
4.根据权利要求1所述的微电子器件，其中所述电容性互连件包括所述第一管芯中的第一金属和所述第二管芯中的第二金属，所述第一金属和所述第二金属被介电介质隔开。
5.根据权利要求4所述的微电子器件，其中所述第一管芯中的所述电容性互连件的所述第一金属从所述接合界面凹陷，并且所述第二管芯中的所述电容性互连件的所述第二金属与所述接合界面齐平。
6.根据权利要求4所述的微电子器件，其中所述第一管芯中的所述电容性互连件的所述第一金属从所述接合界面凹陷，并且所述第二管芯中的所述电容性互连件的所述第二金属也从所述接合界面凹陷。
7.根据权利要求4所述的微电子器件，其中所述电容性互连件的所述介电介质包括二氧化硅、氮化硅、空气或高介电材料。
8.根据权利要求4所述的微电子器件，其中所述电容性互连件的所述介电介质包括选自包括空气、二氧化硅、氮化硅和高介电材料的组的介电材料的组合。
9.根据权利要求4所述的微电子器件，其中所述电容性互连件的所述介电介质包括相对于所述第一管芯和所述第二管芯之间的所述接合界面的水平面的介电材料的非对称组合。
10.根据权利要求4所述的微电子器件，其中所述第一管芯中的所述第一金属与所述第二管芯中的所述第二金属之间的间隔距离被选择，以便为所述电容性互连件提供电容值。
11.根据权利要求4所述的微电子器件，其中所述电容性互连件的所述介电介质包括至少一个介电材料的超薄层。
12.根据权利要求11所述的微电子器件，其中所述介电材料的所述超薄层包括涂层、薄膜、残留物、膜、沉积物和间隙中的一种；并且
其中所述介电材料的所述超薄层的厚度和介电常数决定所述电容性互连件的电容。
13.根据权利要求11所述的微电子器件，其中所述介电材料的所述超薄层包括小于或等于约50纳米的厚度。
14.根据权利要求11所述的微电子器件，其中所述介电材料的所述超薄层包括多层。
15.根据权利要求14所述的微电子器件，其中所组合的多层的厚度小于25纳米。
16.根据权利要求14所述的微电子器件，其中所述多层中的一层包括聚合物。
17.根据权利要求16所述的微电子器件，其中所述电容性互连件的电容由聚合物层的厚度确定。
18.根据权利要求1所述的微电子器件，其中所述导电互连件包括直接接合的电源互连件或直接接合的接地互连件。
19.根据权利要求1所述的微电子器件，其中所述电容性互连件包括所述第一管芯和所述第二管芯之间的信号线。
20.根据权利要求1所述的微电子器件，还包括导电通孔，所述导电通孔是通过至少部分地穿入所述第一管芯或至少部分地穿入所述第一管芯和所述第二管芯二者的后过孔制造工艺而产生的。
21.一种方法，包括：
在两个管芯的接合界面处在相应的介电表面之间产生第一直接接合；
在所述两个管芯的所述接合界面处在相应的导电互连件之间产生第二直接接合；以及
针对所述两个管芯之间的电容性互连件在所述接合界面处产生电容性耦合。
22.根据权利要求21所述的方法，其中在所述接合界面处的相应的导电互连件之间产生所述第二直接接合和在所述接合界面处产生所述电容性耦合是由在相同接合界面处的相同直接接合工艺产生的。
23.根据权利要求21所述的方法，其中所述介电表面之间的直接接合包括氧化物-氧化物直接接合；
其中所述相应的导电互连件之间的直接接合包括金属-金属直接接合；以及
其中所述电容性耦合包括在所述两个管芯的两个相应的金属之间的所述接合界面处的至少一种介电材料。
CN201980080676.7A 2018-12-06 2019-08-28 用于微电子器件的直接接合的界面中的电容性耦合 Pending CN113169159A (zh)

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