CN112912994A - 包含含硫碳氟化合物的干蚀刻气体组合物和使用其的干蚀刻方法 - Google Patents

包含含硫碳氟化合物的干蚀刻气体组合物和使用其的干蚀刻方法 Download PDF

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CN112912994A
CN112912994A CN201980070063.5A CN201980070063A CN112912994A CN 112912994 A CN112912994 A CN 112912994A CN 201980070063 A CN201980070063 A CN 201980070063A CN 112912994 A CN112912994 A CN 112912994A
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清水久志
加藤惟人
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Kanto Denka Kogyo Co Ltd
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Abstract

提供:包含含硫化合物的、相对于低介电常数材料(低‑k材料(SiON、SiCN、SiOCN、SiOC))能对SiO2选择性地进行蚀刻的新型蚀刻气体组合物。一种干蚀刻气体组合物,其包含用通式(1):CxFySz(式中,x、y和z为2≤x≤5、y≤2x、1≤z≤2)表示的、饱和且环状的含硫碳氟化合物。

Description

包含含硫碳氟化合物的干蚀刻气体组合物和使用其的干蚀刻 方法
技术领域
本发明涉及包含含硫碳氟化合物的干蚀刻气体组合物和使用其的干蚀刻方法。
背景技术
随着半导体装置的微细化、3D化,对蚀刻工序的要求逐年变严格。要求开发出能满足这种严格要求的新型蚀刻技术。近年来,为了降低随着半导体器件的微细化而增大的寄生电容,作为包含碳的硅系膜,使用有用SiOC表示的低介电常数材料,但现有的FC气体、HFC气体中,难以相对于低介电常数材料对硅氧化膜、硅氮化膜选择性地进行蚀刻,制造实际的器件中,干蚀刻时对低介电常数膜的损伤(由于离子的侵入、由等离子体而产生的紫外光而膜的组成、结构变化、介电常数等电特性变化)成为问题。
作为解决上述问题的方案,本申请人提出了包含特定的氢氟烃(1,1,4,4-四氟-1,3-丁二烯)的蚀刻气体组合物是有效的(专利文献1)。
现有技术文献
专利文献
专利文献1:日本特开2016-149451号公报
发明内容
发明要解决的问题
因此,本发明的课题在于,提供:包含含硫化合物的、相对于低介电常数材料(低-k材料(SiON、SiCN、SiOCN、SiOC))可以对SiO2选择性地进行蚀刻的新型蚀刻气体组合物。
用于解决问题的方案
根据本发明,提供以下的方案。
[1]
一种干蚀刻气体组合物,其包含用通式(1):CxFySz(式中,x、y和z为2≤x≤5、y≤2x、1≤z≤2)表示的、饱和且环状的含硫碳氟化合物。
[2]
根据[1]所述的干蚀刻气体组合物,其中,前述含硫碳氟化合物为2,2,3,3,4,4,5,5-八氟四氢噻吩(C4F8S)。
[3]
根据[1]或[2]所述的干蚀刻气体组合物,其中,以1~100vol%的量包含含硫碳氟化合物。
[4]
根据[1]~[3]中任一项所述的干蚀刻气体组合物,其中,除前述含硫碳氟化合物之外,还包含选自由O2、O3、CO、CO2、NO、NO2、SO2和SO3组成的组中的至少1种含氧化合物。
[5]
根据[1]~[4]中任一项所述的干蚀刻气体组合物,其中,除前述含硫碳氟化合物之外,还包含选自由N2、He、Ar、Ne和Xe组成的组中的至少1种非活性气体。
[6]
一种干蚀刻方法,其包括如下工序:使用[1]~[5]中任一项所述的干蚀刻气体组合物,对包含选自由(a1)包含碳的硅系膜、(a2)结晶硅膜、(a3)非晶硅膜、(a4)多晶硅膜(polysilicon film)、(a5)硅氧氮膜、(a6)非晶碳膜、(a7)光致抗蚀膜、(a8)硅氧化膜和(a9)硅氮化膜组成的组中的至少2种以上的层叠结构体进行等离子体蚀刻,对除(a6)非晶碳膜和(a7)光致抗蚀膜以外单独或同时地选择性地进行蚀刻。
[7]
一种干蚀刻方法,其包括如下工序:使用[1]~[5]中任一项所述的干蚀刻气体组合物,对包含选自由(a1)包含碳的硅系膜、(a2)结晶硅膜、(a3)非晶硅膜、(a4)多晶硅膜(polysilicon film)、(a5)硅氧氮膜、(a6)非晶碳膜、(a7)光致抗蚀膜和(a8)硅氧化膜组成的组中的至少2种以上的层叠结构体进行等离子体蚀刻,仅对(a8)硅氧化膜选择性地进行蚀刻。
[8]
根据[6]或[7]所述的干蚀刻方法,其中,以生成包含S的离子或活性种的方式将[1]~[5]中任一项所述的蚀刻气体组合物等离子体化,并进行蚀刻。
[9]
根据[6]~[8]中任一项所述的干蚀刻方法,其中,在能对(b1)硅氧化膜和(b2)硅氮化膜同时进行蚀刻的等离子体条件下,进行利用[1]~[5]中任一项所述的干蚀刻气体组合物的蚀刻。
发明的效果
根据本发明,可以提供:包含含硫化合物的、相对于低介电常数材料(低-k材料(SiON、SiCN、SiOCN、SiOC))可以对SiO2选择性地进行蚀刻的新型蚀刻气体组合物。
附图说明
图1为示出蚀刻试验的结果的图。
图2为示出本发明的蚀刻组合物的SiO2选择性的图。
图3为以ACL的蚀刻速率为基准以棒状图的形式示出蚀刻试验的结果的图。
具体实施方式
本发明中的干蚀刻气体组合物中包括:包含下述通式(1)所示的饱和且环状的含硫碳氟化合物的混合气体、或单独气体。
通式(1):CxFySz
(式中,x、y和z为2≤x≤5、y≤2x+2、1≤z≤2)
通式(1)中,从干蚀刻气体的操作容易性的观点出发,优选使用满足x=2~5、y=4~10、z=1者。作为适合的化合物,例如可以举出:
Figure BDA0003034368230000041
四氟硫杂环丙烷(C2F4S)、
Figure BDA0003034368230000042
2,2,3,3,4,4-六氟硫杂环丁烷(C3F6S)、
Figure BDA0003034368230000043
2,2,3-三氟-3-(三氟甲基)-硫杂环丙烷(C3F6S)、
Figure BDA0003034368230000051
2,2,3,3,4,4,5,5-八氟四氢噻吩(C4F8S)、
Figure BDA0003034368230000052
2,3-二氟-2,3-双(三氟甲基)-硫杂环丙烷(C4F8S)、
Figure BDA0003034368230000053
2,2-二氟-3,3-双(三氟甲基)-硫杂环丙烷(C4F8S)、
Figure BDA0003034368230000054
2,2,3,3,4,4,5,5,6,6-十氟四氢-2H-噻喃(C5F10S)等。
本发明的干蚀刻气体组合物中,优选使用通式(1)所示的含硫碳氟化合物的纯度为95.0vol%~100.0vol%者。更优选使用纯度为99vol%以上者,进一步优选使用99.9vol%以上者。作为所含的杂质成分,可以举出N2、O2、CO2、H2O、HF、HCl、SO2、CH4等,但这些杂质成分中,H2O、HF、HCl、SO2等腐蚀使气体流通的通路的可能性高,因此,优选尽量通过纯化去除。
本发明的干蚀刻气体组合物中,将通式(1)所示的含硫碳氟化合物与此外的氟碳(FC)气体、氢氟烃(HFC)气体混合而使用,从而跟不与通式(1)所示的化合物混合的情况相比,可以进一步提高蚀刻对象材料对非蚀刻对象材料的选择比。另外,对由非蚀刻对象材料图案化的结构进行蚀刻的情况下,垂直加工精度也改善。
上述的由非蚀刻对象材料图案化的结构中,蚀刻对象材料为SiO2等包含氧的Si系材料的情况下,将通式(1)所示的化合物与CF4、CHF3、C2F6、C3F8、C4F8、C4F6、C5F8等蚀刻气体混合而使用时,在选择性的蚀刻、垂直加工精度良好的蚀刻方面优选。特别是,要求选择性高的情况下,优选与C的数量大的C4F8、C4F6、C5F8的混合。
由非蚀刻对象材料图案化的结构中,蚀刻对象材料为SiN等包含氮的Si系材料的情况下,将通式(1)所示的气体化合物与CHF3、CH2F2、CH3F等HFC气体混合而用于等离子体蚀刻时,在选择性的蚀刻、垂直加工精度良好的蚀刻方面优选。特别是,要求选择性高的情况下,使用C的数量为2以上的HFC气体也是有效的。
本发明的干蚀刻气体组合物中,对于包含通式(1)所示的化合物的组合物,添加选自由O2、O3、CO、CO2、NO、NO2、SO2和SO3组成的组中的至少1种含氧化合物,从而可以得到抑制过剩的沉积物(deposits)、改善蚀刻对象物的蚀刻速率、改善蚀刻对象物对非蚀刻对象材料的选择性之类的效果。
本发明的干蚀刻气体组合物中,可以在包含通式(1)所示的化合物的组合物中添加选自由N2、He、Ar、Ne和Xe组成的组中的至少1种非活性气体。其中,优选使用He、Ar、Xe。
作为本发明的方法中使用的蚀刻气体的例子,可以举出以下的组合物。
(a)通式(1)所示的化合物可以以纯度90vol%以上实施,优选以纯度99vol%以上实施,特别优选以纯度99.999vol%以上实施。
(b)蚀刻中使用的干蚀刻组合物中,通式(1)所示的化合物优选为1~100vol%。
(c)蚀刻中使用的干蚀刻组合物中,除通式(1)所示的化合物以外,优选还包含选自由O2、O3、CO、CO2、NO、NO2、SO2和SO3构成的包含氧原子的化合物组中的至少一者,特别优选使用O2。包含氧原子的化合物的比率相对于通式(1)所示的化合物与包含氧原子的化合物的总量,优选5~50%、特别优选10~35%。
(d)蚀刻中使用的干蚀刻组合物中,优选包含通式(1)所示的化合物、且包含上述包含氧原子的化合物组中的至少一者和/或选自由稀有气体或N2构成的非活性气体组中的至少一者,特别优选使用Ar。蚀刻气体组合物中所含的非活性气体的比率优选1~80vol%、特别优选50~75vol%。
本发明的干蚀刻中使用的干蚀刻装置可以没有特别限制地利用该技术领域中使用的装置。例如可以使用螺旋波方式、高频感应方式、平行平板型方式、磁控方式和微波方式等的装置等。
本发明的干蚀刻方法进行微细的Si系材料的图案晶圆的垂直加工,因此,蚀刻装置必须具备适于离子辅助蚀刻的、能重现低气体压力条件的真空容器的装置。在低压力条件下,等离子体中的颗粒的直进性提高,对基板照射的离子也到达基板而不妨碍其他颗粒,因此,对基板垂直入射的离子增加,有利于垂直加工。本发明的干蚀刻方法中,蚀刻时的真空容器内的压力优选被调节为100Torr~0.1mTorr,进一步优选被调节为100mTorr~0.1mTorr。
本发明的干蚀刻方法中,优选将通式(1)所示的化合物作为气体导入至蚀刻装置的真空容器。因此,本发明的干蚀刻方法中使用的蚀刻装置优选具备将通式(1)所示的化合物作为气体导入、进一步用于调节其导入量的机构。另外,对于该机构,本发明的等离子体蚀刻方法除通式(1)所示的气体化合物以外,根据目的还使用多种前述其他气体化合物、例如O2、Ar等是有效的,因此,优选气体导入、调节导入量的机构也具备4个以上。
实施例
本实施例(蚀刻试验)中,作为等离子体蚀刻装置,使用SAMCO公司制平行平板型的电容耦合等离子体蚀刻装置。沉积膜的组成由SEM-EDX(扫描型电子显微镜/能量色散型X射线分光法)确定。
作为硅氧化膜(SiOm)(m表示自然数),使用通过等离子体CVD在硅晶圆上沉积SiO2膜为1000nm而成者。作为硅氮化膜(SiN),使用通过热CVD在硅晶圆上沉积SiN膜为300nm而成者。作为非晶碳膜(ACL),使用通过等离子体CVD在硅晶圆上沉积ACL为400nm而成者。作为含碳的硅膜(SiOC),使用在硅晶圆上沉积作为Applied Materials公司的注册商标的BlackDiamond-3(以下BD-3)为500nm而成者。作为SiON膜,使用通过等离子体CVD在硅晶圆上沉积SiON为500nm而成者。作为SiCN膜,使用通过等离子体CVD在硅晶圆上沉积SiCN为500nm而成者。作为SiOCN膜,使用通过等离子体CVD在硅晶圆上沉积SiOCN为500nm而成者。
蚀刻时的样品膜厚用光干涉式膜厚测定器测定。蚀刻条件示于下述表1和表3。气体的蚀刻速率用以下的式子算出。
Figure BDA0003034368230000081
A/B选择比用以下的式子算出。
A/B选择比=A膜的蚀刻速率(nm/分钟)÷B膜的蚀刻速率(nm/分钟)
[蚀刻试验]
使用在硅晶圆上分别沉积有SiO2、SiN、ACL等的不同的样品,在表1所示的条件下进行蚀刻试验。对于蚀刻气体,作为比较例,使用不含硫的全氟环丁烷(1,1,2,2,3,3,4,4-八氟环丁烷(C4F8)),作为本发明的实施例,使用包含硫的下述式所示的全氟硫代环戊烷(2,2,3,3,4,4,5,5-八氟四氢噻吩(C4F8S)):
Figure BDA0003034368230000091
[表1]
表1.蚀刻试验条件
Figure BDA0003034368230000092
将试验结果示于图1。图1中,BD-3是指黑金刚石3。Ar总是以50sccm的量流动,蚀刻气体总是以20sccm的量流动,改变氧气(O2)的量(sccm)。氧气的量相对于蚀刻气体(x)与氧气(y)的总计(x+y)超过20%时,使ACL的蚀刻开始。
实施例的蚀刻气体(C4F8S)随着O2比的增加而SiO2的蚀刻速率急激增加,O2比在25%附近SiO2的蚀刻速率成为最大(大致为80nm/分钟),但比较例(C4F8)中,关于SiO2的蚀刻速率也示出同样的行为。另外,实施例的蚀刻气体(C4F8S)和比较例的蚀刻气体(C4F8)均在蚀刻速率的值上未见差异,但是随着O2比的增加而SiN、BD-3、SiON、SiCN、SiOCN的蚀刻速率稍增加,O2比超过20%时,示出开始急激增加的同样的行为。
对于实施例和比较例中得到的结果,求出SiO2/BD-3、SiO2/SiON、SiO2/SiCN、SiO2/SiOCN的蚀刻速率之比,归纳于图2。由图2可知,实施例和比较例中均可以确认到在O2比为20%时蚀刻速率的比大、但在O2比为33%时蚀刻速率之比变小的行为。
对于实施例和比较例中得到的结果,求出O2比的33%下的ACL/SiO2、ACL/SiN、ACL/多晶硅(Poly-Si)、ACL/BD-3、ACL/SiON、ACL/SiCN、ACL/SiOCN的蚀刻速率之比,归纳于图3。由图3可知,实施例的蚀刻气体与比较例的蚀刻气体相比,对于全部材料,与ACL的蚀刻速率比大。
由以上的结果可知,在使用包含硫的蚀刻气体的本发明的实施例、与使用不含硫的现有的蚀刻气体的比较例之间,蚀刻行为上存在显著差异。即,可以认为,本发明的新型蚀刻气体的SiO2与低-k材料(SiON、SiCN、SiOCN、SiOC))之间的选择性跟现有的蚀刻气体同样大,但本发明中,通过采用包含硫的新型化合物,从而即使O2比增大,ACL的蚀刻速率也不增加,因此,ACL与低-k材料之间的蚀刻选择性大于现有的蚀刻气体。另外,通过组合使用本发明的蚀刻气体与现有的蚀刻气体,从而能够改变ACL与低-k材料之间的蚀刻速率的差值,能进行更精密的蚀刻。

Claims (9)

1.一种干蚀刻气体组合物,其包含用通式(1):CxFySz表示的、饱和且环状的含硫碳氟化合物,式中,x、y和z为2≤x≤5、y≤2x、1≤z≤2。
2.根据权利要求1所述的干蚀刻气体组合物,其中,所述含硫碳氟化合物为2,2,3,3,4,4,5,5-八氟四氢噻吩(C4F8S)。
3.根据权利要求1或2所述的干蚀刻气体组合物,其中,以1~100vol%的量包含含硫碳氟化合物。
4.根据权利要求1~3中任一项所述的干蚀刻气体组合物,其中,除所述含硫碳氟化合物之外,还包含选自由O2、O3、CO、CO2、NO、NO2、SO2和SO3组成的组中的至少1种含氧化合物。
5.根据权利要求1~4中任一项所述的干蚀刻气体组合物,其中,除所述含硫碳氟化合物之外,还包含选自由N2、He、Ar、Ne和Xe组成的组中的至少1种非活性气体。
6.一种干蚀刻方法,其包括如下工序:使用权利要求1~5中任一项所述的干蚀刻气体组合物,对包含选自由(a1)包含碳的硅系膜、(a2)结晶硅膜、(a3)非晶硅膜、(a4)多晶硅膜(polysilicon film)、(a5)硅氧氮膜、(a6)非晶碳膜、(a7)光致抗蚀膜、(a8)硅氧化膜和(a9)硅氮化膜组成的组中的至少2种以上的层叠结构体进行等离子体蚀刻,对除(a6)非晶碳膜和(a7)光致抗蚀膜以外单独或同时地选择性地进行蚀刻。
7.一种干蚀刻方法,其包括如下工序:使用权利要求1~5中任一项所述的干蚀刻气体组合物,对包含选自由(a1)包含碳的硅系膜、(a2)结晶硅膜、(a3)非晶硅膜、(a4)多晶硅膜(polysilicon film)、(a5)硅氧氮膜、(a6)非晶碳膜、(a7)光致抗蚀膜和(a8)硅氧化膜组成的组中的至少2种以上的层叠结构体进行等离子体蚀刻,仅对(a8)硅氧化膜选择性地进行蚀刻。
8.根据权利要求6或7所述的干蚀刻方法,其中,以生成包含S的离子或活性种的方式将权利要求1~5中任一项所述的蚀刻气体组合物等离子体化,并进行蚀刻。
9.根据权利要求6~8中任一项所述的干蚀刻方法,其中,在能对(b1)硅氧化膜和(b2)硅氮化膜同时进行蚀刻的等离子体条件下,进行利用权利要求1~5中任一项所述的干蚀刻气体组合物的蚀刻。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010010568A (ko) * 1999-07-21 2001-02-15 윤종용 황 함유 탄화불소 가스를 사용하는 산화막의 건식 에칭 방법
CN103633014A (zh) * 2012-08-21 2014-03-12 中国科学院微电子研究所 半导体器件制造方法
CN105580116A (zh) * 2013-09-09 2016-05-11 乔治洛德方法研究和开发液化空气有限公司 使用蚀刻气体蚀刻半导体结构的方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3109253B2 (ja) 1992-06-29 2000-11-13 ソニー株式会社 ドライエッチング方法
JP3111661B2 (ja) * 1992-07-24 2000-11-27 ソニー株式会社 ドライエッチング方法
JPH07106308A (ja) * 1993-10-08 1995-04-21 Sony Corp ドライエッチング方法
US8133819B2 (en) * 2008-02-21 2012-03-13 Applied Materials, Inc. Plasma etching carbonaceous layers with sulfur-based etchants
JP6636250B2 (ja) 2015-02-12 2020-01-29 関東電化工業株式会社 ドライエッチングガス組成物及びドライエッチング方法
KR102402769B1 (ko) * 2016-01-06 2022-05-26 삼성전자주식회사 반도체 장치
KR102504833B1 (ko) * 2017-11-16 2023-03-02 삼성전자 주식회사 식각 가스 혼합물과 이를 이용한 패턴 형성 방법과 집적회로 소자의 제조 방법

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010010568A (ko) * 1999-07-21 2001-02-15 윤종용 황 함유 탄화불소 가스를 사용하는 산화막의 건식 에칭 방법
CN103633014A (zh) * 2012-08-21 2014-03-12 中国科学院微电子研究所 半导体器件制造方法
US20140199846A1 (en) * 2012-08-21 2014-07-17 Lingkuan Meng Method of manufacturing semiconductor device
CN105580116A (zh) * 2013-09-09 2016-05-11 乔治洛德方法研究和开发液化空气有限公司 使用蚀刻气体蚀刻半导体结构的方法
US20160307764A1 (en) * 2013-09-09 2016-10-20 American Air Liquide, Inc. Method of etching semiconductor structures with etch gas

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