CN112908854A - Method for reducing punch-through effect and component variation of N-tube short-channel component - Google Patents
Method for reducing punch-through effect and component variation of N-tube short-channel component Download PDFInfo
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- CN112908854A CN112908854A CN202110115660.4A CN202110115660A CN112908854A CN 112908854 A CN112908854 A CN 112908854A CN 202110115660 A CN202110115660 A CN 202110115660A CN 112908854 A CN112908854 A CN 112908854A
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 230000000694 effects Effects 0.000 title abstract description 10
- 238000002347 injection Methods 0.000 claims abstract description 59
- 239000007924 injection Substances 0.000 claims abstract description 59
- 229910052796 boron Inorganic materials 0.000 claims abstract description 54
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims abstract description 53
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 30
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 25
- -1 nitrogen ions Chemical class 0.000 claims abstract description 25
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 21
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 21
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 20
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000002253 acid Substances 0.000 claims abstract description 10
- 238000009792 diffusion process Methods 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims description 25
- 229910015900 BF3 Inorganic materials 0.000 claims description 10
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 claims description 10
- CKUAXEQHGKSLHN-UHFFFAOYSA-N [C].[N] Chemical compound [C].[N] CKUAXEQHGKSLHN-UHFFFAOYSA-N 0.000 claims description 9
- 230000009467 reduction Effects 0.000 abstract description 5
- 230000009286 beneficial effect Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 3
- 125000001475 halogen functional group Chemical group 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
Abstract
The invention provides a method for reducing punch-through effect and component variation of an N-tube short-channel component, which comprises the steps of providing a substrate, and forming a well region on the substrate; carrying out boron injection on the well region to form a boron injection region; injecting carbon and nitrogen ions above the boron injection region to form a carbon and nitrogen ion injection region; forming a gate oxide layer on the upper surface of the substrate in the carbon and nitrogen ion injection region; forming grid polycrystalline silicon on the grid oxide layer and forming first side walls on two sides of the grid polycrystalline silicon; injecting aluminum metaaluminate in shallow regions at two sides of the gate oxide layer and below the first side wall to form an aluminum metaaluminate injection region; the metaaluminic acid diffusion and the carbon-nitrogen ion injection region and the boron ion injection region are overlapped; forming an LDD region in the well region above the metaaluminate injection region; forming a second side wall attached to the first side wall; and forming source and drain regions in the well region at two sides of the grid polysilicon. The invention is beneficial to the reduction of circuit leakage and the time sequence convergence; no extra photomask is needed, and the process steps are simple and easy to realize.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for reducing punch-through effect and device variation of an N-tube short-channel device.
Background
With the continuous reduction of the feature size of the CMOS device, the distance between the source terminal and the drain terminal is smaller and smaller, however, since the operating voltage of the device cannot be correspondingly reduced by the sub-threshold swing and the current in the saturation region, the electric field between the source and the drain is enhanced, and the probability of the occurrence of the punch-through effect is increased, thereby causing the leakage problem of the device.
Therefore, a new method is needed to solve the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for reducing punch-through effect and device variation of an N-transistor short channel device, so as to solve the problem of device leakage caused by punch-through between a source and a drain due to the inability of reducing the operating voltage of a CMOS device in the prior art.
To achieve the above and other related objects, the present invention provides a method for reducing punch-through and device variation in an N-transistor short channel device, comprising:
providing a substrate, and forming a well region on the substrate;
secondly, injecting boron into the well region to form a boron injection region;
step three, injecting carbon and nitrogen ions above the boron injection region to form a carbon and nitrogen ion injection region;
fourthly, forming a gate oxide layer on the upper surface of the substrate in the carbon and nitrogen ion injection region;
fifthly, forming grid polysilicon on the grid oxide layer and forming first side walls on two sides of the grid polysilicon;
sixthly, injecting aluminum metaaluminate into the well region on two sides of the gate oxide layer and below the first side wall to form an aluminum metaaluminate injection region; the metaaluminic acid diffusion is overlapped with the carbon-nitrogen ion implantation area and the boron ion implantation area;
step seven, forming an LDD region in the well region above the metaaluminate injection region;
step eight, forming a second side wall attached to the first side wall;
and step nine, forming source and drain regions in the well region on two sides of the grid polycrystalline silicon.
The invention also provides a method for reducing punch-through effect and device variation of the N-tube short channel device, which at least comprises the following steps:
providing a substrate, and forming a well region on the substrate;
secondly, injecting boron into the well region to form a boron injection region;
step three, injecting carbon ions above the boron injection area to form a carbon ion injection area;
forming a gate oxide layer on the upper surface of the substrate of the carbon ion implantation area;
fifthly, forming grid polysilicon on the grid oxide layer and forming first side walls on two sides of the grid polysilicon;
sixthly, injecting aluminum metaaluminate into the well region on two sides of the gate oxide layer and below the first side wall to form an aluminum metaaluminate injection region; the metaaluminic acid diffusion is overlapped with the carbon-nitrogen ion implantation area and the boron ion implantation area;
step seven, forming an LDD region in the well region above the metaaluminate injection region;
step eight, forming a second side wall attached to the first side wall;
and step nine, forming source and drain regions in the well region on two sides of the grid polycrystalline silicon.
The invention also provides a method for reducing punch-through effect and device variation of the N-tube short channel device, which at least comprises the following steps:
providing a substrate, and forming a well region on the substrate;
secondly, injecting boron into the well region to form a boron injection region;
step three, injecting nitrogen ions above the boron injection region to form a nitrogen ion injection region;
forming a gate oxide layer on the upper surface of the substrate of the nitrogen ion implantation area;
fifthly, forming grid polysilicon on the grid oxide layer and forming first side walls on two sides of the grid polysilicon;
sixthly, injecting aluminum metaaluminate into the well region on two sides of the gate oxide layer and below the first side wall to form an aluminum metaaluminate injection region; the metaaluminic acid diffusion is overlapped with the carbon-nitrogen ion implantation area and the boron ion implantation area;
step seven, forming an LDD region in the well region above the metaaluminate injection region;
step eight, forming a second side wall attached to the first side wall;
and step nine, forming source and drain regions in the well region on two sides of the grid polycrystalline silicon.
Preferably, the well region in the first step is a P-type well region.
Preferably, in the second step, boron or boron fluoride is implanted into the well region to form a boron implanted region.
As described above, the method for reducing punch-through effect and device variation of the N-transistor short channel device of the present invention has the following advantages: the invention is beneficial to the reduction of circuit leakage and the time sequence convergence; no extra photomask is needed, and the process steps are simple and easy to realize.
Drawings
FIG. 1 is a schematic view of an N-tube short channel assembly according to the present invention;
FIG. 2 is a flowchart illustrating a method for reducing punch-through and device variation in an N-transistor short channel device according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1-2. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
The present invention provides a method for reducing punch-through and device variation in an N-transistor short channel device, as shown in fig. 2, fig. 2 is a flow chart of the method for reducing punch-through and device variation in an N-transistor short channel device of the present invention, the method at least comprising the steps of:
providing a substrate, and forming a well region on the substrate; the well region in the first step is a P-type well region; as shown in fig. 1, fig. 1 is a schematic structural diagram of an N-tube short channel device according to the present invention. Providing a substrate (Bulk) on which a well region is formed; further, the well region in the first step of this embodiment is a P-type well region.
Secondly, injecting boron into the well region to form a boron injection region; further, in the second step of this embodiment, boron or boron fluoride (BF2) is implanted into the well region to form a boron implanted region;
step three, injecting carbon and nitrogen ions above the boron injection region to form a carbon and nitrogen ion injection region;
fourthly, forming a gate oxide layer 02 on the upper surface of the substrate in the carbon and nitrogen ion implantation area;
fifthly, forming Gate polysilicon (Gate) on the Gate oxide layer 02 and forming first side walls 01 on two sides of the Gate polysilicon (Gate);
sixthly, injecting aluminum metaaluminate into the well region on two sides of the gate oxide layer and below the first side wall to form an aluminum metaaluminate injection region (light Halo); the metaaluminic acid diffusion is overlapped with the carbon-nitrogen ion implantation area and the boron ion implantation area;
step seven, forming an LDD region in the well region above the metaaluminate injection region;
step eight, forming a second side wall attached to the first side wall 01; the second sidewall is not shown in fig. 1.
And step nine, forming Source and Drain regions in the well region on two sides of the grid polycrystalline silicon, wherein the Source region is Source in the figure 1, and the Drain region is Drain in the figure 1.
Example two
The present invention provides a method for reducing punch-through and device variation in an N-transistor short channel device, as shown in fig. 2, fig. 2 is a flow chart of the method for reducing punch-through and device variation in an N-transistor short channel device of the present invention, the method at least comprising the steps of:
providing a substrate, and forming a well region on the substrate; the well region in the first step is a P-type well region; as shown in fig. 1, fig. 1 is a schematic structural diagram of an N-tube short channel device according to the present invention. Providing a substrate (Bulk) on which a well region is formed; further, the well region in the first step of this embodiment is a P-type well region.
Secondly, injecting boron into the well region to form a boron injection region; further, in the second step of this embodiment, boron or boron fluoride (BF2) is implanted into the well region to form a boron implanted region;
step three, injecting carbon ions above the boron injection area to form a carbon ion injection area;
fourthly, forming a gate oxide layer 02 on the upper surface of the substrate of the carbon ion implantation area;
fifthly, forming Gate polysilicon (Gate) on the Gate oxide layer 02 and forming first side walls 01 on two sides of the Gate polysilicon (Gate);
sixthly, injecting aluminum metaaluminate into the well region on two sides of the gate oxide layer and below the first side wall to form an aluminum metaaluminate injection region; the metaaluminic acid diffusion is overlapped with the carbon-nitrogen ion implantation area and the boron ion implantation area;
step seven, forming an LDD region in the well region above the metaaluminate injection region;
step eight, forming a second side wall attached to the first side wall 01; the second sidewall is not shown in fig. 1.
And step nine, forming Source and Drain regions in the well region on two sides of the grid polycrystalline silicon, wherein the Source region is Source in the figure 1, and the Drain region is Drain in the figure 1.
EXAMPLE III
The present invention provides a method for reducing punch-through and device variation in an N-transistor short channel device, as shown in fig. 2, fig. 2 is a flow chart of the method for reducing punch-through and device variation in an N-transistor short channel device of the present invention, the method at least comprising the steps of:
providing a substrate, and forming a well region on the substrate; the well region in the first step is a P-type well region; as shown in fig. 1, fig. 1 is a schematic structural diagram of an N-tube short channel device according to the present invention. Providing a substrate (Bulk) on which a well region is formed; further, the well region in the first step of this embodiment is a P-type well region.
Secondly, injecting boron into the well region to form a boron injection region; further, in the second step of this embodiment, boron or boron fluoride (BF2) is implanted into the well region to form a boron implanted region;
step three, injecting nitrogen ions above the boron injection region to form a nitrogen ion injection region;
fourthly, forming a gate oxide layer 02 on the upper surface of the substrate of the nitrogen ion implantation area;
fifthly, forming Gate polysilicon (Gate) on the Gate oxide layer 02 and forming first side walls 01 on two sides of the Gate polysilicon (Gate);
sixthly, injecting aluminum metaaluminate into the well region on two sides of the gate oxide layer and below the first side wall to form an aluminum metaaluminate injection region (Light Halo); the metaaluminic acid diffusion is overlapped with the carbon-nitrogen ion implantation area and the boron ion implantation area;
step seven, forming an LDD region in the well region above the metaaluminate injection region;
step eight, forming a second side wall attached to the first side wall 01; the second sidewall is not shown in fig. 1.
And step nine, forming Source and Drain regions in the well region on two sides of the grid polycrystalline silicon, wherein the Source region is Source in the figure 1, and the Drain region is Drain in the figure 1.
The invention is beneficial to the reduction of circuit leakage and the time sequence convergence; no extra photomask is needed, and the process steps are simple and easy to realize.
In summary, the invention is beneficial to the reduction of circuit leakage and timing convergence; no extra photomask is needed, and the process steps are simple and easy to realize. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
1. A method for reducing punch-through and device variation in an N-tube short channel device, comprising:
providing a substrate, and forming a well region on the substrate;
secondly, injecting boron into the well region to form a boron injection region;
step three, injecting carbon and nitrogen ions above the boron injection region to form a carbon and nitrogen ion injection region;
fourthly, forming a gate oxide layer on the upper surface of the substrate in the carbon and nitrogen ion injection region;
fifthly, forming grid polysilicon on the grid oxide layer and forming first side walls on two sides of the grid polysilicon;
sixthly, injecting aluminum metaaluminate into the well region on two sides of the gate oxide layer and below the first side wall to form an aluminum metaaluminate injection region; the metaaluminic acid diffusion is overlapped with the carbon-nitrogen ion implantation area and the boron ion implantation area;
step seven, forming an LDD region in the well region above the metaaluminate injection region;
step eight, forming a second side wall attached to the first side wall;
and step nine, forming source and drain regions in the well region on two sides of the grid polycrystalline silicon.
2. The method of claim 1, wherein the method further comprises: the well region in the first step is a P-type well region.
3. The method of claim 1, wherein the method further comprises: and in the second step, boron or boron fluoride is injected into the well region to form a boron injection region.
4. A method for reducing punch-through and device variation in an N-tube short channel device, comprising:
providing a substrate, and forming a well region on the substrate;
secondly, injecting boron into the well region to form a boron injection region;
step three, injecting carbon ions above the boron injection area to form a carbon ion injection area;
forming a gate oxide layer on the upper surface of the substrate of the carbon ion implantation area;
fifthly, forming grid polysilicon on the grid oxide layer and forming first side walls on two sides of the grid polysilicon;
sixthly, injecting aluminum metaaluminate into the well region on two sides of the gate oxide layer and below the first side wall to form an aluminum metaaluminate injection region; the metaaluminic acid diffusion is overlapped with the carbon-nitrogen ion implantation area and the boron ion implantation area;
step seven, forming an LDD region in the well region above the metaaluminate injection region;
step eight, forming a second side wall attached to the first side wall;
and step nine, forming source and drain regions in the well region on two sides of the grid polycrystalline silicon.
5. The method of claim 4, wherein the method further comprises: the well region in the first step is a P-type well region.
6. The method of claim 1, wherein the method further comprises: and in the second step, boron or boron fluoride is injected into the well region to form a boron injection region.
7. A method for reducing punch-through and device variation in an N-tube short channel device, comprising:
providing a substrate, and forming a well region on the substrate;
secondly, injecting boron into the well region to form a boron injection region;
step three, injecting nitrogen ions above the boron injection region to form a nitrogen ion injection region;
forming a gate oxide layer on the upper surface of the substrate of the nitrogen ion implantation area;
fifthly, forming grid polysilicon on the grid oxide layer and forming first side walls on two sides of the grid polysilicon;
sixthly, injecting aluminum metaaluminate into the well region on two sides of the gate oxide layer and below the first side wall to form an aluminum metaaluminate injection region; the metaaluminic acid diffusion is overlapped with the carbon-nitrogen ion implantation area and the boron ion implantation area;
step seven, forming an LDD region in the well region above the metaaluminate injection region;
step eight, forming a second side wall attached to the first side wall;
and step nine, forming source and drain regions in the well region on two sides of the grid polycrystalline silicon.
8. The method of claim 7, wherein the method further comprises: the well region in the first step is a P-type well region.
9. The method of claim 7, wherein the method further comprises: and in the second step, boron or boron fluoride is injected into the well region to form a boron injection region.
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| US8883600B1 (en) * | 2011-12-22 | 2014-11-11 | Suvolta, Inc. | Transistor having reduced junction leakage and methods of forming thereof |
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2021
- 2021-01-28 CN CN202110115660.4A patent/CN112908854A/en active Pending
Patent Citations (8)
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| US5548143A (en) * | 1993-04-29 | 1996-08-20 | Samsung Electronics Co., Ltd. | Metal oxide semiconductor transistor and a method for manufacturing the same |
| US5557129A (en) * | 1994-06-22 | 1996-09-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor MOSFET device having a shallow nitrogen implanted channel region |
| JPH08298319A (en) * | 1995-04-26 | 1996-11-12 | Mitsubishi Electric Corp | Semiconductor device |
| US6025238A (en) * | 1997-12-18 | 2000-02-15 | Advanced Micro Devices | Semiconductor device having an nitrogen-rich punchthrough region and fabrication thereof |
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