CN102683185B - Method for reducing polysilicon gate depletion in carbon co-implantation technological process - Google Patents
Method for reducing polysilicon gate depletion in carbon co-implantation technological process Download PDFInfo
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- CN102683185B CN102683185B CN201210136027.4A CN201210136027A CN102683185B CN 102683185 B CN102683185 B CN 102683185B CN 201210136027 A CN201210136027 A CN 201210136027A CN 102683185 B CN102683185 B CN 102683185B
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Abstract
The invention provides a method for reducing polysilicon gate depletion in a carbon co-implantation technological process, which is used for preparing a PMOS (p-channel metal oxide semiconductor). The method comprises the following steps of: providing a semiconductor substrate, wherein a grid is formed on the semiconductor substrate, the semiconductor substrate at one side of the grid is a source region, and the semiconductor substrate at the other side is a drain region; the method is characterized by further comprising the following steps of: 1, manufacturing a grid flank wall, and performing P type heavily doped baron implantation and thermal annealing; 2, removing the flank wall and performing lightly doped drain implantation, and performing a carbon co-implantation technology; 3, depositing a silicide mask to manufacture new flank walls; and 4, forming self-aligning silicide. According to the invention, the P type heavily doped baron implantation step and the lightly doped drain implantation step in the carbon co-implantation technological process are regulated, so that the problem of not excellently spreading is avoided, and the polysilicon gate depletion is reduced.
Description
Technical field
The present invention relates to preparation PMOS device carbon and assist injection technology, particularly, relate to reduction carbon and assist the method that in injection technology flow process, polysilicon gate exhausts.
Background technology
In the preparation process of semiconductor device, chip is that batch processes, and same wafer is formed large amount of complex device.Along with developing rapidly of very lagre scale integrated circuit (VLSIC), while the integrated level of chip is more and more higher, chip size is also more and more little.
When metal-oxide-semiconductor channel shortening to a certain extent, just there will be short-channel effect (Short Channel Effects).Channel length is reduced to a certain degree, and the proportion that the depletion region of source, drain junction is shared in whole raceway groove increases, and the quantity of electric charge that the silicon face below grid is formed needed for inversion layer reduces, and thus threshold voltage (Vt) reduces, and cut-off current (Ioff) rises simultaneously.Short-channel effect makes the threshold voltage of device very responsive to the length variations of raceway groove, and the control difficulty on semiconductor device technology is strengthened.
In 65 nano-technology techniques in following technology generation, for ultra-shallow junctions (Ultra shallow junction) technique is used to the short-channel effect reducing cmos device, for PMOS device, due to lightly doped drain technique (Lightly Doped Drain, what adopt LDD) is low-energy boron ion implantation technology, in order to reduce the diffusion in a silicon substrate of boron atom, realize for ultra-shallow junctions, can when LDD injects, adopt the auxiliary injection of carbon (Carbon co-implantation) technique, because carbon atom can reduce the diffusion in a silicon substrate of boron atom, so carbon assists injection technology to be conducive to forming for ultra-shallow junctions.
But, due to when carrying out LDD injection, polysilicon gate can carry out the auxiliary injection of carbon equally, (P Plus Implantation) and thermal anneal process is injected at the P type heavy doping boron carried out afterwards, the carbon atom injected in LDD technique, the diffusivity of boron atom at polysilicon gate of P type heavy doping injection can be reduced equally, cause the boron atoms permeating in polysilicon gate insufficient, its result make in polysilicon gate with grid oxygen interface near carrier concentration reduce, when polysilicon gate adding bias voltage, the situation that polysilicon gate and grid oxygen interface more easily occur carrier depletion and make equivalent oxide thickness thickening, namely polysilicon gate exhausts (Poly Depletion) problem and increases the weight of.
Injection technology is assisted to prepare the flow process of PMOS device referring to figs. 1 to the carbon of the prior art shown in Fig. 3.Technique, from the LDD after polysilicon gate etching injects, as shown in Figure 1, is injected and annealing process at LDD, except carrying out boron ion implantation, adopts the auxiliary injection of carbon simultaneously.Carbon after injection can suppress boron atom in the diffusion of substrate silicon.
Then be the formation of side wall (Spacer), P type heavy doping boron injects and thermal anneal process, as shown in Figure 2, due to carbon atom when LDD injects before existence in polysilicon gate, it is also suppressed that P type heavily mixes the diffusion of boron atom in polysilicon gate, and the resistance of polysilicon gate increases.
Then, be the formation of self-aligned silicide, final PMOS cross section as shown in Figure 3.Because heavy doping boron atom does not fully spread, the carrier concentration near polysilicon gate and grid oxygen interface reduces, and poly-si depletion effect is increased the weight of.
Therefore, a kind of carbon that can effectively solve is provided to assist the method for the problem that polysilicon gate exhausts in injection technology flow process just to seem particularly important.
Summary of the invention
The object of the invention is to avoid assisting injection technology flow process due to carbon and the deficiency that causes the boron atoms permeating in polysilicon gate insufficient, reduce carbon and assist polysilicon gate in injection technology flow process to exhaust.
The invention provides a kind of carbon that reduces assists injection technology to prepare the method that in the flow process of PMOS device, polysilicon gate exhausts, for the preparation of PMOS, first provide Semiconductor substrate, described Semiconductor substrate is formed with grid, the Semiconductor substrate of described grid side is source area, the Semiconductor substrate of opposite side is drain region, wherein, also comprises:
Step 1, makes grid curb wall, and carries out carrying out thermal annealing after P type heavy doping boron injects;
Step 2, removes side wall and carries out lightly doped drain injection, and adopting carbon to assist injection technology;
Step 3, deposit silicide mask is to make new side wall;
Step 4, forms self-aligned silicide.
Above-mentioned method, wherein, in described step 3, adopts dry etching to form side wall.
Above-mentioned method, wherein, the silicide formed in described step 4 covers the upper surface of described source area, drain region and grid.
Above-mentioned method, wherein, in described step 2, also comprises the step forming for ultra-shallow junctions.
The present invention assists P type heavy doping boron implantation step in injection technology flow process and lightly doped drain implantation step by adjustment carbon, avoids the problem that cannot spread preferably, reduces polysilicon gate and exhaust.
Accompanying drawing explanation
By reading the detailed description done non-limiting example with reference to the following drawings, the present invention and feature, profile and advantage will become more obvious.Mark identical in whole accompanying drawing indicates identical part.Deliberately proportionally do not draw accompanying drawing, focus on purport of the present invention is shown.In the accompanying drawings, for cheer and bright, be exaggerated section components, for same parts, only indicate wherein part, those skilled in the art can understand in conjunction with embodiment part.
Fig. 1 to Fig. 3 shows prior art, and carbon assists the schematic diagram of each step of injection technology flow process; And
Fig. 4 to Fig. 7 shows according to of the present invention, a kind ofly reduces the schematic diagram that carbon assists each step of the method that polysilicon gate exhausts in injection technology flow process.
Embodiment
Below in conjunction with the drawings and the specific embodiments, the present invention is further elaborated.Embodiment described herein only for explaining the present invention, the protection range be not intended to limit the present invention.
Assist to a kind of carbon that reduces illustrated in fig. 7 the method flow that in injection technology flow process, polysilicon gate exhausts with reference to figure 4, the present invention assists injection technology to prepare the problem that in the flow process of PMOS device, polysilicon gate exhausts for reducing carbon, Semiconductor substrate 100 is first provided, described Semiconductor substrate 100 is formed with grid 101, the Semiconductor substrate 100 of described grid 101 side is source area 102, the Semiconductor substrate 100 of opposite side is drain region 103, wherein, also comprise: step 1, make grid curb wall 201, and carry out carrying out thermal annealing after P type heavy doping boron injects; Step 2, removes side wall 201 and carries out lightly doped drain injection, and adopting carbon to assist injection technology; Step 3, deposit silicide 301 mask is to make new side wall 202; Step 4, forms self-aligned silicide 301.
In step 1, comparison diagram 4 and Fig. 2, owing to not having carbon atom, the boron atom in polysilicon gate is able to abundant diffusion.
In step 2, with reference to figure 5, due to the existence of carbon atom, the diffusion of the boron atom that inhibit lightly doped drain to inject, defines for ultra-shallow junctions 400.But the heavy doping boron atom in polysilicon gate, owing to fully spreading in annealing process before, so can not by auxiliary impact of injecting carbon.Therefore, the carrier concentration near polysilicon gate and grid oxygen interface increases, and poly-si depletion effect weakens.
In a specific embodiment, in described step 3, dry etching is adopted to form side wall 202.
With reference to figure 7, the silicide 301 formed in described step 4 covers the upper surface of described source area 102, drain region 103 and grid 101.
Those skilled in the art can realize described change case in conjunction with prior art and above-described embodiment, and such change case does not affect flesh and blood of the present invention, does not repeat them here.
Above preferred embodiment of the present invention is described.It is to be appreciated that the present invention is not limited to above-mentioned particular implementation, the equipment wherein do not described in detail to the greatest extent and structure are construed as to be implemented with the common mode in this area; Any those of ordinary skill in the art, do not departing under technical solution of the present invention ambit, the Method and Technology content of above-mentioned announcement all can be utilized to make many possible variations and modification to technical solution of the present invention, or being revised as the Equivalent embodiments of equivalent variations, this does not affect flesh and blood of the present invention.Therefore, every content not departing from technical solution of the present invention, according to technical spirit of the present invention to any simple modification made for any of the above embodiments, equivalent variations and modification, all still belongs in the scope of technical solution of the present invention protection.
Claims (4)
1. one kind is reduced carbon and assists the method that in injection technology flow process, polysilicon gate exhausts, for the preparation of PMOS, first provide Semiconductor substrate, described Semiconductor substrate is formed with grid, the Semiconductor substrate of described grid side is source area, the Semiconductor substrate of opposite side is drain region, it is characterized in that, also comprises:
Step 1, makes grid curb wall, and carries out carrying out thermal annealing after P type heavy doping boron injects;
Step 2, removes side wall and carries out lightly doped drain injection, and adopting carbon to assist injection technology;
Step 3, deposit silicide mask is to make new side wall;
Step 4, forms self-aligned silicide.
2. method according to claim 1, is characterized in that, in described step 2, forms for ultra-shallow junctions.
3. method according to claim 1 and 2, is characterized in that, in described step 3, adopts dry etching to form described new side wall.
4. method according to claim 1 and 2, is characterized in that, the self-aligned silicide formed in described step 4 covers the upper surface of described source area, drain region and grid.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7015108B2 (en) * | 2004-02-26 | 2006-03-21 | Intel Corporation | Implanting carbon to form P-type drain extensions |
| CN101728274A (en) * | 2008-10-27 | 2010-06-09 | 台湾积体电路制造股份有限公司 | Reducing poly-depletion through co-implanting carbon and nitrogen = |
| CN102097379A (en) * | 2009-12-10 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device layer |
| CN102437028A (en) * | 2011-11-30 | 2012-05-02 | 上海华力微电子有限公司 | PMOS (p-channel metal-oxide-semiconductor field-effect transistor) source/drain region ion implantation method and corresponding device manufacturing method |
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2012
- 2012-05-04 CN CN201210136027.4A patent/CN102683185B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7015108B2 (en) * | 2004-02-26 | 2006-03-21 | Intel Corporation | Implanting carbon to form P-type drain extensions |
| CN101728274A (en) * | 2008-10-27 | 2010-06-09 | 台湾积体电路制造股份有限公司 | Reducing poly-depletion through co-implanting carbon and nitrogen = |
| CN102097379A (en) * | 2009-12-10 | 2011-06-15 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device layer |
| CN102437028A (en) * | 2011-11-30 | 2012-05-02 | 上海华力微电子有限公司 | PMOS (p-channel metal-oxide-semiconductor field-effect transistor) source/drain region ion implantation method and corresponding device manufacturing method |
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