JPH08298319A - Semiconductor device - Google Patents

Abstract

PURPOSE: To achieve stronger punch-through resistance and a lower threshold voltage by providing a nitrogen implanted region near the surface of a channel region of a MOS field effect transistor. CONSTITUTION: A device isolation region is formed on a silicon substrate 1 by using a prior art MOS-type device fabricating process. Then, a sacrificial oxide film is formed in an active region, and a well and a channel-cut-region are formed by ion implantation. Then, after boron (B), i.e., a channel impurity, is ion-implanted to form a channel doped region 8, a nitrogen implanting region 9 is formed by carrying out ion-implantation of nitrogen atoms to a projected range distance nearly equal to or not more than that of the B atoms. Finally, after the sacrificial oxide film is removed, a gate oxide film 4 and a gate electrode 5 are formed, and source-drain implantation, heat treatment, and aluminum wiring are carried out to fabricate the device. Thus, a device structure with a lower threshold voltage and stronger punch-through resistance can easily and economically be obtained by ion-implanting technique.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the structure of a MOS field effect transistor.

[0002]

2. Description of the Related Art A high performance and highly integrated semiconductor device requires a MOS field effect transistor having a short gate length. For example, a MOS having a gate length of 0.15 .mu.m level is used.
In order to operate the type transistor at an operating voltage of 1.5 to 2.0 V at high speed, the threshold voltage of the transistor is
It is necessary to be about 0.4 to 0.6V. Under the scaling rule of miniaturization, in order to operate a transistor under a high electric field as described above, it is necessary to increase the carrier concentration in the channel region and strengthen the punch-through resistance. Raises the threshold voltage of the MOS type semiconductor element, and the threshold voltage of the MOS type transistor becomes about 1V.

Therefore, as a method for realizing a high punch-through resistance and a low threshold voltage, the impurity profile of the channel region is made nonuniform. That is, the channel concentration may be low on the channel surface and high near the junction depth position of the source / drain diffusion layers.

One of the methods for producing such a channel structure is a method using selective epitaxial growth. For example, a report by Hori et al. (IEDM '93 lecture number LN.6.
In 8), as shown in FIG. 7, 0.1 μm is formed on the heavily-doped region that acts as a punch-through stopper.
A region in which impurities of the same conductivity type are lightly doped by about m is grown, and this low-concentration silicon layer is used as a substantial channel. In the figure, 1 is a silicon substrate, 2 is a high-concentration channel region, 3 is an epitaxially grown low-concentration or intrinsic silicon layer, 4 is a gate oxide film, 5 is a polysilicon gate electrode, 6 is a sidewall, and 7 is a high-concentration diffusion layer. (Source or drain) is shown. By using such a structure, it is possible to realize a low threshold voltage even in a short gate MOS type semiconductor device and to enhance punch-through resistance.

[0005]

However, since the above-mentioned MOS type transistor uses epitaxial growth to form the above-mentioned channel structure, a high-vacuum single crystal manufacturing apparatus is required for manufacturing such an element, which is costly. However, it is difficult to selectively grow p-type and n-type regions on the same substrate by epitaxial growth.
It was difficult to fabricate a MOS type transistor structure. Therefore, the present invention has a low carrier concentration in the channel region near the channel surface, which can be applied to a CMOS transistor structure at low cost without using a special high-vacuum single crystal manufacturing apparatus, and a source / drain diffusion layer. It is an object of the present invention to provide a structure of a MOS field effect transistor which is high in the vicinity of the junction depth position, has a high punch-through resistance, and has a low threshold voltage.

[0006]

Therefore, as a result of intensive studies, the present inventors have found that a nitrogen implantation region is provided in a region near the surface of a channel region of a MOS field effect transistor, so that heat treatment such as impurity activation is performed after ion implantation. The inventors have found that the carrier concentration in the nitrogen-implanted region can be suppressed to a low level even by carrying out, and the above object can be achieved, and the present invention has been completed.

That is, according to the present invention, in a MOS semiconductor device manufactured on a silicon substrate of the first conductivity type, a first semiconductor device sandwiched between a drain region and a source region of the second conductivity type is provided.
The conductivity type channel region has a structure of a MOS semiconductor device including a low concentration channel region provided with a nitrogen atom implantation region and a high concentration channel region provided below the low concentration channel region. Here, the first conductivity type refers to either the n-type or p-type conductivity type, and the second conductivity type refers to the other conductivity type.

According to the present invention, in the MOS type semiconductor device, the first conductivity type channel region sandwiched between the second conductivity type drain region and the source region is a high concentration channel region and the high concentration channel region. Provided below the channel region,
This is a structure of a MOS type semiconductor device including a low concentration channel region provided with a nitrogen atom implantation region.

Further, according to the present invention, the nitrogen-implanted region is formed in a region other than the channel region, and the drain region and the source region of the second conductivity type sandwiching the channel region of the first conductivity type are provided. A low-concentration diffusion layer provided in the vicinity of the channel region and a high-concentration diffusion layer having a high impurity concentration provided on both sides of the low-concentration diffusion layer. It is also a structure of a MOS type semiconductor device in which a nitrogen atom implantation region is formed in at least one of lower parts of the high concentration diffusion layer.

[0010]

According to the present invention, a nitrogen atom-implanted region is also formed by ion implantation in a part of the channel region in which impurities have been implanted by ion implantation, so that the nitrogen atom in the nitrogen atom-implanted region is subjected to heat treatment during the heat treatment. It is possible to suppress the diffusion and activation of the impurity atoms in, and to keep the carrier concentration low in the nitrogen atom-implanted region even after the heat treatment, and substantially the same effect as when the impurity concentration itself is formed to be low can be obtained. A low concentration channel region can be formed. That is, in a MOS semiconductor device manufactured on a silicon substrate of the first conductivity type, a nitrogen atom implantation region is provided in the region near the substrate surface of the channel region where the impurities of the first conductivity type are implanted (see FIG. 2), the carrier concentration in the nitrogen atom-implanted region after heat treatment is kept low, and a low-concentration channel region is formed in the region near the substrate surface, while the lower region of the low-concentration channel region has no nitrogen atoms implanted. Therefore, it becomes a high-concentration channel region having an original carrier concentration (FIG. 3), and a channel structure manufactured by changing the impurity concentration by using the conventional technique can be easily formed only by the ion implantation technique. .

Further, according to the present invention, the heat treatment is performed after the nitrogen atom-implanted region is formed on the substrate side of the impurity-implanted channel region (FIG. 5).
A low-concentration channel region can be formed below the high-concentration channel region in the channel region of the n-type transistor, the carrier concentration distribution in the channel region becomes steep in the depth direction, and the carrier concentration on the substrate side of the conventional channel region is It is possible to suppress the increase in the threshold value (back bias effect) at the time of applying the back bias, which has occurred due to the concentration higher than necessary.

Further, according to the present invention, by forming the nitrogen-implanted region under the source and drain regions, the same effect as in the case of forming the channel region can be obtained. That is, the source / drain regions of the second conductivity type which are provided so as to sandwich the channel region of the first conductivity type,
A MOS transistor including a low-concentration diffusion layer having a low impurity concentration provided in the vicinity of the channel region and a high-concentration diffusion layer having a high impurity concentration provided adjacent to the low-concentration diffusion layer and on the opposite side of the channel region. In, the formation of a nitrogen atom-implanted region in at least one of the lower portion of the low-concentration diffusion layer and the lower portion of the high-concentration diffusion layer can also make the carrier concentration distribution under the source and drain regions after the heat treatment steep. It is possible to suppress the short channel effect due to the deep formation of the drain region.

[0013]

【Example】

(Embodiment 1) FIGS. 1 to 4 show an embodiment of the present invention. 1-4, the same reference numerals as those in FIG. 7 indicate the same or equivalent portions. In FIG. 1, a normal MOS is formed on the silicon substrate 1.
An element isolation region is formed by using a mold element manufacturing process.
Next, a sacrificial oxide film is formed in the active region, and wells and channel cut regions are formed by ion implantation. Next, after ion implantation of boron (B), which is a channel impurity, to form the channel dope region 8, ion implantation of nitrogen atoms is performed, and the projective range (Rp) is approximately the same as or less than that of B atoms.
Then, the nitrogen atom implantation region 9 is formed. The nitrogen dose amount is 1 × 10 ¹⁶ / cm ² or less. FIG. 2 shows the impurity profile in the depth direction at the center of the channel. 10 is a boron concentration and 11 is a profile of nitrogen concentration immediately after injection. The profile of the well and channel cut region is omitted. Finally, after removing the sacrificial oxide film, the gate oxide film 4 and the gate electrode 5 are formed, and source / drain implantation, heat treatment, and aluminum wiring are performed to complete the device.

Further, after removing the sacrificial oxide film, nitrogen atoms may be implanted to perform heat treatment or sacrificial oxidation again to remove defects and the like generated on the surface of the silicon substrate, and the steps of removing the oxide film. The channel ion implantation and the nitrogen atom implantation steps do not matter which step is performed later.

In order to realize a low threshold voltage in the MOS type transistor, the channel concentration may be lowered. On the other hand, in order to suppress the punch-through phenomenon in which a current flows between the drain and the source independently of the gate voltage when the drain voltage is applied between the drain and the source, the channel concentration must be increased. Since this has a trade-off relationship, it is difficult to achieve both lower threshold voltage and enhanced punch-through resistance. However, since the channel concentration near the substrate surface is particularly reflected in the threshold voltage, the concentration near the substrate surface is lowered, while the punch-through phenomenon is suppressed near the drain / source diffusion layer. Since the diffusion layer has a concentration of about 0.15 μm in the submicron region, the above problem can be solved by increasing the concentration in this region.

When an ion implantation method is used to achieve this structure, a high concentration peak of implanted ions is obtained at a depth of about 0.1 μm, but a reflow process for impurity activation, interlayer film flattening, etc. The heat treatment (1) makes the profile smooth after implantation, and in particular, boron atoms segregate near the silicon surface in the oxidation step, and a channel profile having a low concentration in the above surface near-field region cannot be obtained. Therefore, in this embodiment, a nitrogen atom-implanted region is formed in the region near the surface of the substrate in order to maintain the profile immediately after implantation even after the heat treatment and obtain a channel profile in which the region near the surface has a low concentration. That is, by forming the nitrogen atom-implanted region, since nitrogen has a larger diffusion coefficient than boron, the nitrogen atoms diffuse and fill the empty sites before the boron atoms diffuse and move to the empty sites during heat treatment. Therefore, it becomes difficult for boron atoms to diffuse in such a region. In addition, even if it spreads, it will not fit on the site, so it will not be activated. Therefore, in the region near the substrate surface, the diffusion and activation of boron are suppressed by the presence of nitrogen atoms, and the boron injection profile is maintained to some extent, so that the effective carrier concentration near the substrate surface can be kept low. On the other hand, the boron concentration near the bottom of the diffusion layer can be increased, and the channel concentration near the substrate surface, which is particularly reflected in the threshold voltage, can be lowered. The concentration in the vicinity of can be increased.

FIG. 4 shows N with a gate length of 0.3 μm in the case without nitrogen atom implantation (a) and with nitrogen atom implantation (b).
The Vg / Id characteristic of a MOS transistor is shown. This result shows that the channel impurity boron is 8 × 10 ¹² /
This is a case where ion implantation is performed at a cm ² and nitrogen is also implanted near the surface, and the gate width of the transistor is 10
μm, drain voltages are 0.1 V and 2.5 V.
Without nitrogen ion implantation in (a), the threshold voltage is
Although it is about 0.9 V, it can be seen that with the implantation of (b), the activation of boron is suppressed and the threshold voltage is suppressed to about 0.3 V. However, the punch-through resistance is slightly worse in (b), and it is considered that the punch-through resistance can be made similar to that in (a) by optimizing the implantation energy and the implantation amount in the future. It is considered that the same effect can be obtained because nitrogen atoms have a large diffusion coefficient for channel impurity atoms other than boron, and CMOS fabrication is also possible.

(Embodiment 2) FIG. 5 shows another embodiment of the present invention. FIG. 5 shows the impurity profile in the depth direction at the center of the channel of the MOS transistor. The process is the same as that of the first embodiment up to the point of ion-implanting boron as a channel impurity. After that, ion implantation of nitrogen atoms is performed so that peaks are formed in the vicinity of the junction depth positions of the drain and source diffusion layers, and nitrogen atom implantation regions are formed at these positions.

In this embodiment, as shown in FIG. 5, since nitrogen atoms are implanted at a position deeper than the peak position of the channel impurity atom peak, the impurity atom is suppressed from diffusing and activating in such a region, and the effect in this region is reduced. Channel concentration decreases. As a result, it is possible to suppress an increase in the threshold voltage when the back bias is applied and reduce the back bias effect. It should be noted that this embodiment is expected to have the same effect even when other channel impurities are used.

(Embodiment 3) FIG. 6 shows another embodiment of the present invention. FIG. 6 is a configuration diagram showing a main part of the MOS semiconductor device according to the present embodiment. In the present embodiment, after the implantation of the low-concentration diffusion layer (LDD) of the source / drain and the high-concentration diffusion layer (or even before the implantation), ion implantation of nitrogen atoms has a concentration peak near the junction depth position of each diffusion layer. To do so.
As a result, similar to the first and second embodiments, the effective concentration profile of the impurities can be made steep in the lower part of the source / drain diffusion layer by the nitrogen atom, and the short channel effect can be suppressed.

[0021]

As is apparent from the above description, according to the present invention, by forming the nitrogen atom-implanted region near the surface of the channel region of the MOS transistor, the threshold value can be easily and inexpensively obtained by the ion implantation technique. It is possible to obtain an element structure having a low value voltage and a high punch-through resistance.

Further, by forming the nitrogen atom-implanted region under the channel region, the carrier profile under the channel region can be made steep, and the device characteristics can be easily improved.

Further, by forming the nitrogen atom-implanted region under the source and drain regions, the carrier profile under the source and drain regions can be made steep, and the device special feature can be easily improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a main part of a MOS type semiconductor device according to an embodiment of the present invention.

FIG. 2 is a diagram showing an impurity profile in a depth direction at a central portion of a channel of a MOS type semiconductor device according to an embodiment of the present invention.

FIG. 3 is a configuration diagram in which a channel impurity according to an embodiment of the present invention is pseudo-rectangularly provided.

FIG. 4 is an operating characteristic diagram of an NMOS semiconductor device according to an embodiment of the present invention.

FIG. 5 is a configuration diagram showing a main part of a MOS type semiconductor device according to another embodiment of the present invention.

FIG. 6 is a configuration diagram showing a main part of a MOS type semiconductor device according to another embodiment of the present invention.

FIG. 7 is a configuration diagram showing a main part of a MOS type semiconductor device according to a conventional example.

[Explanation of symbols]

1 silicon substrate, 2 high concentration channel region, 3 epitaxially grown low concentration or intrinsic silicon layer, 4
Gate oxide film, 5 polysilicon gate electrode, 6 sidewall, 7 high concentration diffusion layer (source or drain), 8 channel doped region, 9 nitrogen atom implantation region, 10 channel impurity atom depth concentration profile, 11 nitrogen atom Depth concentration profile, 12 Drain-source low concentration diffusion layer.

Claims (3)

[Claims] 1. A MOS semiconductor device manufactured on a silicon substrate of a first conductivity type, wherein a channel region of the first conductivity type sandwiched between a drain region and a source region of the second conductivity type is formed. A low concentration channel region on the surface of the silicon substrate provided with a nitrogen atom implantation region,
A semiconductor device comprising a high-concentration channel region provided below the low-concentration channel region. 2. The semiconductor device according to claim 1, wherein a low-concentration channel region provided with a nitrogen atom implantation region is provided below the high-concentration channel region. 3. The low-concentration diffusion layer having a low impurity concentration provided in the vicinity of the channel region, and the drain region and the source region of the second conductivity type are adjacent to the low-concentration diffusion layer and opposite to the channel region. 3. A high-concentration diffusion layer having a high impurity concentration, which is provided in, and has a nitrogen atom-implanted region in at least one of the lower part of the low-concentration diffusion layer and the lower part of the high-concentration diffusion layer. The semiconductor device according to any one of claims.