CN113314417B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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CN113314417B
CN113314417B CN202010120136.1A CN202010120136A CN113314417B CN 113314417 B CN113314417 B CN 113314417B CN 202010120136 A CN202010120136 A CN 202010120136A CN 113314417 B CN113314417 B CN 113314417B
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region
well
side wall
gate structure
sidewall
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CN113314417A (en
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吴晓婧
兰启明
李琛
董天化
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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Abstract

A semiconductor device and its forming method, the said method adopts the first well region mask layer used when carrying out the first well region ion implantation, as the mask layer when carrying out the first oblique ion implantation subsequently at the same time, so can save the material of the mask layer, reduce the cost; meanwhile, by increasing the distance between the edge surrounding the gate width in the first well region mask layer and the edge of the corresponding first active region, blocking of the first well region mask layer to the first inclined ion implantation can be avoided, and therefore charge leakage caused by ineffective first inclined ion implantation can be avoided, and performance of the semiconductor device can be improved.

Description

Semiconductor device and method of forming the same
Technical Field
The present disclosure relates to semiconductor technology, and more particularly, to a semiconductor device and a method for forming the same.
Background
Metal-oxide-semiconductor (MOS) transistors are important devices in modern integrated circuits. Taking an N-channel enhancement type MOS field effect transistor as an example, the amount of "induced charges" is controlled by using a gate voltage to change the condition of a conductive channel formed by these "induced charges", and then the purpose of controlling the drain current is achieved.
The basic structure of a MOS transistor generally includes a semiconductor substrate, a gate structure on a surface of the semiconductor substrate, and source-drain doped regions in the semiconductor substrate on either side of the gate structure.
However, the performance of the semiconductor device manufactured by the existing method of manufacturing the MOS transistor is still to be improved.
Disclosure of Invention
The embodiment of the invention solves the problems of simplifying the process flow and improving the performance of the semiconductor device.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor device, including:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region, the first region comprises a first active region and a first isolation region surrounding the first active region, and the first isolation region adjacent to the second region is a first edge isolation region;
forming a first gate structure on a first region of the semiconductor substrate, the first gate structure crossing the first active region along a first direction;
after the first grid structure is formed, a first well region mask layer is formed on the second region, the first well region mask layer also extends to part of the surface of the first edge isolation region, the first well region mask layer is provided with a first opening, the first opening is provided with a first side wall, the first side wall comprises a first side wall region and a second side wall region adjacent to the first side wall region, the first side wall region is positioned at the side part of the first active region along the first direction, the second side wall region is positioned at the side part of the first grid structure along the first direction, the second side wall region protrudes towards the second region relative to the first side wall region, and the size of the first opening in the width direction of the first grid structure in the second side wall region is larger than the width of the first grid structure; performing first well ion implantation on the first region by taking the first well region mask layer as a mask, and forming a first well region surrounding the first active region in the first region, wherein the first well region is also positioned at the partial bottom of the first edge isolation region and the bottom of the first grid structure;
and forming a first halo region in the first active region at two sides of the first gate structure by using the first well region mask layer and the first gate structure as masks and adopting first inclined ion implantation, wherein the implantation direction of the first inclined ion implantation is an acute angle with the first direction and the width direction of the first gate structure respectively.
Optionally, the material of the first well region mask layer is photoresist.
Optionally, the ions implanted by the first angled ion implantation are P-type ions.
Optionally, after the first halo implant, the method further comprises: and lightly doped drain injection is carried out on the first active regions at the two sides of the first grid structure, and a first lightly doped region is formed in the first active regions at the two sides of the first grid structure.
Optionally, the second sidewall region includes a first sub sidewall region and second sub sidewall regions adjacent to and located at both sides of the first sub sidewall region, the second sub sidewall region is adjacent to the first sidewall region, the second sub sidewall region is perpendicular to the first sub sidewall region, and the first sub sidewall region is parallel to the first sidewall region and perpendicular to the first direction.
Optionally, the first opening further has a second sidewall, the second sidewall is located at a side portion of the first active region along the width direction of the first gate structure, the second sidewall is adjacent to the first sidewall, and a surface of the second sidewall is a plane.
Optionally, the first region is used to form a first type transistor, and the second region is used to form a second type transistor, the second type transistor and the first type transistor being of opposite device types.
Optionally, the second region includes a second active region and a second isolation region surrounding the second active region, the second isolation region adjacent to the first region is a second edge isolation region, and for adjacent first and second regions, adjacent first and second edge isolation regions are adjacent;
the method for forming the semiconductor device further comprises the following steps:
forming a second gate structure on a second region of the semiconductor substrate during the forming of the first gate structure, the second gate structure crossing the second active region in a second direction;
removing the first well region mask layer after forming the first lightly doped region and the first well region;
after the first well region mask layer is removed, a second well region mask layer is formed on the first region, the second well region mask layer also extends to a part of the surface of the second edge isolation region, the second well region mask layer is provided with a second opening, the second opening is provided with a third side wall, the third side wall comprises a third side wall region and a fourth side wall region adjacent to the third side wall region, the third side wall region is positioned at the side part of the second active region along the second direction, the fourth side wall region is positioned at the side part of the second gate structure along the second direction, the fourth side wall region protrudes towards the first region relative to the third side wall region, and the size of the second opening in the width direction of the second gate structure in the fourth side wall region is larger than the width of the second gate structure;
performing second well ion implantation on the second region by taking the second well region mask layer as a mask, and forming a second well region surrounding the second active region in the second region, wherein the second well region is also positioned at the bottom of part of the second edge isolation region and the bottom of the second gate structure;
and forming a second halo region in a second region of the semiconductor substrate at two sides of the second gate structure by using the second well region mask layer and the second gate structure as masks and adopting second inclined ion implantation, wherein the implantation direction of the second inclined ion implantation is an acute angle with the extension direction of the second gate structure and the width direction of the second gate structure respectively.
The embodiment of the invention also provides a semiconductor device, which comprises:
a semiconductor substrate comprising a first region and a second region, wherein the first region comprises a first active region and a first isolation region surrounding the first active region, and the first isolation region adjacent to the second region is a first edge isolation region;
a first gate structure located on the first region of the semiconductor substrate, the first gate structure crossing the first active region in a first direction;
the first well region is positioned in the first region and surrounds the first active region, the first well region is also positioned at part of the bottom of the first edge isolation region and the bottom of the first grid structure, the first well region is provided with a first well side wall adjacent to the second region, the first well side wall comprises a first well side wall region and a second well side wall region adjacent to the first well side wall region, the first well side wall region is positioned at the side part of the first active region along the first direction, the second well side wall region is positioned at the side part of the first grid structure along the first direction, the second well side wall region protrudes towards the second region relative to the first well side wall region, and the size of the second well side wall region along the width direction of the first grid structure is larger than the width of the first grid structure;
and the first halo region is positioned in the first active region at two sides of the first grid structure.
Optionally, the conductive ions in the first halo region are P-type ions.
Optionally, the semiconductor device further includes: and the first lightly doped region is positioned in the first active region at two sides of the first gate structure.
Optionally, the second well sidewall region includes a first well sidewall region and second well sidewall regions adjacent to and located at two sides of the first well sidewall region, the second well sidewall region is adjacent to the first well sidewall region, the second well sidewall region is perpendicular to the first well sidewall region, and the first well sidewall region is parallel to the first well sidewall region and perpendicular to the first direction.
Optionally, the first well region further has a second well sidewall adjacent to the second region, the second well sidewall being located at a side portion of the first active region in a width direction of the first gate structure, the second well sidewall being adjacent to the first well sidewall.
Optionally, the first region is used to form a first type transistor, and the second region is used to form a second type transistor, the second type transistor and the first type transistor being of opposite device types.
Optionally, the second region includes a second active region and a second isolation region surrounding the second active region, the second isolation region adjacent to the first region is a second edge isolation region, and for adjacent first and second regions, adjacent first and second edge isolation regions are adjacent;
the semiconductor device further includes: a second gate structure located on the second region of the semiconductor substrate, the second gate structure crossing the second active region in a second direction; the second well region is positioned in the second region and surrounds the second active region, the second well region is also positioned at part of the bottom of the second edge isolation region and the bottom of the second gate structure, the second well region is provided with a third well side wall adjacent to the first region, the third well side wall comprises a third well side wall region and a fourth well side wall region adjacent to the third well side wall region, the third well side wall region is positioned at the side part of the second active region along the second direction, the fourth well side wall region is positioned at the side part of the second gate structure along the second direction, the fourth well side wall region protrudes towards the first region relative to the third well side wall region, and the size of the fourth well side wall region along the width direction of the second gate structure is larger than the width of the second gate structure;
and a second halo region in the second active region on both sides of the second gate structure.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the scheme, the first well region mask layer used when the first well region ion implantation is executed can be simultaneously used as the mask layer when the first inclined ion implantation is executed subsequently, so that the material of the mask layer can be saved, and the cost is reduced; the first halo region is formed by adopting first inclined ion implantation, so that the edge morphology of the first halo region, which faces the channel, is arc-shaped at the position, close to the crossing corner of the first gate structure and the first active region, of the first halo region, and the first halo region is used for increasing the inhibition effect of the first halo region on the lateral diffusion of the first lightly doped region and the first source building region and avoiding electric leakage. Meanwhile, the first opening in the first well region mask layer is provided with a second side wall region protruding towards the second region relative to the first side wall region, and the dimension of the second side wall region along the width direction of the first gate structure is larger than the width of the first gate structure, so that the first well region mask layer at the second side wall region is far away from a channel at the bottom of the first gate structure in the channel width direction and the channel length direction, and therefore the first inclined ion implantation inefficiency can be avoided, and the performance of the semiconductor device is improved.
Drawings
Fig. 1 to 4 are schematic views of a device structure formed by steps of a method for forming a semiconductor device according to the prior art;
fig. 5 is a flow chart of a method of forming a semiconductor device in an embodiment of the invention;
fig. 6 to 12 are schematic cross-sectional views showing a forming process of a semiconductor device according to an embodiment of the present invention.
Detailed Description
As described in the background, the performance of the existing semiconductor device is to be improved.
A method for forming a semiconductor device may include:
referring to fig. 1, a semiconductor substrate 100 is provided. The semiconductor substrate 100 includes a first region I and a second region II. The first region I includes a first active region (not shown) and a first isolation region (not shown) surrounding the first active region. Wherein, the first isolation region adjacent to the second region II in the first isolation region is the first edge isolation region 101. The second region II includes a second active region and a second isolation region surrounding the second active region. Wherein, the second isolation region adjacent to the first region I in the second isolation region is the second edge isolation region 201. For adjacent first region I and second region II, adjacent first edge isolation region 101 and second edge isolation region 201 are contiguous.
With continued reference to fig. 1, a first photoresist layer 210 is formed on the second region II, and a first well ion implantation is performed on the first region I using the first photoresist layer 210 as a mask, so as to form a first well region 102 in the semiconductor substrate 100. Wherein the first well region 102 is further located at the bottom of a portion of the first edge isolation region 101. Since the longitudinal depth of the ion implantation is deep when the first well ion implantation is performed, the thickness of the first photoresist layer 210 is required to be large.
Referring to fig. 2, after forming the first well region 102, the first photoresist layer 210 is removed, and a first gate structure 120 is formed on the first region I of the semiconductor substrate 100, and a second gate structure 220 is formed on the second region II; after forming the first gate structure 120 and the second gate structure 220, a second photoresist layer 230 is formed on the second region II.
Next, description will be made taking only an example of forming an NMOS transistor on the first region I.
Referring to fig. 3, a first angled ion implantation is performed on the first region using the second photoresist layer 230 and the first gate structure 120 as masks to form a first halo region 103 within the semiconductor substrate 100. The included angles between the implantation direction of the first inclined ion implantation and the extension direction of the first gate structure 120 and the width direction of the first gate structure 120 are acute angles. The first halo region 103 is formed by adopting first inclined ion implantation, so that the edge morphology of the first halo region, which is close to the corner where the first gate structure and the first active region cross and faces the channel, is in a solitary shape, and the inhibition effect of the first halo region on the lateral diffusion of the first lightly doped region and the first source drain region is increased, and charge leakage is avoided.
The ion implantation longitudinal depth at the time of performing the first oblique ion implantation and the lightly doped drain implantation is shallow, so that the thickness of the second photoresist layer 230 is required to be thin.
With continued reference to fig. 3, a first lightly doped drain implant is performed on the semiconductor substrate 100 on both sides of the first gate structure 120 to form a first lightly doped region 104. In the first oblique ion implantation and the first lightly doped drain implantation, the first gate structure 120 is used as a mask to adjust the width of the channel, so that the first oblique ion implantation and the lightly doped drain implantation are performed after the first gate structure 120 is formed.
As can be seen from the above description, the method includes two photoresist layer forming steps, namely, a first photoresist layer forming step and a second photoresist layer forming step.
In order to save the process and reduce the cost, it is proposed that the first well ion implantation, the first oblique ion implantation and the first lightly doped drain implantation are all performed after the first gate structure is formed, so that the first well ion implantation can be performed using the first photoresist layer as a mask, and the first oblique ion implantation and the first lightly doped drain implantation can be performed using the first photoresist layer and the first gate structure as a mask.
Referring to fig. 4, in the extending direction of the first gate structure, the distance between the edge of the first well region located at the bottom of a portion of the first edge isolation region and the edge of the adjacent first active region is smaller, and the ion beam has a certain inclination angle when performing the first inclined ion implantation.
In order to solve the problems in the prior art, the first well region mask layer used when the first well region ion implantation is performed according to the technical scheme adopted by the embodiment of the invention can be simultaneously used as the mask layer when the first inclined ion implantation is performed subsequently, so that the material of the mask layer can be saved, and the cost is reduced; meanwhile, the first opening in the first well region mask layer is provided with a second side wall region protruding towards the second region relative to the first side wall region, and the dimension of the second side wall region along the width direction of the first gate structure is larger than the width of the first gate structure, so that the first well region mask layer at the second side wall region is far away from a channel at the bottom of the first gate structure in the channel width direction and the channel length direction, the first inclined ion implantation inefficiency can be avoided, and the performance of the semiconductor device is improved.
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 5 is a schematic diagram showing a method for forming a semiconductor device according to an embodiment of the present invention. Referring to fig. 5, a method for forming a semiconductor device according to an embodiment of the present invention may specifically include the following steps:
step S501: providing a semiconductor substrate; the semiconductor substrate comprises a first region and a second region, the first region comprises a first active region and a first isolation region surrounding the first active region, and the first isolation region adjacent to the second region is a first edge isolation region.
Step S502: forming a first gate structure on a first region of the semiconductor substrate, the first gate structure crossing the first active region along a first direction;
step S503: after the first grid structure is formed, a first well region mask layer is formed on the second region, the first well region mask layer also extends to part of the surface of the first edge isolation region, the first well region mask layer is provided with a first opening, the first opening is provided with a first side wall, the first side wall comprises a first side wall region and a second side wall region adjacent to the first side wall region, the first side wall region is positioned at the side part of the first active region along the first direction, the second side wall region is positioned at the side part of the first grid structure along the first direction, the second side wall region protrudes towards the second region relative to the first side wall region, and the size of the first opening in the width direction of the first grid structure in the second side wall region is larger than the width of the first grid structure;
step S504: performing first well ion implantation on the first region by taking the first well region mask layer as a mask, and forming a first well region surrounding the first active region in the first region, wherein the first well region is also positioned at the partial bottom of the first edge isolation region and the bottom of the first grid structure;
step S505: and forming a first halo region in the first active region at two sides of the first gate structure by using the first well region mask layer and the first gate structure as masks and adopting first inclined ion implantation, wherein the implantation direction of the first inclined ion implantation is an acute angle with the first direction and the width direction of the first gate structure respectively.
The method of forming the semiconductor device in the embodiment of the present invention will be described in further detail with reference to fig. 6 to 12.
Referring to fig. 6 to 12, a method for forming a semiconductor device according to an embodiment of the present invention specifically includes:
referring to fig. 6, a semiconductor substrate 100 is provided, the semiconductor substrate 100 including a first region I and a second region II.
In particular implementations, the semiconductor substrate 100 provides a handling platform for subsequent processing.
The semiconductor substrate 100 may be a silicon substrate, and may also be germanium, silicon carbide, gallium arsenide, indium gallium arsenide, a silicon substrate on an insulating base, a germanium substrate on an insulator, or the like.
The first region I of the semiconductor substrate 100 includes a first active region (not shown) and a first isolation region (not shown) surrounding the first active region. Wherein, the first isolation region adjacent to the second region II in the first isolation region is the first edge isolation region 101. The second region II of the semiconductor substrate 100 includes a second active region and a second isolation region surrounding the second active region. Wherein, the second isolation region adjacent to the first region I in the second isolation region is the second edge isolation region 201. For adjacent first region I and second region II, adjacent first edge isolation region 101 and second edge isolation region 201 are contiguous.
In this embodiment, the first region I has only one first active region, and the second region II has only one second active region. In other embodiments, the number of the first active regions in the first region I and the second active regions in the second region II may be two or more, which is not limited herein.
It should be noted that, the first region I is used to form a first type transistor, the second region II is used to form a second type transistor, and the device types of the second type transistor and the first type transistor are opposite. For example, the first region I is used to form an N-type transistor, and the second region II is used to form a P-type transistor; alternatively, the first region I is used to form a P-type transistor and the second region II is used to form an N-type transistor.
Referring to fig. 7, a first gate structure 110 is formed on a first region I of the semiconductor substrate 100.
The first gate structure 110 spans a first active region (not shown). When the first region I includes a plurality of first active regions and a plurality of first isolation regions, the first gate structure 110 also spans the first isolation regions between the adjacent first active regions along the extending direction of the first gate structure.
In the present embodiment, during the process of forming the first gate structure 110, the second gate structure 210 is also formed on the second region II of the semiconductor substrate 100, and the second gate structure 210 spans the second active region of the second region II.
Referring to fig. 8, after forming the first gate structure 110, a first well region mask layer 220 is formed on the second region II, and the first well region mask layer 220 covers the entire second region II and extends onto a portion of the surface of the first edge isolation region 101.
The first well region mask layer is used for performing first well ion implantation on the first region I to form a first well region in the semiconductor substrate.
Fig. 9 is a schematic top view of fig. 8. Referring to fig. 9, in the present embodiment, the first well region mask layer has a first opening, and the first opening has a first sidewall 91 and a second sidewall 92 adjacent to each other. Wherein:
the first sidewall 91 includes a first sidewall region 911 and a second sidewall region 912 adjoining the first sidewall region 911. The first sidewall region 911 is located at a side of the first active region in the first direction, the second sidewall region 912 is located at a side of the first gate structure in the first direction, the second sidewall region 912 protrudes toward the second region with respect to the first sidewall region 911, and a size of the first opening in the width direction of the first gate structure in the second sidewall region 912 is greater than a width of the first gate structure. The second sidewall region 912 specifically includes a first sub-sidewall region 9121 and second sub-sidewall regions 9122 adjacent to the first sub-sidewall region 9121 and located on two sides of the first sub-sidewall region 9121, the second sub-sidewall region 9121 is adjacent to the first sidewall region 91, the second sub-sidewall region 9122 is perpendicular to the first sub-sidewall region 9121, and the first sub-sidewall region 9121 is parallel to the first sidewall region 91 and perpendicular to the first direction.
The second sidewall 92 is located at a side portion of the first active region along the width direction of the first gate structure, the second sidewall 92 is adjacent to the first sidewall 91, and a surface of the second sidewall 92 is a plane.
Compared with the first well region mask layer corresponding to the first well region shown in fig. 4, the first opening in the first well region mask layer in the embodiment of the present invention has the second sidewall region 912 protruding toward the second region with respect to the first sidewall region 911, and the dimension of the second sidewall region 912 along the width direction of the first gate structure is greater than the width of the first gate structure, so that the first well region mask layer at the second sidewall region 912 moves away from the channel at the bottom of the first gate structure in both the channel width direction and the channel length direction, and the shadow formed by the first well region mask layer at the second sidewall region 912 moves away from the channel at the bottom of the first gate structure in both the channel width direction and the channel length direction, thereby avoiding the inefficiency of the ion implantation during the first oblique ion implantation, and improving the performance of the semiconductor device.
Referring to fig. 10, a first well ion implantation is performed on the first region using the first well mask layer 220 as a mask, a first well region 103 surrounding the first active region 102 is formed in the first region, and the first well region 103 is further located at a portion of the bottom of the first edge isolation region 101 and at the bottom of the first gate structure 110.
The first well region 103 is formed by performing first well ion implantation to dope different types of impurity ions into the semiconductor substrate 100 according to the type of the formed MOS transistor. Specifically, when the MOS transistor to be formed on the first region is an N-type transistor, the impurity ions implanted by the first well ion implantation are P-type impurity ions, and the P-type impurity ions are one or more of boron ions, gallium ions and indium ions; when the MOS transistor to be formed on the first region I is a P-type transistor, the impurity ions implanted by the first well ion implantation are N-type impurity ions, and the N-type impurity ions are one or more of phosphorus ions, arsenic ions and gallium ions.
In a specific implementation, the ion implantation energy when the first well ion implantation is performed is relatively high, and the ions to be implanted when the first well ion implantation is performed are implanted into the semiconductor substrate at the bottom of the first gate structure through the first gate structure, so the thickness of the first well region mask layer 210 is relatively high, so as to avoid the ions implanted when the first well ion implantation is performed from being implanted into the second region.
Referring to fig. 11, with the first well region mask layer 210 and the first gate structure 120 as masks, a first halo region 104 is formed in the first active region at both sides of the first gate structure 120 by using a first oblique ion implantation.
In a specific implementation, the included angles between the implantation direction of the first inclined ion implantation and the first direction and the width direction of the first gate structure are respectively acute angles.
When the MOS transistor to be formed on the first region is an N-type transistor, performing first inclined ion implantation to implant ions into P-type ions; when the MOS transistor to be formed on the first region is a P-type transistor, the ions implanted by the first inclined ion implantation are N-type ions.
Referring to fig. 12, after the first oblique ion implantation is performed, the first active regions on both sides of the first gate structure are lightly doped drain implanted with the first well mask layer 210 and the first gate structure 120 as masks, and the first lightly doped regions 105 are formed in the first active regions on both sides of the first gate structure.
When the MOS transistor to be formed on the first region is an N-type transistor, implanting ions into the first region by adopting first inclined ion implantation to form N-type ions; when the MOS transistor to be formed on the first region I is a P-type transistor, the ions implanted by the first oblique ion implantation are P-type ions.
In other embodiments, before forming the first halo region, the first active region on both sides of the first gate structure may be lightly doped drain implanted with the first well region mask layer and the first gate structure as masks, and a first lightly doped region may be formed in the first active region on both sides of the first gate structure.
The following describes the process of performing the second well ion implantation, the second inclined ion implantation, the lightly doped drain implantation, and the like in the second region.
Forming a second gate structure 220 on a second region of the semiconductor substrate during the forming of the first gate structure 120, the second gate structure crossing the second active region in a second direction;
after forming the first lightly doped region 104 and the first well region 103, removing the first well region mask layer 210;
after removing the first well region mask layer 210, forming a second well region mask layer on the first region, wherein the second well region mask layer further extends to a part of the surface of the second edge isolation region, the second well region mask layer is provided with a second opening therein, the second opening is provided with a third side wall, the third side wall comprises a third side wall region and a fourth side wall region adjacent to the third side wall region, the third side wall region is positioned at the side part of the second active region along the second direction, the fourth side wall region is positioned at the side part of the second gate structure along the second direction, the fourth side wall region protrudes towards the first region relative to the third side wall region, and the size of the second opening in the width direction of the second gate structure in the fourth side wall region is larger than the width of the second gate structure;
performing second well ion implantation on the second region by taking the second well region mask layer as a mask, and forming a second well region surrounding the second active region in the second region, wherein the second well region is also positioned at the bottom of part of the second edge isolation region and the bottom of the second gate structure;
and forming a second halo region in a second region of the semiconductor substrate at two sides of the second gate structure by using the second well region mask layer and the second gate structure as masks and adopting second inclined ion implantation, wherein the implantation direction of the second inclined ion implantation is an acute angle with the extension direction of the second gate structure and the width direction of the second gate structure respectively.
In one embodiment, the first direction is parallel to the second direction. In other embodiments, the first direction and the second direction are at an angle greater than zero degrees.
The embodiment of the invention also provides a semiconductor device. With continued reference to fig. 11 and 12, a semiconductor device according to an embodiment of the present invention includes:
a semiconductor substrate 100, wherein the semiconductor substrate 100 comprises a first region and a second region, the first region comprises a first active region and a first isolation region surrounding the first active region, and the first isolation region adjacent to the second region is a first edge isolation region;
a first gate structure 120 located on the first region of the semiconductor substrate, the first gate structure 120 crossing the first active region in a first direction;
a first well region 103 surrounding the first active region in the first region. The first well region 103 is further located at a part of the bottom of the first edge isolation region 101 and at the bottom of the first gate structure 110, the first well region 103 has a first well sidewall adjacent to the second region, the first well sidewall includes a first well sidewall region and a second well sidewall region adjacent to the first well sidewall region, the first well sidewall region is located at a side portion of the first active region along the first direction, the second well sidewall region is located at a side portion of the first gate structure along the first direction, the second well sidewall region protrudes toward the second region with respect to the first well sidewall region, and a dimension of the second well sidewall region along a width direction of the first gate structure is greater than a width of the first gate structure. In an embodiment, the second well sidewall region includes a first well sidewall region and second well sidewall regions adjacent to and located at two sides of the first well sidewall region, the second well sidewall region is adjacent to the first well sidewall region, the second well sidewall region is perpendicular to the first well sidewall region, and the first well sidewall region is parallel to the first well sidewall region and perpendicular to the first direction.
In this embodiment, the first well region further has a second well sidewall adjacent to the second region, the second well sidewall is located at a side portion of the first active region along the width direction of the first gate structure, and the second well sidewall is adjacent to the first well sidewall.
A first halo region 104 in the first active region on either side of the first gate structure 120.
In this embodiment, the semiconductor device further includes: a first lightly doped region 105 in the first active region on either side of the first gate structure 120.
In this embodiment, the second region includes a second active region and a second isolation region surrounding the second active region, the second isolation region adjacent to the first region is a second edge isolation region, and for the adjacent first region and second region, the adjacent first edge isolation region and second edge isolation region are adjacent;
the semiconductor device further includes: a second gate structure located on the second region of the semiconductor substrate, the second gate structure crossing the second active region in a second direction; the second well region is positioned in the second region and surrounds the second active region, the second well region is also positioned at part of the bottom of the second edge isolation region and the bottom of the second gate structure, the second well region is provided with a third well side wall adjacent to the first region, the third well side wall comprises a third well side wall region and a fourth well side wall region adjacent to the third well side wall region, the third well side wall region is positioned at the side part of the second active region along the second direction, the fourth well side wall region is positioned at the side part of the second gate structure along the second direction, the fourth well side wall region protrudes towards the first region relative to the third well side wall region, and the size of the fourth well side wall region along the width direction of the second gate structure is larger than the width of the second gate structure;
and a second halo region in the second active region on both sides of the second gate structure.
The embodiment of the invention also provides a semiconductor device, which comprises: the semiconductor device comprises a semiconductor substrate, shallow trench isolation structures positioned in the semiconductor substrate, a grid structure positioned on the semiconductor substrate between the shallow trench isolation structures and source-drain doped regions positioned on two sides of the grid structure. As compared with the prior art, the N-well region of the semiconductor device in the embodiment of the present invention has an extension region extending along the length direction of the bottom channel of the gate structure, and the width of the extension region is greater than the width of the bottom channel of the gate structure, which is specifically described in detail in the method for forming the semiconductor device and is not repeated.
By adopting the scheme in the embodiment of the invention, the first well region mask layer used when the first well region ion implantation is executed can be simultaneously used as the mask layer when the first inclined ion implantation is executed subsequently, so that the material of the mask layer can be saved, and the cost is reduced; meanwhile, by increasing the distance between the edge surrounding the gate width in the first well region mask layer and the edge of the corresponding first active region, blocking of the first well region mask layer to the first inclined ion implantation can be avoided, and therefore charge leakage caused by ineffective first inclined ion implantation can be avoided, and performance of the semiconductor device can be improved.
The method and system according to the embodiments of the present invention are described in detail above, and the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (15)

1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region, the first region comprises a first active region and a first isolation region surrounding the first active region, and the first isolation region adjacent to the second region is a first edge isolation region;
forming a first gate structure on a first region of the semiconductor substrate, the first gate structure crossing the first active region along a first direction;
after the first grid structure is formed, a first well region mask layer is formed on the second region, the first well region mask layer also extends to part of the surface of the first edge isolation region, the first well region mask layer is provided with a first opening, the first opening is provided with a first side wall, the first side wall comprises a first side wall region and a second side wall region adjacent to the first side wall region, the first side wall region is positioned at the side part of the first active region along the first direction, the second side wall region is positioned at the side part of the first grid structure along the first direction, the second side wall region protrudes towards the second region relative to the first side wall region, and the size of the first opening in the width direction of the first grid structure in the second side wall region is larger than the width of the first grid structure;
performing first well ion implantation on the first region by taking the first well region mask layer as a mask, forming a first well region surrounding the first active region in the first region, wherein the first well region is also positioned at the partial bottom of the first edge isolation region and the bottom of the first grid structure;
and forming a first halo region in the first active region at two sides of the first gate structure by using the first well region mask layer and the first gate structure as masks and adopting first inclined ion implantation, wherein the implantation direction of the first inclined ion implantation is an acute angle with the first direction and the width direction of the first gate structure respectively.
2. The method of claim 1, wherein the material of the first well region mask layer is photoresist.
3. The method of claim 1, wherein the ions implanted by the first angled ion implantation are P-type ions.
4. The method of forming a semiconductor device of claim 1, further comprising, after the first halo implant: and lightly doped drain injection is carried out on the first active regions at the two sides of the first grid structure, and a first lightly doped region is formed in the first active regions at the two sides of the first grid structure.
5. The method of forming a semiconductor device according to claim 1, wherein the second sidewall region includes a first sub sidewall region and a second sub sidewall region adjacent to and on both sides of the first sub sidewall region, the second sub sidewall region being adjacent to the first sidewall region, the second sub sidewall region being perpendicular to the first sub sidewall region, the first sub sidewall region being parallel to the first sidewall region and perpendicular to the first direction.
6. The method of forming a semiconductor device according to claim 1, wherein the first opening further has a second sidewall located on a side portion of the first active region in a width direction of the first gate structure, the second sidewall being adjacent to the first sidewall, a surface of the second sidewall being planar.
7. The method of forming a semiconductor device according to claim 1, wherein the first region is used to form a first type transistor and the second region is used to form a second type transistor, the second type transistor being of an opposite device type to the first type transistor.
8. The method of forming a semiconductor device according to claim 4, wherein the second region includes a second active region and a second isolation region surrounding the second active region, the second isolation region adjacent to the first region being a second edge isolation region, and for adjacent first and second regions, adjacent first and second edge isolation regions are contiguous;
the method for forming the semiconductor device further comprises the following steps:
forming a second gate structure on a second region of the semiconductor substrate during the forming of the first gate structure, the second gate structure crossing the second active region in a second direction;
removing the first well region mask layer after forming the first lightly doped region and the first well region;
after the first well region mask layer is removed, a second well region mask layer is formed on the first region, the second well region mask layer also extends to a part of the surface of the second edge isolation region, the second well region mask layer is provided with a second opening, the second opening is provided with a third side wall, the third side wall comprises a third side wall region and a fourth side wall region adjacent to the third side wall region, the third side wall region is positioned at the side part of the second active region along the second direction, the fourth side wall region is positioned at the side part of the second gate structure along the second direction, the fourth side wall region protrudes towards the first region relative to the third side wall region, and the size of the second opening in the width direction of the second gate structure in the fourth side wall region is larger than the width of the second gate structure;
performing second well ion implantation on the second region by taking the second well region mask layer as a mask, and forming a second well region surrounding the second active region in the second region, wherein the second well region is also positioned at the bottom of part of the second edge isolation region and the bottom of the second gate structure;
and forming a second halo region in a second region of the semiconductor substrate at two sides of the second gate structure by using the second well region mask layer and the second gate structure as masks and adopting second inclined ion implantation, wherein the implantation direction of the second inclined ion implantation is an acute angle with the extension direction of the second gate structure and the width direction of the second gate structure respectively.
9. A semiconductor device, comprising:
a semiconductor substrate comprising a first region and a second region, wherein the first region comprises a first active region and a first isolation region surrounding the first active region, and the first isolation region adjacent to the second region is a first edge isolation region;
a first gate structure located on the first region of the semiconductor substrate, the first gate structure crossing the first active region in a first direction;
the first well region is positioned in the first region and surrounds the first active region, the first well region is also positioned at part of the bottom of the first edge isolation region and the bottom of the first grid structure, the first well region is provided with a first well side wall adjacent to the second region, the first well side wall comprises a first well side wall region and a second well side wall region adjacent to the first well side wall region, the first well side wall region is positioned at the side part of the first active region along the first direction, the second well side wall region is positioned at the side part of the first grid structure along the first direction, the second well side wall region protrudes towards the second region relative to the first well side wall region, and the size of the second well side wall region along the width direction of the first grid structure is larger than the width of the first grid structure;
and the first halo region is positioned in the first active region at two sides of the first grid structure.
10. The semiconductor device of claim 9, wherein the conductive ions in the first halo region are P-type ions.
11. The semiconductor device according to claim 9, further comprising: and the first lightly doped region is positioned in the first active region at two sides of the first gate structure.
12. The semiconductor device of claim 9, wherein the second well sidewall region comprises a first well sidewall region and second well sidewall regions adjacent to and on opposite sides of the first well sidewall region, the second well sidewall region being adjacent to the first well sidewall region, the second well sidewall region being perpendicular to the first well sidewall region, the first well sidewall region being parallel to the first well sidewall region and perpendicular to the first direction.
13. The semiconductor device of claim 9, wherein the first well region further has a second well sidewall adjacent to the second region, the second well sidewall being located on a side of the first active region in a width direction of the first gate structure, the second well sidewall being adjacent to the first well sidewall.
14. The semiconductor device of claim 9, wherein the first region is for forming a first type transistor and the second region is for forming a second type transistor, the second type transistor being of an opposite device type than the first type transistor.
15. The semiconductor device of claim 9, wherein the second region comprises a second active region and a second isolation region surrounding the second active region, the second isolation region adjacent the first region being a second edge isolation region, adjacent first and second edge isolation regions being contiguous for adjacent first and second regions;
the semiconductor device further includes: a second gate structure located on the second region of the semiconductor substrate, the second gate structure crossing the second active region in a second direction; the second well region is positioned in the second region and surrounds the second active region, the second well region is also positioned at part of the bottom of the second edge isolation region and the bottom of the second gate structure, the second well region is provided with a third well side wall adjacent to the first region, the third well side wall comprises a third well side wall region and a fourth well side wall region adjacent to the third well side wall region, the third well side wall region is positioned at the side part of the second active region along the second direction, the fourth well side wall region is positioned at the side part of the second gate structure along the second direction, the fourth well side wall region protrudes towards the first region relative to the third well side wall region, and the size of the fourth well side wall region along the width direction of the second gate structure is larger than the width of the second gate structure;
and a second halo region in the second active region on both sides of the second gate structure.
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US6429082B1 (en) * 2000-09-26 2002-08-06 United Microelectronics Corp. Method of manufacturing a high voltage using a latid process for forming a LDD
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