CN112599485B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN112599485B
CN112599485B CN202010690912.1A CN202010690912A CN112599485B CN 112599485 B CN112599485 B CN 112599485B CN 202010690912 A CN202010690912 A CN 202010690912A CN 112599485 B CN112599485 B CN 112599485B
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conductive layer
semiconductor device
conductor
conductive
disposed
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CN112599485A (zh
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许平
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Nanya Technology Corp
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Nanya Technology Corp
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Abstract

本发明公开一种半导体装置及其制造方法。该半导体装置包括一第一导电体、一第二导电体和该第一导电体分离设置、多个衬垫分别对应地贴设于该第一导电体的侧表面及该第二导电体的侧表面及一第一绝缘区段设置于该第一导电体和该第二导电体之间。

Description

半导体装置及其制造方法
技术领域
本公开主张2019/09/17申请的美国正式申请案第16/573,549号的优先权及益处，该美国正式申请案的内容以全文引用的方式并入本文中。
本公开涉及一种半导体装置及其制造方法。更具体地，一种具有衬垫的半导体装置与其相关制造方法。
背景技术
半导体装置被用于各种电子设备的应用当中，例如个人电脑、手机、数码相机和其他电子设备。为满足对计算能力不断增长的需求，半导体装置的尺寸不断地缩小。然而，半导体装置微型化的过程使其制造方面遭遇着各种问题，这些问题将影响半导体装置最终的电特性、品质和产率。因此，在提高半导体装置的性能、质量、良率、效能和可靠性等方面仍然面临挑战。
上文的“现有技术”说明仅提供背景技术，并未承认上文的“现有技术”说明公开本公开的标的，不构成本公开的现有技术，且上文的“现有技术”的任何说明均不应作为本公开的任一部分。
发明内容
本公开的一方面提供一种半导体装置，该半导体装置包括一第一导电体、一第二导电体和该第一导电体分离设置、多个衬垫分别对应地贴设于该第一导电体的侧表面及该第二导电体的侧表面及一第一绝缘区段设置于该第一导电体和该第二导电体之间。
在本公开的一些实施例中，该半导体装置还包括一第一掺杂区域设置于该第一导电体的顶面及该第一导电体的侧表面。
在本公开的一些实施例中，该第一绝缘区段包括一嵌入部及一延伸部，该嵌入部设置于所述多个衬垫之间，而该延伸部设置于该嵌入部上。
在本公开的一些实施例中，该延伸部的两侧分别对应地设置于该第一导电体的顶面的一部分及该第二导电体的顶面的一部分上。
在本公开的一些实施例中，该延伸部的宽度大于或等于该第一导电体和该第二导电体间的水平距离。
在本公开的一些实施例中，该半导体装置还包括一第一导电垫和一第二导电垫，其中该第一导电垫设置于该第一导电体的顶面，该第二导电垫设置于该第二导电体的顶面。
在本公开的一些实施例中，该第一导电垫包括一第一底部导电层及一第一中间导电层，该第一底部导电层设置于该第一导电体的顶面，该第一中间导电层设置于该第一底部导电层上。
在本公开的一些实施例中，该第一导电垫包括一第一底部导电层、一第一中间导电层及一第一顶部导电层，该第一底部导电层设置于该第一导电体的顶面，该第一中间导电层设置于该第一底部导电层上，该第一顶部导电层设置于该第一中间导电层上。
在本公开的一些实施例中，该第一底部导电层的一侧覆盖该延伸部的顶面的一部分。
在本公开的一些实施例中，该第一导电垫是由铝、银、白金、铅、镍、金、铜、或其合金所形成。
在本公开的一些实施例中，该第一导电垫和该第二导电垫间的水平距离小于该延伸部的宽度。
在本公开的一些实施例中，该半导体装置还包括一第一钝化区段设置于该第一导电垫及该第二导电垫之间。
本公开的另一方面提供一种半导体装置的制造方法，其包括提供一具有一第一表面及一第二表面的基底，该第二表面和该第一表面相对、内凹地形成一沟渠于该基底的第一表面、形成多个衬垫于该沟渠的侧表面、形成一第一绝缘区段填满该沟渠以及自该第二表面移除部分的基底以曝露该第一绝缘区段和所述多个衬垫。
在本公开的一些实施例中，该半导体装置的制造方法还包括形成一掺杂区域于该基底中，其中该掺杂区域形成于该基底的第一表面、该沟渠的侧表面及该沟渠的底部。
在本公开的一些实施例中，所述多个衬垫是由钛、氮化钛、钛钨合金、钽、氮化钽、或其组合所形成。
在本公开的一些实施例中，该第一绝缘区段包括一嵌入部及一延伸部，该嵌入部形成于该沟渠中并覆盖所述多个衬垫，该延伸部形成于该嵌入部上。
在本公开的一些实施例中，该延伸部更覆盖该基底的第一表面的一部分。
在本公开的一些实施例中，该半导体装置的制造方法还包括形成一第一导电垫和一第二导电垫于该基底的上方。
在本公开的一些实施例中，该第一导电垫包括一第一底部导电层、一第一中间导电层及一第一顶部导电层，该第一底部导电层形成于该基底上，该第一中间导电层形成于该第一底部导电层上，该第一顶部导电层形成于该第一中间导电层上。
在本公开的一些实施例中，该半导体装置的制造方法还包括形成一第一钝化区段于该第一导电垫及该第二导电垫之间。
由于本公开的半导体装置的设计，该半导体装置的等效串联电阻及等效串联电感将会降低；因此，该半导体装置的效能将会提升。
上文已相当广泛地概述本公开的技术特征及优点，从而使下文的本公开详细描述得以获得更好了解。构成本公开的保护范围标的的其它技术特征及优点将描述于下文。本公开所属技术领域中技术人员应了解，可相当容易地利用下文公开的概念与特定实施例可作为修改或设计其它结构或工艺而实现与本公开相同的目的。本公开所属技术领域中技术人员亦应了解，这类等效建构无法脱离相关申请文件所界定的本公开的构思和范围。
附图说明
参阅实施方式与相关申请文件合并考量附图时，可得以更全面了解本公开的公开内容，附图中相同的元件符号是指相同的元件。
图1为示意图，以剖面图例示本公开于一实施例中的半导体装置。
图2为示意图，以剖面图例示本公开于另一实施例中的半导体装置。
图3为示意图，以流程图例示本公开于一实施例中的半导体装置的制造方法。
图4至图22为示意图，以剖面图例示本公开于一实施例中半导体装置的制造方法的流程。
附图标记说明：
10：制造方法
101：基底
103：第一表面
105：第二表面
107：沟渠
113：第一导电体
115：第二导电体
201：掺杂区域
203：第一掺杂区域
205：第二掺杂区域
301：衬垫层
303：衬垫
401：第一绝缘层
403：第二绝缘层
405：第一绝缘区段
407：嵌入部
409：延伸部
411：第二绝缘区段
501：第一导电层
503：第二导电层
505：第三导电层
507：第一导电垫
509：第二导电垫
511：第一底部导电层
513：第一中间导电层
515：第一顶部导电层
517：第二底部导电层
519：第二中间导电层
521：第二顶部导电层
601：钝化层
603：第一钝化区段
605：第二钝化区段
701：第一遮罩层
703：第二遮罩层
705：第三遮罩层
707：第四遮罩层
D1：水平距离
D2：宽度
D3：水平距离
R1：电阻率
R2：电阻率
R3：电阻率
R4：电阻率
R5：电阻率
具体实施方式
本公开的以下说明伴随并入且组成说明书的一部分的附图，说明本公开的实施例，然而本公开并不受限于该实施例。此外，以下的实施例可适当整合以下实施例以完成另一实施例。
“一实施例”、“实施例”、“例示实施例”、“其他实施例”、“另一实施例”等是指本公开所描述的实施例可包含特定特征、结构或是特性，然而并非每一实施例必须包含该特定特征、结构或是特性。再者，重复使用“在实施例中”一语并非必须指相同实施例，然而可为相同实施例。
为了使得本公开可被完全理解，以下说明提供详细的步骤与结构。显然，本公开的实施不会限制本领域中的技术人士已知的特定细节。此外，已知的结构与步骤不再详述，以免不必要地限制本公开。本公开的优选实施例详述如下。然而，除了详细说明之外，本公开亦可广泛实施于其他实施例中。本公开的范围不限于详细说明的内容，而是由相关申请文件定义。
在本公开中，半导体装置通常是指可以通过利用半导体特性来起作用的装置。如电光装置、发光显示装置、电容器组件、半导体电路和电子装置都将包括在半导体装置的类别中。
在本公开的说明书的描述中，上方对应于Z轴的箭头方向，下方则对应Z轴的箭头的相反方向。
图1为示意图，以剖面图例示本公开于一实施例中的半导体装置。
参照图1，在所示的实施例中，一种半导体装置包括一第一导电体113、一第二导电体115、一第一掺杂区域203、一第二掺杂区域205、多个衬垫303、一第一绝缘区段405、多个第二绝缘区段411、一第一导电垫507、一第二导电垫509、一第一钝化区段603及多个第二钝化区段605。
参照图1，在所示的实施例中，该第一导电体113和该第二导电体115分开设置。该第一导电体113包括一顶面、一侧表面及一底面。该第二导电体115包括一顶面、一侧表面及一底面。该第一导电体113的顶面和该第一导电体113的侧表面相连接并互相垂直，但并不以此为限。该第一导电体113的顶面和该第一导电体113的底面互相平行，但并不以此为限。该第一导电体113的底面和该第一导电体113的侧表面相连接并互相垂直，但并不以此为限。
参照图1，在所示的实施例中，该第二导电体115的顶面和该第二导电体115的侧表面相连接并互相垂直，但并不以此为限。该第二导电体115的顶面和该第二导电体115的底面互相平行，但并不以此为限。该第二导电体115的底面和该第二导电体115的侧表面相连接并互相垂直，但并不以此为限。该第一导电体113的侧表面面向该第二导电体115的侧表面。更具体地，该第一导电体113的侧表面与该第二导电体115的侧表面间的水平距离D1介于约0.02纳米至约0.2纳米之间。替代地，在所示的另一实施例中，该第一导电体113的侧表面与该第二导电体115的侧表面间的水平距离D1介于200纳米至约2000纳米之间。
参照图1，在所示的实施例中，该第一导电体113和该第二导电体115是由硅(包含单晶硅single crystalline silicon或多晶硅polycrystalline silicon)、经掺杂的硅(doped silicon)、锗(germanium)、经掺杂的锗(doped germanium)、硅锗(silicongermanium)、硅碳(silicon carbon)、经掺杂的硅碳(doped silicon carbon)、硅锗碳(silicon germanium carbon)、经掺杂的硅锗碳(doped silicon germanium carbon)、镓(gallium)、经掺杂的镓(doped gallium)、砷化镓(gallium arsenic)、砷化铟(indiumarsenic)、磷化铟(indium phosphorus)、其他IV-IV族、III-V族或II-VI族半导体材料等所形成。在所示的实施例中，该第一导电体113和该第二导电体115皆是由单晶硅所形成。该第一导电体113和该第二导电体115优选地是由同一材料所形成，但并不以此为限。该第一导电体113具有电阻率R1，该第二导电体115具有电阻率R2。该第一导电体113的电阻率R1该第二导电体115的电阻率R2相同，但并不以此为限。更具体地，该第一导电体113的电阻率R1和该第二导电体115的电阻率R2小于1.0E-3Ω·cm。
参照图1，在所示的实施例中，该第一掺杂区域203设置于该第一导电体113中。更具体地，该第一掺杂区域203设置于该第一导电体113的顶面及该第一导电体113的侧表面。该第一掺杂区域203的电阻率R3小于该第一导电体113的电阻率R1。更具体地，该第一掺杂区域203是以一掺质掺杂，该掺质为磷、砷或锑。该第一掺杂区域203的掺质浓度(dopantconcentration)约为1.0E20 ions/cm^3。该第一掺杂区域203的电阻率R3小于0.9E-3Ω·cm。该第一掺杂区域203能降低该第一导电体113中沿着该第一导电体113的顶面及侧表面的电阻率。
参照图1，在所示的实施例中，该第二掺杂区域205设置于该第二导电体115中。更具体地，该第二掺杂区域205设置于该第二导电体115的顶面及该第二导电体115的侧表面。该第二掺杂区域205的电阻率R4小于该第二导电体115的电阻率R2。更具体地，该第二掺杂区域205是以一掺质掺杂，该掺质为磷、砷或锑。该第二掺杂区域205的掺质浓度约为1.0E20ions/cm^3。该第二掺杂区域205的电阻率R4小于0.9E-3Ω·cm。该第二掺杂区域205和该第一掺杂区域203以相同的掺质掺杂，但并不以此为限。该第二掺杂区域205的电阻率R4和该第一掺杂区域203的电阻率R3相同，但并不以此为限。该第二掺杂区域205能降低该第二导电体115中沿着该第二导电体115的顶面及侧表面的电阻率。该第一掺杂区域203和该第二掺杂区域205的低电阻率将能分别补偿该第一导电体113和该第二导电体115在施加交流电(AC power)于该半导体装置时因集肤效应(skin effect)所诱发的导电区域缩减(reduction)。因此，该第一掺杂区域203和该第二掺杂区域205将降低该半导体装置的等效串联电阻(equivalent series resistance)，并借此提升该半导体装置的效能。
参照图1，在所示的实施例中，所述多个衬垫303分别对应地贴设于该第一导电体113的侧表面和该第二导电体115的侧表面。换言之，所述多个衬垫303分别对应地和位于该第一导电体113侧表面的该第一掺杂区域203以及位于该第二导电体115侧表面的第二掺杂区域205相邻且连接。所述多个衬垫303的厚度介于约1.0微米至约10微米。替代地，在所示的另一实施例中，所述多个衬垫303的厚度介于约10纳米至约100纳米。所述多个衬垫303是由钛、氮化钛、钛钨合金、钽、氮化钽、或其组合所形成。所述多个衬垫303具有一电阻率R5小于该第一导电体113的电阻率R1和该第二导电体115的电阻率R2。所述多个衬垫303的电阻率R5等于或小于该第一掺杂区域203的电阻率R3或该第二掺杂区域205的电阻率R4。所述多个衬垫303将能降低该半导体装置的等效串联电阻，并提升该半导体装置的效能。此外，所述多个衬垫303将使得该第一导电体113和该第二导电体115间的空间减小；因此，该半导体装置的电容(capacitance)将得以提高，而该半导体装置的效能将得以提升。
参照图1，在所示的实施例中，该第一绝缘区段405设置于该第一导电体113和该第二导电体115之间。该第一绝缘区段405包括一嵌入部407和一延伸部409。该嵌入部407设置于该第一导电体113和该第二导电体115之间。更具体地，该嵌入部407设置于该第一导电体113侧表面及该第二导电体115侧表面之间。该嵌入部407的两侧直接和所述多个衬垫303相连。该嵌入部407覆盖所述多个衬垫303。
参照图1，在所示的实施例中，该延伸部409设置于该嵌入部407、该第一导电体113和该第二导电体115上。该延伸部409的宽度D2大于该第一导电体113的侧表面与该第二导电体115的侧表面间的水平距离D1。更具体地，该延伸部409的两侧分别设置于该第一导电体113的顶面及该第二导电体115的顶面上。该嵌入部407和该延伸部409是由氮化硅(silicon nitride)、氧化硅(silicon oxide)、氮氧化硅(silicon oxynitride)、可流动氧化物(flowable oxide)、东燃硅氮烷(tonen silazen)、未掺杂硅酸盐玻璃(undopedsilica glass)、硼硅酸盐玻璃(borosilica glass)、磷硅酸盐玻璃(phosphosilicaglass)、硼磷硅酸盐玻璃(borophosphosilica glass)、等离子体加强型四乙基正硅酸盐(plasma-enhanced tetra-ethyl orthosilicate)、氟硅酸盐玻璃(fluoride silicateglass)、碳掺杂氧化硅(carbon-doped silicon oxide)、干凝胶(xerogel)、气凝胶(aerogel)、无定形氟化碳(amorphous fluorinated carbon)、有机硅酸盐玻璃(organosilicate glass)、聚对二甲苯(parylene)、双苯并环丁烯(bis-benzocyclobutenes)、聚酰亚胺(polyimide)、孔洞聚合材料(porous polymeric material)或其组合所形成，但并不以此为限。优选地，该嵌入部407和该延伸部409是由相同材料所形成，但并不以此为限。
参照图1，在所示的实施例中，所述多个第二绝缘区段411分别对应地设置于该第一导电体113的顶面和该第二导电体115的顶面上。所述多个第二绝缘区段411和该延伸部409等高。所述多个第二绝缘区段411和该延伸部409彼此间隔开。所述多个第二绝缘区段411和该该延伸部409由相同材料所形成。
参照图1，在所示的实施例中，该第一导电垫507设置于该第一导电体113的顶面。该第一导电垫507包括一第一底部导电层511、一第一中间导电层513以及一第一顶部导电层515。该第一底部导电层511设置于该第一导电体113的顶面。该第一底部导电层511的两侧分别对应地覆盖位于该第一导电体113顶面上的第二绝缘区段411的一部分及位于该第一导电体113顶面上的延伸部409的一部分。该第一底部导电层511和该第一掺杂区域203及该第一导电体113电连接。
参照图1，在所示的实施例中，该第一中间导电层513设置于该第一底部导电层511上。该第一中间导电层513和该第一底部导电层511电连接。该第一顶部导电层515设置于该第一中间导电层513上。该第一顶部导电层515和该第一中间导电层513电连接。该第一底部导电层511、该第一中间导电层513及该第一顶部导电层515是由铝、银、白金、铅、镍、金、铜、其合金、或其类似物所形成。在所示的实施例中，该第一底部导电层511是由铝所形成，该第一中间导电层513是由镍所形成，该第一顶部导电层515是由金所形成。由铝所形成的第一底部导电层511能降低该第一导电垫507的总电阻(total resistivity)。由镍所形成的第一中间导电层513能提高第一导电垫507和焊锡(solder)间的键结强度(bondingstrength)。由金所形成的第一顶部导电层515能避免该第一中间导电层513被氧化。
参照图1，在所示的实施例中，该第二导电垫509设置于该第二导电体115的顶面。该第二导电垫509包括一第二底部导电层517、一第二中间导电层519以及一第二顶部导电层521。该第二底部导电层517设置于该第二导电体115的顶面。该第二底部导电层517的两侧分别对应地覆盖位于该第二导电体115顶面上的第二绝缘区段411的一部分及位于该第二导电体115顶面上的延伸部409的一部分。该第二底部导电层517和该第二掺杂区域205及该第二导电体115电连接。
参照图1，在所示的实施例中，该第二中间导电层519设置于该第二底部导电层517上。该第二中间导电层519和该第二底部导电层517电连接。该第二顶部导电层521设置于该第二中间导电层519上。该第二顶部导电层521和该第二中间导电层519电连接。该第二底部导电层517、该第二中间导电层519及该第二顶部导电层521是由铝、银、白金、铅、镍、金、铜、其合金、或其类似物所形成。在所示的实施例中，该第二底部导电层517是由铝所形成，该第二中间导电层519是由镍所形成，该第二顶部导电层521是由金所形成。由铝所形成的第二底部导电层517能降低该第二导电垫509的总电阻。由镍所形成的第二中间导电层519能提高第二导电垫509和焊锡间的键结强度。由金所形成的第二顶部导电层521能避免该第二中间导电层519被氧化。该第一导电垫507和该第二导电垫509间的水平距离D3大于该第一导电体113的侧表面与该第二导电体115的侧表面间的水平距离D1；该第一导电垫507和该第二导电垫509间的水平距离D3小于该延伸部409的宽度D2。因该第一底部导电层511覆盖位于该第一导电体113顶面上的延伸部409的部分，以及该第二底部导电层517覆盖位于该第二导电体115顶面上的延伸部409的部分，将使得该第一导电垫507和该第二导电垫509间的水平距离D3减小，故得以降低其间电流的通过。因此，该半导体装置的等效串联电阻及等效串联电感(equivalent series inductance)将会降低。
参照图1，在所示的实施例中，该第一钝化区段603设置于该第一绝缘区段405上。该第一钝化区段603设置于该第一导电垫507和该第二导电垫509之间。该第一钝化区段603的两侧分别对应覆盖该第一顶部导电层515顶面的一部分以及该第二顶部导电层521顶面的一部分。该第一钝化区段603是由苯环丁烯、聚酰亚胺、氧化硅、氮化硅、磷硅酸盐玻璃、或其类似物所形成。
参照图1，在所示的实施例中，所述多个第二钝化区段605分别对应地设置于所述多个第二绝缘区段411上。所述多个第二钝化区段605和该第一钝化区段603彼此间隔开。所述多个第二钝化区段605分别对应覆盖该第一顶部导电层515顶面的另一部分以及该第二顶部导电层521顶面的另一部分。该第一顶部导电层515的顶面及该第二顶部导电层521的顶面分别经由所述多个第二钝化区段605和该第一钝化区段603间的空间而曝露。所述多个第二钝化区段605和该第一钝化区段603优选地是由同一材料所形成，但并不以此为限。该第一钝化区段603和所述多个第二钝化区段605能保护该第一导电体113、该第二导电体115、该第一导电垫507和该第二导电垫509不被外界的湿气影响。
图2为示意图，以剖面图例示本公开于另一实施例中的半导体装置。
参照图2，在所示的另一实施例中，该第一导电垫507包含一第一底部导电层511和一第一中间导电层513。该第一底部导电层511设置于该第一导电体113的顶面。该第一底部导电层511的两侧分别对应地覆盖位于该第一导电体113顶面上的第二绝缘区段411的一部分及位于该第一导电体113顶面上的延伸部409的一部分。该第一底部导电层511和该第一掺杂区域203及该第一导电体113电连接。该第一中间导电层513设置于该第一底部导电层511上。
参照图2，在所示的另一实施例中，该第二导电垫509包括一第二底部导电层517和一第二中间导电层519。该第二底部导电层517设置于该第二导电体115的顶面。该第二底部导电层517的两侧分别对应地覆盖位于该第二导电体115顶面上的第二绝缘区段411的一部分及位于该第二导电体115上的延伸部409的一部分。该第二底部导电层517和该第二掺杂区域205及该第二导电体115电连接。该第二中间导电层519设置于该第二底部导电层517上。
图3为示意图，以流程图例示本公开于一实施例中的半导体装置的制造方法10。图4至图22为示意图，以剖面图例示本公开于一实施例中半导体装置的制造方法的流程。
参照图3和图4，于步骤S11，在所示的实施例中，提供一基底101。该基底包括一第一表面103和一第二表面105。在所示的实施例中，该基底101的第一表面103面朝上且平行于该第二表面105。该基底的第二表面105面朝下且相对于该基底101的第一表面103。
参照图3、图5和图6，于步骤S13，在所示的实施例中，形成一沟渠107于该基底101中。该沟渠107是内凹形成于该基底101，并具有一开口位于该基底101的第一表面103。参照图5，执行一微影工艺以形成一第一遮罩层701于该基底101的第一表面103，并借此定义将形成该沟渠107的位置于该基底101的第一表面103。参照图6，于微影工艺后执行一蚀刻工艺，以形成该沟渠107于该基底101中，该蚀刻工艺为非等向性干式蚀刻。
参照图3和图7，于步骤S15，在所示的实施例中，形成一掺杂区域201于该基底101中。自该基底101的第一表面103上方执行一植入工艺以形成该掺杂区域201于该基底101中。该掺杂区域201形成于该基底101的第一表面103、该沟渠107的侧表面及该沟渠107的底部。该掺杂区域201的电阻率小于或等于该基底101的电阻率。
参照图3、图8和图9，于步骤S17，在所示的实施例中，形成多个衬垫303于该沟渠107中。参照图8，一衬垫层301沉积在该基底101的第一表面103、该沟渠107的侧表面及该沟渠107的底部。该衬垫层301是由钛、氮化钛、钛钨合金、钽、氮化钽、或其组合所形成。参照图9，执行一蚀刻工艺以形成所述多个衬垫303贴设于该沟渠107的侧表面，该蚀刻工艺为非等向性干式蚀刻。所述多个衬垫303和该掺杂区域201电连接。
参照图3、图10至图13，于步骤S19，在所示的实施例中，一第一绝缘区段405形成于该沟渠107中及该基底101上，多个第二绝缘区段411形成于该基底101的第一表面103上。参照图10，执行一沉积工艺以沉积一第一绝缘层401于该沟渠107中，并覆盖该基底101的第一表面103。执行一平坦化工艺，例如化学机械研磨，以将多余的填料移除，并为后续工艺提供平坦的表面。填满该沟渠107的该第一绝缘层401可视为该第一绝缘区段405的嵌入部407。
该第一绝缘层401是由氮化硅、氧化硅、氮氧化硅、可流动氧化物、东燃硅氮烷、未掺杂硅酸盐玻璃、硼硅酸盐玻璃、磷硅酸盐玻璃、硼磷硅酸盐玻璃、等离子体加强型四乙基正硅酸盐、氟硅酸盐玻璃、碳掺杂氧化硅、干凝胶、气凝胶、无定形氟化碳、有机硅酸盐玻璃、聚对二甲苯、双苯并环丁烯、聚酰亚胺、孔洞聚合材料或其组合所形成，但并不以此为限。
参照图11，执行一沉积工艺以沉积一第二绝缘层403于该基底101的第一表面103上方。该第二绝缘层403优选地可和该第一绝缘层401由相同材料所形成，但并不以此为限。参照图12，执行一微影工艺以形成一第二遮罩层703于该第二绝缘层403上，并借此定义将形成该第一绝缘区段405的延伸部409的位置于该第二绝缘层403。参照图13，于该微影工艺后，执行一蚀刻工艺将该第二绝缘层403蚀刻为该第一绝缘区段405的延伸部409以及所述多个第二绝缘区段411，该蚀刻工艺为非等向性干式蚀刻。
参照图3及图14至图18，于步骤S21，在所示的实施例中，一第一导电垫507和一第二导电垫509形成于该基底101的上方。该第一导电垫507包括一第一底部导电层511、一第一中间导电层513以及一第一顶部导电层515。该第二导电垫509包括一第二底部导电层517、一第二中间导电层519以及一第二顶部导电层521。
参照图14至图16，通过一系列的沉积工艺沉积一第一导电层501、一第二导电层503和一第三导电层505于该基底101的上方。该第一导电层501形成于该基底101的第一表面103并覆盖该延伸部409及所述多个第二绝缘区段411。执行一平坦化工艺，例如化学机械研磨，以将多余的填料移除，并为后续工艺提供平坦的表面。该第二导电层503形成于该第一导电层501上。该第三导电层505形成于该第二导电层503上。该第一导电层501、该第二导电层503及该第三导电层505是由铝、银、白金、铅、镍、金、铜、其合金、或其类似物所形成。
参照图17，执行一微影工艺以形成一第三遮罩层705于该第三导电层505上，并借此定义将形成该第一导电垫507及该第二导电垫509的位置于该第三导电层505。参照图18，于该微影工艺后，执行一蚀刻工艺将该第一导电层501、该第二导电层503及该第三导电层505蚀刻为该第一导电垫507以及该第二导电垫509，该蚀刻工艺为非等向性干式蚀刻。
参照图3及图19至图21，于步骤S23，形成一第一钝化区段603及多个第二钝化区段605于该基底101的上方。参照图19，执行一沉积工艺以沉积一钝化层601于该第一导电垫507、该第二导电垫509、该第一绝缘区段405与所述多个第二绝缘区段411上。该钝化层601是由苯环丁烯、聚酰亚胺、氧化硅、氮化硅、磷硅酸盐玻璃、或其类似物所形成。参照图20，执行一微影工艺以形成一第四遮罩层707于该钝化层601上，并借此定义将形成该第一钝化区段603与所述多个第二钝化区段605的位置于该钝化层601。参照图21，于该微影工艺后，执行一蚀刻工艺将该钝化层601蚀刻为该第一钝化区段603以及所述多个第二钝化区段605，该蚀刻工艺为非等向性干式蚀刻。
参照图3和图22，于步骤S25，自该第二表面105移除该基底101的部分直至曝露所述多个衬垫303和该第一绝缘区段405的嵌入部407。执行一移除工艺于该基底101的第二表面105，以曝露所述多个衬垫303和该第一绝缘区段405的嵌入部407，并借此将该基底101转变为一第一导电体113和一第二导电体115，该移除工艺为化学机械研磨。
本公开的一方面提供一种半导体装置，该半导体装置包括一第一导电体、一第二导电体和该第一导电体分离设置、多个衬垫分别对应地贴设于该第一导电体的侧表面及该第二导电体的侧表面及一第一绝缘区段设置于该第一导电体和该第二导电体之间。
本公开的另一方面提供一种半导体装置的制造方法，其包括提供一具有一第一表面及一第二表面的基底，该第二表面和该第一表面相对、内凹地形成一沟渠于该基底的第一表面、形成多个衬垫于该沟渠的侧表面、形成一第一绝缘区段填满该沟渠以及自该第二表面移除部分的基底以曝露该第一绝缘区段和所述多个衬垫。
由于本公开的半导体装置的设计，该半导体装置的等效串联电阻及等效串联电感将会降低；因此，该半导体装置的效能将会提升。
虽然已详述本公开及其优点，然而应理解可进行各种变化、取代与替代而不脱离相关申请文件的保护范围所定义的本公开的构思与范围。例如，可用不同的方法实施上述的许多工艺，并且以其他工艺或其组合替代上述的许多工艺。
再者，本公开的范围并不受限于说明书中所述的工艺、机械、制造、物质组成物、手段、方法与步骤的特定实施例。本领域的技术人士可自本公开的公开内容理解可根据本公开而使用与本文所述的对应实施例具有相同功能或是达到实质上相同结果的现存或是未来发展的工艺、机械、制造、物质组成物、手段、方法、或步骤。据此，这些工艺、机械、制造、物质组成物、手段、方法、或步骤包含于本公开的权利要求内。

Claims (18)

1.一种半导体装置，包括：
一第一导电体；
一第二导电体和该第一导电体分离设置；
多个衬垫分别对应地贴设于该第一导电体的侧表面及该第二导电体的侧表面；
一第一绝缘区段设置于该第一导电体和该第二导电体之间；以及
一第一掺杂区域设置于该第一导电体的顶面及该第一导电体的侧表面。
2.如权利要求1所述的半导体装置，其中该第一绝缘区段包括一嵌入部及一延伸部，该嵌入部设置于所述多个衬垫之间，而该延伸部设置于该嵌入部上。
3.如权利要求2所述的半导体装置，其中该延伸部的两侧分别对应地设置于该第一导电体的顶面的一部分及该第二导电体的顶面的一部分上。
4.如权利要求2所述的半导体装置，其中该延伸部的宽度大于或等于该第一导电体和该第二导电体间的水平距离。
5.如权利要求4所述的半导体装置，还包括一第一导电垫和一第二导电垫，其中该第一导电垫设置于该第一导电体的顶面，该第二导电垫设置于该第二导电体的顶面。
6.如权利要求5所述的半导体装置，其中该第一导电垫包括一第一底部导电层及一第一中间导电层，该第一底部导电层设置于该第一导电体的顶面，该第一中间导电层设置于该第一底部导电层上。
7.如权利要求5所述的半导体装置，其中该第一导电垫包括一第一底部导电层、一第一中间导电层及一第一顶部导电层，该第一底部导电层设置于该第一导电体的顶面，该第一中间导电层设置于该第一底部导电层上，该第一顶部导电层设置于该第一中间导电层上。
8.如权利要求7所述的半导体装置，其中该第一底部导电层的一侧覆盖该延伸部的顶面的一部分。
9.如权利要求5所述的半导体装置，其中该第一导电垫是由铝、银、白金、铅、镍、金、铜、或其合金所形成。
10.如权利要求5所述的半导体装置，其中该第一导电垫和该第二导电垫间的水平距离小于该延伸部的宽度。
11.如权利要求5所述的半导体装置，还包括一第一钝化区段设置于该第一导电垫及该第二导电垫之间。
12.一种半导体装置的制造方法，包括：
提供一基底，该基底具有一第一表面及一第二表面，该第二表面和该第一表面相对；
内凹地形成一沟渠于该基底的第一表面；
形成多个衬垫于该沟渠的侧表面；
形成一第一绝缘区段填满该沟渠；
自该第二表面移除部分的基底以曝露该第一绝缘区段和所述多个衬垫；以及
形成一掺杂区域于该基底中，其中该掺杂区域形成于该基底的第一表面、该沟渠的侧表面及该沟渠的底部。
13.如权利要求12所述的半导体装置的制造方法，其中所述多个衬垫是由钛、氮化钛、钛钨合金、钽、氮化钽、或其组合所形成。
14.如权利要求13所述的半导体装置的制造方法，其中该第一绝缘区段包括一嵌入部及一延伸部，该嵌入部形成于该沟渠中并覆盖所述多个衬垫，该延伸部形成于该嵌入部上。
15.如权利要求14所述的半导体装置的制造方法，其中该延伸部更覆盖该基底的第一表面的一部分。
16.如权利要求15所述的半导体装置的制造方法，还包括形成一第一导电垫和一第二导电垫于该基底的上方。
17.如权利要求16所述的半导体装置的制造方法，其中该第一导电垫包括一第一底部导电层、一第一中间导电层及一第一顶部导电层，该第一底部导电层形成于该基底上，该第一中间导电层形成于该第一底部导电层上，该第一顶部导电层形成于该第一中间导电层上。
18.如权利要求17所述的半导体装置的制造方法，还包括形成一第一钝化区段于该第一导电垫及该第二导电垫之间。
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