CN112509924B - 一种E/D集成的GaN HEMT器件制备方法 - Google Patents
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Abstract
本发明公开了一种E/D集成的GaN HEMT器件制备方法，步骤：通过离子注入进行器件隔离；去除E模器件栅极区域的原位SiN层，打开p型GaN的栅电极窗口，通过退火激活工艺激活E模器件栅角所在的p型GaN区域；去除D模器件栅极区域的原位SiN层，再进行二次刻蚀去除D模器件栅极区域的p型GaN层；在器件表面生长一层SiN栅氧介质层；制作E模器件栅电极和D模器件栅电极；打开E模器件和D模器件源漏电极区域；制作E模器件和D模器件漏源电极。本发明采用选区激活的方法，使E/D模器件工艺完全兼容，避免了器件沟道区域的刻蚀损伤，有利于提高GaN E/D集成电路的可靠性和成品率。
Description
技术领域
本发明属于半导体器件领域，特别涉及了一种GaN HEMT器件制备方法。
背景技术
传统电子设备中功率开关器件主要采用垂直扩散金属氧化物半导体(VDMOS)和绝缘栅双极型晶体管(IGNT)等Si功率器件。受材料特性自身制约，Si功率器件性能已无法获得进一步提升，也无法完全满足绿色能源新技术发展需要。氮化镓GaN(gallium nitride)功率器件因其出色的导通与开关特性，能够实现系统高频化与小型化，有效提升系统功率密度。但是，增强型GaN功率器件由于其栅极可靠性问题，使其在电源管理系统中无法直接替换传统硅基功率MOSFET器件。
近年来，随着GaN微波功率器件向实用化发展，GaN在高速数字和混和信号电路中的应用吸引了越来越广泛的关注，目的是充分发挥其高电子漂移速度和高击穿电压的优势，在保持高速性能的同时获得理想的电压摆幅。特别是近两年，GaN高频器件和E/D集成研究逐渐成为了国际研究热点，并誉为下一代GaN电子器件与集成电路技术。GaN材料特有的极化特性使得常规AlGaN/GaN HEMT为本征n沟道耗尽型晶体管，因此如何实现与GaN耗尽型器件工艺兼容的增强型器件并稳定可控成为发展GaN基集成电路亟待解决的关键问题。
GaN基E-mode器件的性能及可靠性的提高，其在电路中的研究应用也越来越广泛。GaN基E/D-mode电路即GaN基E-mode与D-mode参考CMOS电路组合，采用直接耦合场效应管逻辑(Direct Coupled Field-Effect Transistors Logical:DCFL)实现GaN基E/D-mode数字电路。其中E-mode器件的性能包括大阈值电压，高跨导，低导通电阻，低膝点电压和大输入电压摆幅在整个数字电路中起到至关重要的作用。
目前，基于GaN基异质结构实现增强型器件的途径主要有两类，一类是从材料结构出发，通过新型异质结构的设计实现本征增强型器件，如InGaN、p型(Al)GaN帽层结构，薄势垒结构，MOS结构等；第二类是从工艺技术出发，如挖槽工艺，氟离子注入、氧等离子体处理技术等，基于常规AlGaN/GaN异质结构通过后工艺技术将栅极区域二维电子气耗尽，以实现增强型器件；另外，还可将两类方法相结合，如新材料结构(本征耗尽型)结合栅挖槽技术或氧等离子体处理技术，进一步提高增强型器件性能。新型本征增强型材料结构设计，可以较好的控制增强型器件的阈值电压，提高器件的一致性，目前成为制备单一增强型器件的主流方法，但由于其材料结构本身限制，不适用于E/D集成，新型本征耗尽型材料结构虽可通过工艺技术实现E/D兼容并获得较好的一致性，却仍然面临由新材料引入带来的从材料生长到器件工艺一系列新的技术问题，与传统工艺兼容性较差，需要重新开发。另一方面，基于传统异质结构采用栅挖槽工艺实现增强型器件需将原势垒层厚度(约20-30nm)减薄到5nm以下，AlGaN势垒层深挖槽工艺的可控性和重复性难以保证；而氟离子注入技术也存在工艺一致性和可控性不高以及高温下氟离子可动性导致的器件可靠性问题，难以满足大规模应用需求。传统AlGaN/GaN异质结构中，通常引入2-3nmGaN帽层以提高器件的击穿电压，抑制电流崩塌效应，在制作栅金属时根据需要将该帽层进行选择性刻蚀，GaN帽层的生长与刻蚀工艺均为传统工艺。
发明内容
为了解决上述背景技术提到的技术问题，本发明提出了一种E/D集成的GaN HEMT器件制备方法。
为了实现上述技术目的，本发明的技术方案为：
一种E/D集成的GaN HEMT器件制备方法，包括以下步骤：
(1)在衬底上依次形成GaN缓冲层、AlGaN势垒层、AlN或本征氮化镓插入层、p型GaN层和原位SiN层，形成常规的AlGaN/GaN异质结构，异质界面形成二维电子气；
(2)通过离子注入进行器件隔离，构成用于实现E/D集成的AlGaN/GaN异质结构；
(3)去除E模器件栅极区域的原位SiN层，打开p型GaN的栅电极窗口；通过退火激活工艺激活E模器件栅角所在的p型GaN区域，形成关断沟道；
(4)去除D模器件栅极区域的原位SiN层，再进行二次刻蚀去除D模器件栅极区域的p型GaN层；
(5)在器件表面生长一层SiN栅氧介质层；
(6)在E模器件栅极区域的SiN栅氧介质层和D模器件栅极区域的SiN栅氧介质层上分别制作E模器件栅电极和D模器件栅电极；
(7)分别去除E模器件和D模器件源漏电极区域的SiN栅氧介质层、p型GaN层和部分AlGaN势垒层，打开E模器件和D模器件源漏电极区域；
(8)分别在打开的E模器件和D模器件源漏电极区域沉积欧姆金属，制作E模器件和D模器件漏源电极，通过低温工艺实现欧姆接触。
进一步地，在步骤(1)中，所述AlGaN势垒层的n型掺杂浓度≥1×1017cm-3。
进一步地，在步骤(1)中，所述p型GaN层的p型掺杂浓度≥1×1019cm-3。
进一步地，制备完成后，D模器件栅极区域AlGaN势垒层的厚度为1-10nm。
进一步地，E模器件和D模器件的栅结构为肖特基栅或绝缘栅。
进一步地，所述绝缘栅的介质为SiN、SiO2、Al2O3、AlN或HfO2。
进一步地，所述衬底为SiC、蓝宝石、Si或GaN。
采用上述技术方案带来的有益效果：
本发明通过p型氮化镓选区激活，最大限度地降低了工艺过程对器件的沟道损伤，通过增加一层插入层降低了激活过程中Mg杂质扩散对沟道的影响，通过一次钝化实现了D模器件和E模器件的MIS结构，降低栅极漏电流，提升了器件的可靠性。
附图说明
图1是E/D集成的GaN HEMT器件制备方法步骤1的示意图；
图2是E/D集成的GaN HEMT器件制备方法步骤2的示意图；
图3是E/D集成的GaN HEMT器件制备方法步骤3的示意图；
图4是E/D集成的GaN HEMT器件制备方法步骤4的示意图；
图5是E/D集成的GaN HEMT器件制备方法步骤5的示意图；
图6是E/D集成的GaN HEMT器件制备方法步骤6的示意图；
图7是E/D集成的GaN HEMT器件制备方法步骤7的示意图；
图8是E/D集成的GaN HEMT器件制备方法步骤8的示意图；
标号说明：1、GaN缓冲层；2、AlGaN势垒层；3、AlN或本征氮化镓插入层；4、p型GaN层；5、原位SiN层；6、SiN栅氧介质层；7、欧姆金属；8、E/D模器件的栅电极；9、激活的p型GaN层。
具体实施方式
以下将结合附图，对本发明的技术方案进行详细说明。
本发明设计了一种E/D集成的GaN HEMT器件制备方法，步骤如下：
步骤1：在衬底上依次形成GaN缓冲层、AlGaN势垒层、AlN或本征氮化镓插入层、p型GaN层和原位SiN层，形成常规的AlGaN/GaN异质结构，异质界面形成二维电子气，如图1所示；
步骤2：通过离子注入进行器件隔离，构成用于实现E/D集成的AlGaN/GaN异质结构，如图2所示；
步骤3：去除E模器件栅极区域的原位SiN层，打开p型GaN的栅电极窗口；通过退火激活工艺激活E模器件栅角所在的p型GaN区域，形成关断沟道，如图3所示；
步骤4：去除D模器件栅极区域的原位SiN层，再进行二次刻蚀去除D模器件栅极区域的p型GaN层，如图4所示；
步骤5：在器件表面生长一层SiN栅氧介质层，如图5所示；
步骤6：在E模器件栅极区域的SiN栅氧介质层和D模器件栅极区域的SiN栅氧介质层上分别制作E模器件栅电极和D模器件栅电极，如图6所示；
步骤7：分别去除E模器件和D模器件源漏电极区域的SiN栅氧介质层、p型GaN层和部分AlGaN势垒层，打开E模器件和D模器件源漏电极区域，如图7所示；
步骤8：分别在打开的E模器件和D模器件源漏电极区域沉积欧姆金属，制作E模器件和D模器件漏源电极，通过低温工艺实现欧姆接触，如图8所示。
在本实施例中，优选地，在步骤(1)中，所述AlGaN势垒层的n型掺杂浓度≥1×1017cm-3；所述p型GaN层的p型掺杂浓度≥1×1019cm-3。
在本实施例中，优选地，制备完成后，D模器件栅极区域AlGaN势垒层的厚度为1-10nm。
在本实施例中，优选地，E模器件和D模器件的栅结构为肖特基栅或绝缘栅；进一步地，所述绝缘栅的介质为SiN、SiO2、Al2O3、AlN或HfO2。
在本实施例中，优选地，所述衬底为SiC、蓝宝石、Si或GaN。
实施例仅为说明本发明的技术思想，不能以此限定本发明的保护范围，凡是按照本发明提出的技术思想，在技术方案基础上所做的任何改动，均落入本发明保护范围之内。
Claims (7)
1.一种E/D集成的GaN HEMT器件制备方法，其特征在于，包括以下步骤：
(1)在衬底上依次形成GaN缓冲层、AlGaN势垒层、AlN或本征氮化镓插入层、p型GaN层和原位SiN层，形成常规的AlGaN/GaN异质结构，异质界面形成二维电子气；
(2)通过离子注入进行器件隔离，构成用于实现E/D集成的AlGaN/GaN异质结构；
(3)去除E模器件栅极区域的原位SiN层，打开p型GaN的栅电极窗口；通过退火激活工艺激活E模器件栅角所在的p型GaN区域，形成关断沟道；
(4)去除D模器件栅极区域的原位SiN层，再进行二次刻蚀去除D模器件栅极区域的p型GaN层；
(5)在器件表面生长一层SiN栅氧介质层；
(6)在E模器件栅极区域的SiN栅氧介质层和D模器件栅极区域的SiN栅氧介质层上分别制作E模器件栅电极和D模器件栅电极；
(7)分别去除E模器件和D模器件源漏电极区域的SiN栅氧介质层、p型GaN层和部分AlGaN势垒层，打开E模器件和D模器件源漏电极区域；
(8)分别在打开的E模器件和D模器件源漏电极区域沉积欧姆金属，制作E模器件和D模器件漏源电极，通过低温工艺实现欧姆接触。
2.根据权利要求1所述E/D集成的GaN HEMT器件制备方法，其特征在于，在步骤(1)中，所述AlGaN势垒层的n型掺杂浓度≥1×1017cm-3。
3.根据权利要求1所述E/D集成的GaN HEMT器件制备方法，其特征在于，在步骤(1)中，所述p型GaN层的p型掺杂浓度≥1×1019cm-3。
4.根据权利要求1所述E/D集成的GaN HEMT器件制备方法，其特征在于，制备完成后，D模器件栅极区域AlGaN势垒层的厚度为1-10nm。
5.根据权利要求1所述E/D集成的GaN HEMT器件制备方法，其特征在于，E模器件和D模器件的栅极结构替换为肖特基栅。
6.根据权利要求1所述E/D集成的GaN HEMT器件制备方法，其特征在于，所述栅极介质替换为SiO2、Al2O3、AlN或HfO2。
7.根据权利要求5所述E/D集成的GaN HEMT器件制备方法，其特征在于，所述衬底为SiC、蓝宝石、Si或GaN。
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