CN112449725A - 电容器及其制作方法 - Google Patents

电容器及其制作方法 Download PDF

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Publication number
CN112449725A
CN112449725A CN201980001219.4A CN201980001219A CN112449725A CN 112449725 A CN112449725 A CN 112449725A CN 201980001219 A CN201980001219 A CN 201980001219A CN 112449725 A CN112449725 A CN 112449725A
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China
Prior art keywords
layer
conductive layer
conductive
substrate
trench
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CN201980001219.4A
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English (en)
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CN112449725B (zh
Inventor
陆斌
沈健
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Publication of CN112449725A publication Critical patent/CN112449725A/zh
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0805Capacitors only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92Capacitors having potential barriers
    • H01L29/94Metal-insulator-semiconductors, e.g. MOS
    • H01L29/945Trench capacitors

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本申请实施例提供一种电容器及其制作方法,电容器包括:半导体衬底,包括至少一个衬底沟槽组;至少一个叠层结构,每个叠层结构包括n层导电层和m层电介质层,n层导电层中的第一层导电层设置于半导体衬底上方和衬底沟槽组内,n层导电层中的第i层导电层形成有第i导电层沟槽组,n层导电层中的第i+1层导电层设置于第i层导电层的上方和第i导电层沟槽组内,m、n、i为正整数,且n≥2,1≤i≤n‑1;至少一个第一外接电极,电连接至n层导电层中的一部分导电层;至少一个第二外接电极,电连接至n层导电层中的另一部分导电层,一部分导电层中的每层导电层在叠层结构中相邻的导电层包括有另一部分导电层中的至少一个导电层。

Description

PCT国内申请,说明书已公开。

Claims (49)

  1. PCT国内申请,权利要求书已公开。
CN201980001219.4A 2019-07-03 2019-07-03 电容器及其制作方法 Active CN112449725B (zh)

Applications Claiming Priority (1)

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PCT/CN2019/094619 WO2021000304A1 (zh) 2019-07-03 2019-07-03 电容器及其制作方法

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CN112449725A true CN112449725A (zh) 2021-03-05
CN112449725B CN112449725B (zh) 2023-01-20

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US (1) US11362171B2 (zh)
EP (1) EP3783647B1 (zh)
CN (1) CN112449725B (zh)
WO (1) WO2021000304A1 (zh)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3680934A1 (en) * 2019-01-08 2020-07-15 Murata Manufacturing Co., Ltd. Rc architectures, and methods of fabrication thereof
US11854959B2 (en) * 2021-03-26 2023-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Metal-insulator-metal device with improved performance

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102709311A (zh) * 2011-02-17 2012-10-03 美士美积体产品公司 带有具有压缩应力的保形沉积导电层的深沟槽电容器
CN103208415A (zh) * 2013-03-22 2013-07-17 上海宏力半导体制造有限公司 电容及其形成方法
US20140145299A1 (en) * 2012-11-26 2014-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Deep trench structure for high density capacitor
CN108735719A (zh) * 2017-04-25 2018-11-02 三星电机株式会社 电容器及制造该电容器的方法
CN108962880A (zh) * 2018-07-17 2018-12-07 昆山晔芯电子科技有限公司 一种高密度多层堆叠mim电容器及像素电路与成像装置
CN109103188A (zh) * 2017-06-20 2018-12-28 台湾积体电路制造股份有限公司 用以形成半导体装置的方法
CN109427753A (zh) * 2017-09-01 2019-03-05 台湾积体电路制造股份有限公司 电容结构、包括电容结构的半导体管芯及其形成方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6570477B2 (en) * 2000-05-09 2003-05-27 Innochips Technology Low inductance multilayer chip and method for fabricating same
US9978829B2 (en) * 2012-11-26 2018-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Low impedance high density deep trench capacitor
EP2924730A1 (en) * 2014-03-25 2015-09-30 Ipdia Capacitor structure
CN107204331B (zh) * 2017-07-07 2019-08-23 上海华虹宏力半导体制造有限公司 多层电容器的制造方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102709311A (zh) * 2011-02-17 2012-10-03 美士美积体产品公司 带有具有压缩应力的保形沉积导电层的深沟槽电容器
US20140145299A1 (en) * 2012-11-26 2014-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Deep trench structure for high density capacitor
CN103208415A (zh) * 2013-03-22 2013-07-17 上海宏力半导体制造有限公司 电容及其形成方法
CN108735719A (zh) * 2017-04-25 2018-11-02 三星电机株式会社 电容器及制造该电容器的方法
CN109103188A (zh) * 2017-06-20 2018-12-28 台湾积体电路制造股份有限公司 用以形成半导体装置的方法
CN109427753A (zh) * 2017-09-01 2019-03-05 台湾积体电路制造股份有限公司 电容结构、包括电容结构的半导体管芯及其形成方法
CN108962880A (zh) * 2018-07-17 2018-12-07 昆山晔芯电子科技有限公司 一种高密度多层堆叠mim电容器及像素电路与成像装置

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Publication number Publication date
EP3783647B1 (en) 2022-05-25
CN112449725B (zh) 2023-01-20
WO2021000304A1 (zh) 2021-01-07
US11362171B2 (en) 2022-06-14
EP3783647A1 (en) 2021-02-24
US20210005707A1 (en) 2021-01-07
EP3783647A4 (en) 2021-06-30

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