CN112397455A - 半导体封装件及其制造方法 - Google Patents

半导体封装件及其制造方法 Download PDF

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Publication number
CN112397455A
CN112397455A CN202010371907.4A CN202010371907A CN112397455A CN 112397455 A CN112397455 A CN 112397455A CN 202010371907 A CN202010371907 A CN 202010371907A CN 112397455 A CN112397455 A CN 112397455A
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semiconductor chip
support structure
top surface
semiconductor
package
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CN202010371907.4A
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CN112397455B (zh
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张元基
明福植
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

提供了一种半导体封装件及其制造方法，所述半导体封装件可以包括封装基底、位于封装基底上并在其中具有腔的支撑结构以及在腔中位于封装基底上的至少一个第一半导体芯片。支撑结构可以具有面向腔的第一内侧壁、第一顶表面以及连接第一内侧壁和第一顶表面的第一倾斜表面。第一倾斜表面可以相对于所述至少一个第一半导体芯片的顶表面倾斜。

Description

半导体封装件及其制造方法
本专利申请要求于2019年8月13日在韩国知识产权局提交的第10-2019-0098779号韩国专利申请的优先权，该韩国专利申请的公开内容通过引用全部包含于此。
技术领域
发明构思的实施例涉及一种半导体封装件和一种制造该半导体封装件的方法。
背景技术
集成电路芯片可以以半导体封装件的形式实现，以被适当地应用于电子产品。在典型的半导体封装件中，半导体芯片可以安装在印刷电路板(PCB)上并且可以通过接合引线(也称为接合线或键合引线)或凸块电连接到PCB。为了效率，可以将多个集成电路芯片(或半导体芯片)安装在大面积的板上以同时制造多个半导体封装件，然后，可以执行锯切模制层和板的单片化工艺(即，切单工艺)以使半导体封装件彼此分离。
随着电子工业的发展，已经越来越要求更高性能、更高速和更小的电子组件。为了实现这些要求，已经减小了集成电路芯片和印刷电路板的厚度。
发明内容
发明构思的实施例可以提供一种具有改善的结构稳定性的半导体封装件和一种用于制造该半导体封装件的方法。
发明构思的实施例还可以提供一种用于制造半导体封装件的方法，该方法能够减少缺陷或故障或者使缺陷或故障最少化。
在一个方面，一种半导体封装件可以包括封装基底、位于封装基底上并在其中具有腔的支撑结构以及在腔中位于封装基底上的至少一个第一半导体芯片。支撑结构可以具有面向腔的第一内侧壁、第一顶表面以及连接第一内侧壁和第一顶表面的第一倾斜表面。第一倾斜表面可以相对于所述至少一个第一半导体芯片的顶表面倾斜。
在一个方面，一种用于制造半导体封装件的方法可以包括：在基底上形成彼此间隔开的牺牲结构；在基底上形成覆盖牺牲结构的支撑层；对支撑层执行各向异性蚀刻工艺以形成暴露牺牲结构的顶表面的凹入；去除牺牲结构以在支撑层中形成腔；分别将半导体芯片设置在通过去除牺牲结构形成的腔中；以及在半导体芯片上形成模制层。
在一个方面，一种半导体封装件可以包括：封装基底，包括中心区域和围绕中心区域的外围区域；半导体芯片，位于封装基底的中心区域上；支撑结构，位于封装基底的外围区域上并围绕半导体芯片的至少两个侧壁；模制层，在封装基底上覆盖半导体芯片和支撑结构并且填充半导体芯片与支撑结构之间的空间；外部端子，位于封装基底的底表面上。半导体芯片的侧壁可以与封装基底的顶表面基本垂直。半导体芯片与支撑结构之间的距离可以从封装基底的顶表面到特定高度恒定或基本恒定，并且可以从该特定高度朝向支撑结构的顶表面逐渐地增大。
附图说明
借助于附图和后面的详细描述，发明构思将变得更明显。
图1A是示出根据发明构思的一些实施例的半导体封装件的剖视图。
图1B是示出根据发明构思的一些实施例的半导体封装件的平面图。
图2A是示出根据发明构思的一些实施例的半导体封装件的剖视图。
图2B和图2C是示出根据发明构思的一些实施例的半导体封装件的平面图。
图3A是示出根据发明构思的一些实施例的半导体封装件的剖视图。
图3B是示出根据发明构思的一些实施例的半导体封装件的平面图。
图4A是示出根据发明构思的一些实施例的半导体封装件的剖视图。
图4B是示出根据发明构思的一些实施例的半导体封装件的平面图。
图5和图6是示出根据发明构思的一些实施例的半导体封装件的剖视图。
图7至图15是示出根据发明构思的一些实施例的用于制造半导体封装件的方法的视图。
具体实施方式
在下文中将参照附图描述根据发明构思的半导体封装件。
图1A是示出根据发明构思的一些实施例的半导体封装件的剖视图。图1B是示出根据发明构思的一些实施例的半导体封装件的平面图。图1A对应于沿着图1B的线A-A'截取的剖视图。
参照图1A和图1B，半导体封装件10可以包括封装基底100、第一半导体芯片200、支撑结构300和/或模制层(或称为成型层)400。
封装基底100可以包括印刷电路板(PCB)。可选择地，封装基底100可以是具有电路图案的再分布基底。封装基底100可以具有其中绝缘层110和互连层120交替地堆叠的结构。例如，堆叠的互连层120可以通过穿透设置在其间的绝缘层110的过孔彼此连接。互连层120可以被绝缘层110围绕。绝缘层110可以包括聚合物材料或者可以包括诸如氧化硅或氮化硅的无机绝缘材料。例如，绝缘层110可以包括预浸料(prepreg)或阻焊剂。互连层120可以包括诸如金属的导电材料。包括绝缘层110和互连层120的封装基底100的总厚度可以大于10μm且小于80μm。
半导体封装件10可以通过封装基底100而具有扇出结构。互连层120的一部分可以被形成在提供封装基底100的顶表面100a的绝缘层110中的开口OP暴露，并且可以用作使第一半导体芯片200安装在其上的基底垫122。互连层120的另一部分可以从提供封装基底100的底表面100b的绝缘层110暴露，并且可以用作外部端子130连接到其的端子垫124。
封装基底100可以包括中心区域CR和外围区域PR。当在平面图中观察时，外围区域PR可以围绕中心区域CR。这里，中心区域CR可以是封装基底100的安装有第一半导体芯片200的区域。例如，封装基底100的基底垫122可以设置在中心区域CR中。
外部端子130可以设置在封装基底100的底表面100b上。外部端子130可以包括焊球或焊垫。根据外部端子130的种类，半导体封装件10可以具有球栅阵列(BGA)形式、精细球栅阵列(FBGA)形式或平面栅阵列(LGA)形式。外部端子130可以电连接到封装基底100的互连层120。在本说明书中，可以理解的是，当一个组件电连接到另一组件时，这个组件可以直接地或间接地连接到所述另一组件。
第一半导体芯片200可以设置在封装基底100上。第一半导体芯片200的面向封装基底100的底表面可以是后表面，并且第一半导体芯片200的顶表面200a可以是前表面。在本说明书中，前表面可以是与半导体芯片中的集成器件的有源表面相邻的表面，并且可以被定义为半导体芯片的垫形成在其上的表面。后表面可以被定义为与前表面相对的另一表面。第一半导体芯片200可以安装在封装基底100的中心区域CR上。第一半导体芯片200可以通过引线接合方法安装。第一半导体芯片200可以通过第一接合引线210电连接到封装基底100。第一接合引线210可以连接到设置在第一半导体芯片200的前表面200a上的芯片垫，并且可以穿过封装基底100的绝缘层110的开口OP连接到封装基底100的基底垫122。第一半导体芯片200可以通过封装基底100电连接到外部端子130。第一半导体芯片200可以通过第一粘合剂层220粘合到封装基底100的绝缘层110。
在某些实施例中，第一半导体芯片200可以通过倒装芯片方法安装。在示例实施例中，第一半导体芯片200的底表面可以是前表面，并且第一半导体芯片200的顶表面可以是后表面。第一半导体芯片200可以通过诸如焊球的芯片端子电连接到封装基底100。芯片端子可以设置在第一半导体芯片200与封装基底100之间，以分别连接到第一半导体芯片200的前表面的芯片垫和封装基底100的基底垫。
第一半导体芯片200可以是逻辑芯片或存储器芯片。例如，存储器芯片可以是DRAM芯片、NAND闪存芯片、NOR闪存芯片、PRAM芯片、ReRAM芯片或MRAM芯片。可选择地，第一半导体芯片200可以是诸如应用处理器的非存储器芯片。
支撑结构300可以设置在封装基底100上。支撑结构300可以设置在外围区域PR上。当在平面图中观察时，支撑结构300可以沿着外围区域PR围绕中心区域CR。例如，支撑结构300可以具有暴露中心区域CR的腔CA。支撑结构300的底表面可以与封装基底100的绝缘层110接触。支撑结构300可以支撑封装基底100以抑制或防止封装基底100变形。例如，在形成半导体封装件10的工艺中，支撑结构300可以从上方支撑封装基底100，以减少或防止具有薄厚度的封装基底100弯曲或翘曲。因此，可以改善半导体封装件10的结构稳定性。稍后将在用于制造半导体封装件10的方法中对此进行更详细地描述。支撑结构300可以包括绝缘材料。例如，支撑结构300可以包括味之素复合膜(ABF，ajinomoto build-up film)或树脂涂覆铜(RCC)。
支撑结构300可以设置在第一半导体芯片200的侧壁200b的侧面处。例如，第一半导体芯片200可以设置在支撑结构300的腔CA中，并且当在平面图中观察时，支撑结构300可以围绕第一半导体芯片200。支撑结构300可以与第一半导体芯片200间隔开。当第一半导体芯片200通过引线接合方法安装在封装基底100上时，第一半导体芯片200的第一接合引线210可以在第一半导体芯片200与支撑结构300之间与支撑结构300间隔开。支撑结构300的内侧壁300b与第一半导体芯片200之间的距离可以在从1μm至10μm的范围。然而，发明构思的实施例不限于此。在某些实施例中，支撑结构300的内侧壁300b与第一半导体芯片200之间的距离可以小于1μm或大于10μm。支撑结构300的顶表面300a可以定位在与第一半导体芯片200的顶表面200a的水平(水平面或高度)相同或基本相同的水平(水平面或高度)处。可选择地，与图1A不同，支撑结构300的顶表面300a可以比第一半导体芯片200的顶表面200a高或比第一半导体芯片200的顶表面200a低。
支撑结构300可以具有设置在顶表面300a与面向第一半导体芯片200的内侧壁300b之间的第一倾斜表面300c。第一倾斜表面300c可以使支撑结构300的顶表面300a和内侧壁300b连接。支撑结构300的内侧壁300b可以与封装基底100的顶表面100a垂直或基本垂直，并且第一倾斜表面300c可以相对于支撑结构300的内侧壁300b倾斜。例如，第一倾斜表面300c可以相对于封装基底100的顶表面100a和第一半导体芯片200的顶表面200a倾斜。支撑结构300的内侧壁300b和第一倾斜表面300c的接触点CP可以定位在比第一半导体芯片200的顶表面200a的水平低的水平处。换句话说，支撑结构300的内侧壁300b和第一倾斜表面300c的接触点CP定位所处的第一高度可以处于第一半导体芯片200的顶表面200a和底表面之间。因此，第一半导体芯片200与支撑结构300之间的距离可以从封装基底100的顶表面100a到第一高度是恒定的或基本恒定的，并且可以从第一高度朝向支撑结构300的顶表面300a逐渐地增大。当与图1A不同，支撑结构300的顶表面300a比第一半导体芯片200的顶表面200a高时，支撑结构300的内侧壁300b和第一倾斜表面300c的接触点CP可以定位在比第一半导体芯片200的顶表面200a的水平高的水平处。当在平面图中观察时，支撑结构300的第一倾斜表面300c可以围绕第一半导体芯片200。
模制层400可以设置在封装基底100上。模制层400可以在封装基底100的中心区域CR和外围区域PR上覆盖第一半导体芯片200和支撑结构300。模制层400可以填充第一半导体芯片200与支撑结构300之间的空间。模制层400可以包括诸如环氧模塑料(EMC)的绝缘聚合物材料。可选择地，模制层400可以包括绝缘聚合物(例如，环氧类聚合物)、有机材料或无机材料。
图2A是示出根据发明构思的一些实施例的半导体封装件的剖视图。图2B和图2C是示出根据发明构思的一些实施例的半导体封装件的平面图。图2A对应于沿着图2B和图2C的线B-B'截取的剖视图。在以下实施例中，与图1A和图1B的一些实施例中的组件相同的组件将由相同的附图标号或标记表示，并且为了易于和便于解释的目的，将省略或简要地提及对其的描述。换句话说，将主要描述以下实施例与图1A和图1B的一些实施例之间的差异。
参照图2A、图2B和图2C，支撑结构300'可以设置在封装基底100上。支撑结构300'可以设置在外围区域PR上。支撑结构300'可以设置在外围区域PR的一部分上。支撑结构300'可以支撑封装基底100以抑制或防止封装基底100变形。支撑结构300'可以覆盖或面向第一半导体芯片200的至少一个侧壁200b。
如图2B中所示，支撑结构300'可以覆盖或面向第一半导体芯片200的一个侧壁200b。支撑结构300'可以设置在第一半导体芯片200的侧面处，并且当在平面图中观察时，可以具有与第一半导体芯片200的所述一个侧壁200b平行的线形状。支撑结构300'可以与第一半导体芯片200间隔开。当在平面图中观察时，支撑结构300'的第一倾斜表面300c可以具有与第一半导体芯片200的所述一个侧壁200b平行的线形状。
可选择地，如图2C中所示，支撑结构300'可以覆盖或面向第一半导体芯片200的两个相邻侧壁200b。支撑结构300'可以在平面图中具有L形状，并且第一半导体芯片200可以定位在支撑结构300'内部。支撑结构300'可以与第一半导体芯片200间隔开。当在平面图中观察时，支撑结构300'的第一倾斜表面300c可以具有围绕第一半导体芯片200的所述两个相邻侧壁200b的L形状。
支撑结构300'可以具有设置在顶表面300a与面向第一半导体芯片200的内侧壁300b之间的第一倾斜表面300c。第一倾斜表面300c可以连接支撑结构300'的顶表面300a和内侧壁300b。支撑结构300'的内侧壁300b可以与封装基底100的顶表面垂直或基本垂直，并且第一倾斜表面300c可以相对于支撑结构300'的内侧壁300b倾斜。
图3A是示出根据发明构思的一些实施例的半导体封装件20的剖视图。图3B是示出根据发明构思的一些实施例的半导体封装件20的平面图。图3A对应于沿着图3B的线C-C'截取的剖视图。
参照图3A和图3B，多个半导体芯片200和500可以设置在封装基底100上。例如，第一半导体芯片200和第二半导体芯片500可以安装在封装基底100的中心区域CR上。第一半导体芯片200和第二半导体芯片500可以彼此间隔开。第一半导体芯片200和第二半导体芯片500可以通过引线接合方法安装。例如，第一半导体芯片200可以通过第一接合引线210电连接到封装基底100，并且第二半导体芯片500可以通过第二接合引线510电连接到封装基底100。第一半导体芯片200和第二半导体芯片500可以分别通过第一粘合剂层220和第二粘合剂层520粘合到封装基底100的绝缘层110。
第一半导体芯片200和第二半导体芯片500中的每个可以是逻辑芯片或存储器芯片。例如，第一半导体芯片200可以是逻辑芯片，第二半导体芯片500可以是存储器芯片。可选择地，第一半导体芯片200和第二半导体芯片500可以是相同种类的芯片。
第一半导体芯片200和第二半导体芯片500中的每个可以设置为多个。如图3A中所示，多个第一半导体芯片200可以竖直地堆叠以构成第一芯片堆叠件230，并且多个第二半导体芯片500可以竖直地堆叠以构成第二芯片堆叠件530。在某些实施例中，第一半导体芯片200和第二半导体芯片500中的一者可以设置为多个。可选择地，第一半导体芯片200和第二半导体芯片500中的每者可以设置为单个。
支撑结构300可以设置在封装基底100上。支撑结构300可以设置在封装基底100的外围区域PR上。当在平面图中观察时，支撑结构300可以沿着外围区域PR围绕中心区域CR。第一芯片堆叠件230和第二芯片堆叠件530可以设置在支撑结构300的腔CA中，并且当在平面图中观察时，支撑结构300可以围绕第一芯片堆叠件230和第二芯片堆叠件530。支撑结构300的顶表面300a可以定位在与第一芯片堆叠件230的顶表面230a和第二芯片堆叠件530的顶表面530a的水平相同的水平或基本相同的水平处。可选择地，支撑结构300的顶表面300a可以比第一芯片堆叠件230的顶表面230a和第二芯片堆叠件530的顶表面530a高或比第一芯片堆叠件230的顶表面230a和第二芯片堆叠件530的顶表面530a低。
支撑结构300可以具有设置在支撑结构300的顶表面300a和内侧壁300b之间的第一倾斜表面300c。第一倾斜表面300c可以使支撑结构300的顶表面300a和内侧壁300b连接。支撑结构300的内侧壁300b可以与封装基底100的顶表面100a垂直或基本垂直，并且第一倾斜表面300c可以相对于支撑结构300的内侧壁300b倾斜。
模制层400可以设置在封装基底100上。模制层400可以在封装基底100的中心区域CR和外围区域PR上覆盖第一芯片堆叠件230、第二芯片堆叠件530和支撑结构300。模制层400可以填充第一芯片堆叠件230与支撑结构300之间的空间、第二芯片堆叠件530与支撑结构300之间的空间以及第一芯片堆叠件230与第二芯片堆叠件530之间的空间。
图4A是示出根据发明构思的一些实施例的半导体封装件的剖视图。图4B是示出根据发明构思的一些实施例的半导体封装件的平面图。图4A对应于沿着图4B的线D-D'截取的剖视图。
参照图4A和图4B，封装基底100可以包括中心区域CR、外围区域PR和分离区域SR。当在平面图中观察时，外围区域PR可以围绕中心区域CR。分离区域SR可以与中心区域CR交叉。换句话说，分离区域SR可以将由外围区域PR围绕的中心区域CR划分成两个子区域SCR1和SCR2。
多个半导体芯片200和500可以设置在封装基底100上。例如，第一半导体芯片200和第二半导体芯片500可以安装在封装基底100的中心区域CR上。第一半导体芯片200和第二半导体芯片500可以分别设置在子区域SCR1和SCR2上。第一半导体芯片200和第二半导体芯片500可以通过引线接合方法安装。第一半导体芯片200和第二半导体芯片500中的每个可以是逻辑芯片或存储器芯片。
支撑结构300可以设置在封装基底100上。支撑结构300可以设置在外围区域PR上。当在平面图中观察时，支撑结构300可以沿着外围区域PR围绕中心区域CR。第一半导体芯片200和第二半导体芯片500可以设置在支撑结构300的腔CA中，并且当在平面图中观察时，支撑结构300可以围绕第一半导体芯片200和第二半导体芯片500。支撑结构300的顶表面300a可以定位在与第一半导体芯片200的顶表面200a和第二半导体芯片500的顶表面500a的水平相同的水平或基本相同的水平处。可选择地，支撑结构300的顶表面300a可以比第一半导体芯片200的顶表面200a和第二半导体芯片500的顶表面500a高或比第一半导体芯片200的顶表面200a和第二半导体芯片500的顶表面500a低。
支撑结构300还可以包括分离结构600。分离结构600可以设置在封装基底100的分离区域SR上。分离结构600可以与腔CA交叉。换句话说，分离结构600可以将支撑结构300中的腔CA划分成两个子腔SCA1和SCA2。分离结构600可以使子区域SCR1和SCR2彼此分离或隔离。分离结构600可以在第一半导体芯片200与第二半导体芯片500之间相交。换句话说，支撑结构300和分离结构600可以限定其上分别安装有第一半导体芯片200和第二半导体芯片500的区域。分离结构600可以与第一半导体芯片200和第二半导体芯片500间隔开。分离结构600的顶表面600a可以定位在与第一半导体芯片200的顶表面200a和第二半导体芯片500的顶表面500a的水平相同的水平或基本相同的水平处。可选择地，分离结构600的顶表面600a可以比第一半导体芯片200的顶表面200a和第二半导体芯片500的顶表面500a高或低。此外，分离结构600的顶表面600a可以定位在与支撑结构300的顶表面300a的水平相同的水平或基本相同的水平处。
分离结构600可以具有设置在顶表面600a与面向子腔SCA1和SCA2的内侧壁600b之间的第二倾斜表面600c。第二倾斜表面600c可以使分离结构600的顶表面600a和内侧壁600b连接。分离结构600的内侧壁600b可以与封装基底100的顶表面100a垂直或基本垂直，并且第二倾斜表面600c可以相对于分离结构600的内侧壁600b倾斜。例如，第二倾斜表面600c可以相对于封装基底100的顶表面100a倾斜。分离结构600的第二倾斜表面600c可以定位在与支撑结构300的第一倾斜表面300c的水平相同的水平处，并且可以连接到第一倾斜表面300c。
在某些实施例中，分离结构600的顶表面600a可以定位在比支撑结构300的顶表面300a低的水平处。例如，支撑结构300的顶表面300a可以与第一半导体芯片200的顶表面200a和第二半导体芯片500的顶表面500a定位在同一水平处或者定位在比第一半导体芯片200的顶表面200a和第二半导体芯片500的顶表面500a高的水平处，并且分离结构600的顶表面600a可以与第一半导体芯片200的顶表面200a和第二半导体芯片500的顶表面500a定位在同一水平处或者定位在比第一半导体芯片200的顶表面200a和第二半导体芯片500的顶表面500a低的水平处。分离结构600的第二倾斜表面600c可以不连接到支撑结构300的第一倾斜表面300c。
图5是示出根据发明构思的一些实施例的半导体封装件的剖视图。
参照图5，第一半导体芯片200可以设置在封装基底100上。第一半导体芯片200可以安装在封装基底100的中心区域CR上。第一半导体芯片200可以通过引线接合方法安装。第一半导体芯片200可以通过第一粘合剂层(未示出)粘合到封装基底100的绝缘层110。第一半导体芯片200可以通过第一接合引线210电连接到封装基底100。第一半导体芯片200可以是逻辑芯片。
间隔件芯片SPC可以设置在封装基底100上。间隔件芯片SPC可以在封装基底100的中心区域CR上与第一半导体芯片200间隔开。间隔件芯片SPC的顶表面可以与第一半导体芯片200的顶表面定位在同一水平处。间隔件芯片SPC可以是虚设芯片。
第三半导体芯片700可以设置在第一半导体芯片200上。第三半导体芯片700可以设置在第一半导体芯片200和间隔件芯片SPC上。第三半导体芯片700可以由第一半导体芯片200和间隔件芯片SPC支撑。第三半导体芯片700可以设置为多个。例如，多个第三半导体芯片700可以竖直地堆叠以构成第三芯片堆叠件730。第三半导体芯片700可以通过引线接合方法安装。第三半导体芯片700可以通过第三接合引线710电连接到封装基底100。第三半导体芯片700可以是存储器芯片。
支撑结构300可以设置在封装基底100上。支撑结构300可以设置在封装基底100的外围区域PR上。当在平面图中观察时，支撑结构300可以沿着外围区域PR围绕中心区域CR。第一半导体芯片200、间隔件芯片SPC和第三芯片堆叠件730可以设置在支撑结构300的腔CA中，并且当在平面图中观察时，支撑结构300可以围绕第一半导体芯片200、间隔件芯片SPC和第三芯片堆叠件730。支撑结构300的顶表面300a可以定位在与第三芯片堆叠件730的顶表面730a的水平相同的水平或基本相同的水平处。可选择地，支撑结构300的顶表面300a可以比第三芯片堆叠件730的顶表面730a高或比第三芯片堆叠件730的顶表面730a低。
模制层400可以设置在封装基底100上。模制层400可以在封装基底100的中心区域CR和外围区域PR上覆盖第一半导体芯片200、间隔件芯片SPC和第三芯片堆叠件730以及支撑结构300。
图6是示出根据发明构思的一些实施例的半导体封装件的剖视图。
参照图6，第一半导体芯片200可以设置在封装基底100上。第一半导体芯片200可以安装在封装基底100的中心区域CR上。第一半导体芯片200可以通过引线接合方法安装。第一半导体芯片200可以是逻辑芯片。
支撑结构300可以设置在封装基底100上。支撑结构300可以设置在封装基底100的外围区域PR上。当在平面图中观察时，支撑结构300可以沿着外围区域PR围绕中心区域CR。第一半导体芯片200可以设置在支撑结构300的腔CA中，当在平面图中观察时，支撑结构300可以围绕第一半导体芯片200。支撑结构300的顶表面300a可以定位在与第一半导体芯片200的顶表面200a的水平相同的水平或基本相同的水平处。
第四半导体芯片800可以设置在第一半导体芯片200上。第四半导体芯片800可以设置在第一半导体芯片200和支撑结构300上。换句话说，第四半导体芯片800可以覆盖中心区域CR并且可以与外围区域PR的一部分叠置。第四半导体芯片800可以由第一半导体芯片200和支撑结构300支撑。第四半导体芯片800可以设置为多个。例如，多个第四半导体芯片800可以竖直地堆叠以构成第四芯片堆叠件830。第四半导体芯片800可以通过引线接合方法安装。第四半导体芯片800可以通过第四接合引线810电连接到封装基底100。第四接合引线810中的至少一些可以穿透封装基底100的支撑结构300和绝缘层110，以连接到封装基底100的互连层120。第四半导体芯片800可以是存储器芯片。
模制层400可以设置在封装基底100上。模制层400可以在封装基底100的中心区域CR和外围区域PR上覆盖第一半导体芯片200、第四芯片堆叠件830和支撑结构300。
图7至图15是示出根据发明构思的一些实施例的用于制造半导体封装件的方法的视图。图7、图10和图13是平面图，图8、图9、图11、图12、图14和图15是剖视图。图8对应于沿着图7的线E-E'截取的剖视图，图14对应于沿着图13的线F-F'截取的剖视图。
参照图7和图8，可以提供基底100'。基底100'可以包括中心区域CR和围绕中心区域CR的外围区域PR。基底100'可以是用于同时形成多个封装件的基底。例如，如图7中所示，基底100'可以包括多个中心区域CR，并且外围区域PR可以围绕中心区域CR中的每个。可以通过随后的锯切工艺将基底100'划分成封装基底100(见图1A)。基底100'可以包括印刷电路板(PCB)。基底100'可以具有其中绝缘层110和互连层120交替地堆叠的结构。包括绝缘层110和互连层120的基底100'的总厚度可以大于10μm且小于80μm。
可以在基底100'下方设置载体基底140。可以通过载体粘合剂层将载体基底140粘合到基底100'的底表面。载体基底140可以从下方支撑基底100'。
参照图9，可以在基底100'上形成牺牲结构900。可以在基底100'的中心区域CR上分别设置牺牲结构900。例如，可以形成牺牲层以覆盖基底100'，然后，可以将牺牲层图案化以形成牺牲结构900。此时，牺牲结构900的侧壁900b可以与基底100'的顶表面垂直或基本垂直。牺牲结构900的平面形状可以与稍后将安装在基底100'上的半导体芯片200(见图1B或图15)的平面形状对应，并且牺牲结构900的高度可以等于或小于半导体芯片200的高度。牺牲结构900可以包括光敏材料。例如，牺牲结构900可以包括干膜抗蚀剂(DFR)和/或光可成像电介质(PID)。
在某些实施例中，可以在基底100'上形成单个牺牲结构900'。如图10中所示，单个牺牲结构900'可以与多个中心区域CR叠置。换句话说，牺牲结构900'可以覆盖多个中心区域CR和外围区域PR的设置在中心区域CR之间的部分。在下文中，将描述图9的一些实施例作为示例。
参照图11，可以在基底100'上形成支撑层310。可以在基底100'的中心区域CR和外围区域PR上形成支撑层310。支撑层310可以覆盖牺牲结构900。例如，支撑层310可以与牺牲结构900的顶表面900a和侧壁900b接触。支撑层310的高度可以等于稍后将在基底100'上安装的半导体芯片200(见图1A或图15)的高度。可选择地，支撑层310的高度可以比半导体芯片200的高度高或比半导体芯片200的高度低。可以通过将绝缘材料涂敷到基底100'上来形成支撑层310。绝缘材料可以相对于牺牲结构900具有蚀刻选择性。绝缘材料可以包括味之素复合膜(ABF)或树脂涂覆铜(RCC)。
具有薄厚度的基底100'可能在用于形成半导体封装件的各种工艺(例如，传送基底的工艺、对基底执行的蚀刻工艺、沉积工艺和/或芯片安装工艺)中弯曲或翘曲。可以在基底100'上设置支撑层310以支撑基底100'。因此，支撑层310可以减少或防止基底100'在这些工艺中弯曲或翘曲。结果，可以减少在用于形成半导体封装件的工艺中出现的缺陷或故障。
此后，可以去除载体基底140。
参照图12，可以在支撑层310(见图11)上形成掩模图案MP。可以在外围区域PR上形成掩模图案MP以暴露中心区域CR。此时，考虑到稍后将描述的蚀刻工艺中的工艺分散或工艺误差，被掩模图案MP暴露的暴露区域ER可以比中心区域CR大。例如，当在平面图中观察时，中心区域CR可以定位在暴露区域ER中。换句话说，掩模图案MP可以暴露中心区域CR以及外围区域PR的与中心区域CR相邻的部分。掩模图案MP的内侧壁可以与中心区域CR水平地间隔开。
可以对支撑层310(见图11)执行蚀刻工艺以形成支撑结构300。可以使用掩模图案MP作为蚀刻掩模来执行蚀刻工艺。蚀刻工艺可以包括各向异性蚀刻工艺。例如，蚀刻工艺可以包括喷砂工艺。可以通过蚀刻工艺蚀刻支撑层310以在暴露区域ER中形成凹入RS。可以通过去除支撑层310的第一部分312和第二部分314来形成凹入RS。支撑层310的第一部分312可以设置在牺牲结构900中的每个上，支撑层310的第二部分314可以设置在牺牲结构900与掩模图案MP之间。因此，可以暴露牺牲结构900的顶表面900a。此时，由于蚀刻工艺的工艺分散或误差，第二部分314的蚀刻深度可以随着与掩模图案MP的距离减小而减小。因此，凹入RS的内侧壁(例如，支撑结构300的通过去除第二部分314而形成的倾斜表面300c)可以相对于牺牲结构900的顶表面900a和掩模图案MP的侧壁倾斜。
在某些实施例中，如图10中所示，可以形成单个牺牲结构900'以覆盖中心区域CR，然后可以蚀刻支撑层的覆盖牺牲结构900'的部分。可以通过蚀刻工艺蚀刻支撑层，并且因此可以形成支撑结构300"。此时，可以暴露牺牲结构900'。当在平面图中观察时，支撑结构300"可以围绕多个中心区域CR中的所有。在下文中，将描述图12的一些实施例。
参照图13和图14，可以去除掩模图案MP。因此，可以暴露支撑结构300的顶表面300a。
可以去除牺牲结构900(见图12)。可以使用湿蚀刻工艺去除牺牲结构900。牺牲结构900可以相对于支撑结构300和基底100'具有蚀刻选择性，因此支撑结构300可以在湿蚀刻工艺期间不被去除。详细地，如图13和图14中所示，可以去除牺牲结构900以在支撑结构300中形成腔CA。腔CA可以定位在中心区域CR上。腔CA中的每个可以是在后续工艺中将安装有半导体芯片200(见图15)中的每个的区域。由于牺牲结构900的侧壁900b与基底100'的顶表面垂直或基本垂直，所以腔CA的内侧壁(例如，支撑结构300的内侧壁300b)可以与基底100'的顶表面垂直或基本垂直。
可以在基底上形成绝缘材料(例如，支撑层)，然后，可以通过蚀刻支撑层来形成支撑结构的腔。在示例实施例中，腔的内侧壁可以是倾斜的，蚀刻残留物会累积在基底上和腔中，并且/或者腔的内侧壁可以是凹的。例如，如果通过喷砂工艺蚀刻支撑层，则腔的内侧壁可以是倾斜的。可选择地，如果通过喷砂工艺或激光开槽工艺蚀刻支撑层，则在蚀刻工艺中出现的残留物会粘附到腔的内侧壁和基底的顶表面。可选择地，如果通过湿蚀刻工艺蚀刻支撑层，则腔的内侧壁可能凹地形成(例如，倒圆蚀刻)，并且基底可能被蚀刻溶液损坏。
然而，根据发明构思的一些实施例，可以形成具有与基底100'的顶表面垂直或基本垂直的侧壁900b的牺牲结构900，可以形成支撑层310以围绕牺牲结构900，然后，可以去除牺牲结构900以形成支撑结构300。因此，腔CA的内侧壁(例如，支撑结构300的内侧壁300b)可以与基底100'的顶表面垂直或基本垂直。
另外，与由高强度材料形成的用来支撑基底100'的支撑结构300不同，对牺牲结构900的材料的限制会较少。例如，可以由相对于基底100'具有大蚀刻选择性的材料形成牺牲结构900。可以通过湿蚀刻牺牲结构900来形成支撑结构300的腔CA。因此，在蚀刻工艺中，不会产生残留物并且不会损坏基底100'。
此外，可以根据牺牲结构900的形状来形成支撑结构300的腔CA的形状，因此腔CA可以容易地以各种期望的形状形成。
参照图15，可以将半导体芯片200安装在基底100'上。可以在支撑结构300的腔CA中设置半导体芯片200。可以通过使用粘合剂层220将半导体芯片200粘合到基底100'的中心区域CR上。可以通过接合引线210将半导体芯片200安装在基底100'上。支撑结构300的内侧壁300b与每个半导体芯片200之间的距离可以在从1μm至10μm的范围。如果支撑结构300与半导体芯片200之间的距离小于1μm，则会难以在后续工艺中将模制材料提供到支撑结构300与半导体芯片200之间的空间中。然而，发明构思的实施例不限于此。在某些实施例中，支撑结构300的内侧壁300b与每个半导体芯片200之间的距离可以大于10μm。
在图15中，在一个中心区域CR上安装了一个半导体芯片200。然而，发明构思的实施例不限于此。在某些实施例中，可以在一个中心区域上安装多个半导体芯片。在示例实施例中，可以制造出根据图3A和图3B的一些实施例的半导体封装件20。在下文中，将描述图15的一些实施例。
可以在基底100'上形成模制层400。可以通过将模制材料涂敷到基底100'上来形成模制层400。此时，模制材料可以填充支撑结构300与半导体芯片200之间的空间。
如果在形成支撑结构的腔的一般工艺中在基底上和腔中产生并累积残留物并且/或者腔的内侧壁是凹的，则会难以将模制材料提供到支撑结构与半导体芯片之间的空间中。在示例实施例中，中空部(例如，气隙)会形成在基底与模制层之间，并且/或者杂质(例如，残留物)会保留在模制层中。因此，会造成半导体封装件的缺陷或故障。
然而，根据发明构思的一些实施例，腔CA的内侧壁(例如，支撑结构300的内侧壁300b)可以形成为与基底100'的顶表面垂直或基本垂直，并且支撑结构300与半导体芯片200之间的空间可以具有均匀的或基本均匀的宽度。因此，可以容易地向支撑结构300与半导体芯片200之间的空间中提供模制材料，并且可以减少半导体封装件的缺陷或故障或者使半导体封装件的缺陷或故障最少化。
参照图1A、图1B和图15，可以对图15的所得结构执行切单工艺。例如，可以切割模制层400、支撑结构300和基底100'以将半导体封装件10彼此分离。换句话说，可以沿着定位在半导体芯片200之间的锯切线SL锯切模制层400、支撑结构300和基底100'，因此可以将半导体芯片200彼此分离。可以通过上述工艺制造出图1A和图1B的半导体封装件10。
在某些实施例中，如图10中所示，支撑结构300"可以形成为围绕多个中心区域CR中的所有。支撑结构300"可以围绕形成在多个中心区域CR上的单个牺牲结构900'。可以去除牺牲结构900'以形成单个腔CA'。可以将半导体芯片安装在基底100'上。可以将半导体芯片设置在支撑结构300"的腔CA'中，并且可以在中心区域CR中的每个上设置半导体芯片中的每个。可以在基底100'上形成模制层。模制层可以填充支撑结构300"与半导体芯片之间的空间以及半导体芯片之间的空间。可以切割模制层、支撑结构300"和基底100'以使半导体封装件彼此分离。此时，图10中的区域“A”的半导体封装件可以是图2A和2B的半导体封装件，并且图10中的区域“B”的半导体封装件可以是图2A和图2C的半导体封装件。
根据发明构思的一些实施例，支撑结构可以支撑封装基底以减少或防止封装基底变形，因此半导体封装件的结构稳定性可以得到改善。
在根据发明构思的一些实施例的用于制造半导体封装件的方法中，支撑层和使用支撑层形成的支撑结构可以在基底上支撑基底，并且可以减少或防止具有薄厚度的基底在用于形成半导体封装件的各种工艺中弯曲或翘曲。结果，可以减少在用于形成半导体封装件的工艺中发生的缺陷或故障。
另外，在用于形成腔的蚀刻工艺中，不会产生残留物并且不会损坏基底。此外，支撑结构的腔的形状可以由牺牲结构的形状确定，因此腔可以容易地形成为各种期望的形状。此外，可以容易地将模制材料提供到支撑结构与半导体芯片之间的空间中，并且可以减少半导体封装件的缺陷或故障或者使半导体封装件的缺陷或故障最少化。
虽然已经参照示例实施例描述了发明构思，但是对于本领域技术人员将明显的是，在不脱离发明构思的精神和范围的情况下，可以进行各种改变和修改。因此，应理解的是，以上实施例不是限制性的，而是说明性的。因此，发明构思的范围将由权利要求及其等同物的最宽可允许的解释来确定，并且不应受前面描述的约束或限制。

Claims (20)

1.一种半导体封装件，所述半导体封装件包括：
封装基底；
支撑结构，位于封装基底上并在其中具有腔；以及
至少一个第一半导体芯片，在腔中位于封装基底上，
其中，支撑结构具有：第一内侧壁，面向腔；第一顶表面；以及第一倾斜表面，连接第一内侧壁和第一顶表面，并且
其中，第一倾斜表面相对于所述至少一个第一半导体芯片的顶表面倾斜。
2.根据权利要求1所述的半导体封装件，其中，支撑结构的第一内侧壁和第一倾斜表面的接触点位于比所述至少一个第一半导体芯片的顶表面的水平低的水平处。
3.根据权利要求1所述的半导体封装件，其中，支撑结构的第一顶表面位于与所述至少一个第一半导体芯片的顶表面的水平基本相同的水平处。
4.根据权利要求1所述的半导体封装件，其中，支撑结构的第一内侧壁与所述至少一个第一半导体芯片之间的距离在从1μm至10μm的范围。
5.根据权利要求1所述的半导体封装件，其中，支撑结构的第一内侧壁与封装基底的顶表面基本垂直。
6.根据权利要求1所述的半导体封装件，其中，所述至少一个第一半导体芯片通过接合引线连接到封装基底，并且
其中，接合引线在第一半导体芯片与支撑结构之间与支撑结构间隔开。
7.根据权利要求1所述的半导体封装件，其中，所述支撑结构还包括：分离结构，位于封装基底上，以将腔划分成多个子腔，
其中，所述至少一个第一半导体芯片为多个第一半导体芯片，并且
其中，所述多个第一半导体芯片分别位于所述多个子腔中。
8.根据权利要求7所述的半导体封装件，其中，所述分离结构具有：第二内侧壁，面向每个子腔；第二顶表面；以及第二倾斜表面，连接第二内侧壁和第二顶表面，并且
其中，第二倾斜表面中的每个相对于所述多个第一半导体芯片的顶表面倾斜。
9.根据权利要求8所述的半导体封装件，其中，分离结构的第二顶表面位于与支撑结构的第一顶表面的水平相同的水平处，并且
其中，分离结构的第二倾斜表面位于与支撑结构的第一倾斜表面的水平相同的水平处并且连接到第一倾斜表面。
10.根据权利要求1所述的半导体封装件，所述半导体封装件还包括：
第二半导体芯片，位于所述至少一个第一半导体芯片上并安装到封装基底。
11.根据权利要求10所述的半导体封装件，其中，第二半导体芯片位于腔中，并且
其中，支撑结构的第一顶表面位于与第二半导体芯片的顶表面的水平基本相同的水平处。
12.根据权利要求10所述的半导体封装件，其中，支撑结构的第一顶表面位于与所述至少一个第一半导体芯片的顶表面的水平基本相同的水平处，并且
其中，第二半导体芯片位于所述至少一个第一半导体芯片和支撑结构上。
13.根据权利要求1所述的半导体封装件，所述半导体封装件还包括：
模制层，在封装基底上覆盖所述至少一个第一半导体芯片和支撑结构，
其中，模制层填充支撑结构与所述至少一个第一半导体芯片之间的空间。
14.一种用于制造半导体封装件的方法，所述方法包括：
在基底上形成彼此间隔开的牺牲结构；
在基底上形成覆盖牺牲结构的支撑层；
对支撑层执行各向异性蚀刻工艺以形成暴露牺牲结构的顶表面的凹入；
去除牺牲结构以在支撑层中形成腔；
分别将半导体芯片设置在通过去除牺牲结构形成的腔中；以及
在半导体芯片上形成模制层。
15.根据权利要求14所述的方法，其中，牺牲结构的侧壁与基底的顶表面垂直。
16.根据权利要求14所述的方法，其中，在执行各向异性蚀刻工艺之后，凹入的内侧壁相对于牺牲结构的顶表面和牺牲结构的侧壁倾斜。
17.根据权利要求14所述的方法，所述方法还包括：
在形成模制层之后，切割模制层、支撑层和基底以使半导体芯片彼此分离。
18.根据权利要求14所述的方法，其中，模制层填充具有腔的支撑层与半导体芯片之间的空间。
19.一种半导体封装件，所述半导体封装件包括：
封装基底，包括中心区域和围绕中心区域的外围区域；
半导体芯片，位于封装基底的中心区域上；
支撑结构，位于封装基底的外围区域上并围绕半导体芯片的至少两个侧壁；
模制层，在封装基底上覆盖半导体芯片和支撑结构，并且填充半导体芯片与支撑结构之间的空间；以及
外部端子，位于封装基底的底表面上，
其中，半导体芯片的侧壁与封装基底的顶表面基本垂直，并且
其中，半导体芯片与支撑结构之间的距离从封装基底的顶表面到特定高度基本恒定，并且从所述特定高度朝向支撑结构的顶表面逐渐地增大。
20.根据权利要求19所述的半导体封装件，其中，所述支撑结构具有：内侧壁，面向半导体芯片；顶表面；以及倾斜表面，连接内侧壁和顶表面，并且
其中，倾斜表面相对于半导体芯片的顶表面倾斜。
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