CN112394202A - Interconnection test fixture and interconnection test method for silicon adapter plate - Google Patents
Interconnection test fixture and interconnection test method for silicon adapter plate Download PDFInfo
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- CN112394202A CN112394202A CN202011187409.0A CN202011187409A CN112394202A CN 112394202 A CN112394202 A CN 112394202A CN 202011187409 A CN202011187409 A CN 202011187409A CN 112394202 A CN112394202 A CN 112394202A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
- G01R1/04—Housings; Supporting members; Arrangements of terminals
- G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/54—Testing for continuity
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/66—Testing of connections, e.g. of plugs or non-disconnectable joints
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Abstract
The invention belongs to the technical field of advanced electronic packaging, and discloses an interconnection test fixture and an interconnection test method for a silicon adapter plate, wherein the test fixture comprises a fixture body and a plurality of silica gel pads, the fixture body is provided with a through hole and a vacuum joint, the inner wall of the through hole is provided with a wafer placing ring, the wafer placing ring is provided with a plurality of cavities, and the cavities are provided with vacuum adsorption grooves and a plurality of mounting holes; the silica gel pad is provided with a plurality of vacuum holes and a plurality of bulges, the bulges are respectively connected with the mounting holes, and the vacuum holes are communicated with the vacuum adsorption grooves. The test method comprises the steps of obtaining test data on a silicon adapter plate to be tested; setting the placing position of the silicon adapter plate according to the test data on the silicon adapter plate to be tested and loading the silicon adapter plate to be tested on the interconnection test fixture; and generating an open circuit test scheme and a short circuit test scheme of each test point network for testing. The risk of splintering is effectively avoided, direct test is adopted, light and reliable contact is guaranteed, product damage is avoided, and post-process machining is not affected.
Description
Technical Field
The invention belongs to the technical field of advanced electronic packaging, and relates to an interconnection test fixture and an interconnection test method for a silicon adapter plate.
Background
The feature sizes of integrated circuits are now approaching physical limits and continuing to increase integration density by reducing device feature sizes is becoming increasingly difficult and does not bring significant cost and performance benefits. With the continuous development of chip packaging technology, chip integration is moving from an arrangement mode of two-dimensional plane distribution to a three-dimensional stacking mode, and 2.5D/3D advanced packaging technology is the technology which is the first to bear more than moore's law. The 2.5D refers to a manufacturing process in which chips are manufactured, not packaged, but arranged in parallel on the same substrate, and then connected to an Interposer (Interposer) Through a wire bonding or flip-chip or Through-Silicon-Via (TSV) process, so as to connect a plurality of functional chips in a vertical direction. The Interposer is also called an intermediate layer or an Interposer, and generally refers to a functional layer for interconnection and pin redistribution between a chip and a package substrate, and at present, the Interposer is mainly made of a silicon-based material, silicon is used as the Interposer, and TSV is a circuit interconnection tool, so that an integrated system is smaller, more power is saved, and higher bandwidth is provided.
The existing TSV mass production process is not mature, the interconnection channel on the silicon interposer cannot be completely reworked, and if the interconnection channel is assembled on a defective silicon interposer, expensive and precise bare chip testing becomes a waste. To ensure assembly yield and reduce system production costs, the silicon interposer must be tested before the chips are assembled to ensure that it is known to be good. In the processing process of the silicon adapter plate, whether conductive materials exist in the interconnection direction of each plane can be observed through an optical method, but the silicon adapter plate is mostly interconnected through high-density TSVs, and the defect detection in the vertical interconnection direction cannot adopt the optical inspection method, so that the method only depends on high-quality process control. Even if each layer is optically inspected, temperature and process induced interlayer stress can cause defects in the interconnect that need to be diagnosed before the chip is mounted. Both open defects of the internal interconnects and short defects between the internal interconnects need to be inspected by silicon interposer testing, sometimes requiring high resolution in order to inspect for potential or possible defects. These defects are physical imperfections that, while not immediately creating an open or short circuit, may become open or short circuits in the near future. These defects may cause unpredictable failures during post-processing or in use by the user, and are of particular concern, particularly during use, where potential open circuits are more likely to result from thermal, mechanical or bias stresses, while the ion deposition or the photolithography process may result in electrical leakage or potential shorts.
At present, for the interconnection test of the silicon adapter plate, no existing and effective test method exists in the industry, and no uniform test standard exists, so that the current mainstream probe test equipment does not support the simultaneous loading test connection of the surface and the back of the wafer. The flying probe tester for PCB (printed circuit board) can load and test the PCB surface and back, but can not be directly used for testing the silicon adapter plate, and the holding and supporting of the flying probe tester are more difficult. Some packaging processes abandon the testing link of the silicon adapter plate, and test is carried out after the silicon adapter plate is welded with a chip or even after packaging is finished, so that the risk of scrapping is increased, or the test structure which is designed to be attached to the characteristics of the product indirectly represents the preparation quality, so that the design cost is increased, and the yield is influenced by the area overhead.
Disclosure of Invention
The invention aims to overcome the defect of difficulty in interconnection test of a silicon adapter plate in the prior art, and provides an interconnection test fixture and an interconnection test method of the silicon adapter plate.
In order to achieve the purpose, the invention adopts the following technical scheme to realize the purpose:
on one hand, the interconnection test fixture for the silicon adapter plate comprises a fixture body and a plurality of silica gel pads, wherein a through hole is formed in the fixture body, a wafer placing ring is arranged on the inner wall of the through hole, a plurality of cavities are formed in the wafer placing ring, and a vacuum adsorption groove and a plurality of mounting holes are formed in each cavity; the clamp body is provided with a plurality of vacuum joints communicated with the vacuum adsorption grooves; the silica gel pad is provided with a plurality of vacuum holes and a plurality of bulges, the bulges are respectively connected with the mounting holes, and the vacuum holes are communicated with the vacuum adsorption grooves.
The interconnection test fixture of the silicon adapter plate is further improved in that:
the clamp comprises a clamp body and is characterized in that a first annular sinking step is formed in one side of the clamp body, a second annular sinking step is formed in the other side of the clamp body, the inner wall of the first annular sinking step coincides with the outer wall of a wafer placing ring, and the inner wall of the second annular sinking step coincides with the inner wall of the wafer placing ring.
And a plurality of scales are uniformly arranged on the clamp body along the circumferential direction of the wafer placing ring.
The clamp body is provided with a plurality of handles.
The side walls of the two ends of the cavity are both inclined inwards.
In another aspect of the present invention, a method for testing interconnection of a silicon interposer includes the following steps:
s1: acquiring the shape, coordinates and network of a measuring point on a silicon adapter plate to be measured;
s2: setting the placing position of the silicon adapter plate according to the shape of a measuring point, the measuring point coordinate and the measuring point network on the silicon adapter plate to be measured, and loading the silicon adapter plate to be measured on the test fixture of claim 1 according to the placing position;
s3: obtaining an open circuit test scheme and a short circuit test scheme of each test point network according to the distribution of the test point networks on the silicon adapter plate to be tested, and testing according to the open circuit test scheme and the short circuit test scheme;
s4: and outputting a test result, and unloading the silicon adapter plate to be tested.
The interconnection test method of the silicon adapter plate is further improved as follows:
the specific method for loading the silicon interposer to be tested on the interconnection test fixture according to the placement position in the step S2 is as follows: scanning points are arranged on two sides of the silicon adapter plate to be tested, and the silicon adapter plate to be tested is loaded on the interconnection test fixture according to the placing position based on the scanning points and the scale on the interconnection test fixture.
The short-circuit test scheme in the S3 is obtained as follows:
setting the largest measuring point network on the silicon adapter plate to be measured as an antenna network, and when the coverage rate of the antenna network is greater than a preset threshold value, determining that the short circuit test scheme of each measuring point network is as follows: acquiring a measuring point network of a suspected short circuit by adopting an electric field short circuit testing method, and testing the measuring point network of the suspected short circuit by adopting a resistance method; otherwise, determining the short circuit test scheme of each test point network as follows: and (3) acquiring a measuring point network of the suspected short circuit by adopting a proximity distance method, and testing the measuring point network of the suspected short circuit by adopting a resistance method.
The open circuit test scheme in the S3 is an open circuit test method by an electric field method and/or an open circuit test method by a resistance method.
The S4 further includes: and retesting the measuring point network of the open circuit fault.
Compared with the prior art, the invention has the following beneficial effects:
according to the test fixture, the wafer placing ring is supported by the wafer placing ring, the silicon adapter plate is adsorbed by the vacuum holes distributed on the silica gel pad, the silica gel pad isolates the silicon adapter plate from the fixture body, the silicon adapter plate is not directly contacted with the fixture body made of metal or high in hardness, the clamping safety is improved, the thickness, the size and the shape of the silicon adapter plate are not limited, and the cracking risk is effectively avoided while the silicon adapter plate is stably held and supported.
Further, set up first annular step that sinks on anchor clamps body one side, set up second annular step that sinks on the opposite side, and, the outer wall coincidence that the ring was placed to the inner wall and the wafer of first annular step that sinks, the inner wall coincidence that the ring was placed to the inner wall and the wafer of second annular step that sinks, through setting up two annular steps that sink, can effectively avoid test fixture to touch test system's needle arm.
Further, evenly set up a plurality of scales on placing the ring circumferencial direction along the wafer on the anchor clamps body, be convenient for fix a position the silicon keysets of treating the centre gripping.
Furthermore, a plurality of handles are arranged on the clamp body, so that the test clamp can be conveniently taken and placed.
Furthermore, the lateral walls of the two ends of the cavity are inclined inwards to play a limiting role, so that the silica gel pad can be effectively prevented from falling out.
According to the testing method, the placing position and the testing scheme of the silicon adapter plate to be tested are determined through the shape of the testing points on the silicon adapter plate to be tested, the coordinates of the testing points and the testing point network, the silicon adapter plate to be tested is loaded on the testing clamp according to the placing position, and the testing is carried out according to the testing scheme to obtain the testing result. The silicon adapter plate is stably held and supported by the test fixture, so that a stable environment is provided for testing; meanwhile, a direct test mode is adopted, light and reliable contact is guaranteed in the test process, product damage is avoided, post-process processing is not influenced, the silicon adapter plate is one of ideal solutions for realizing heterogeneous and heterogeneous integration, the method lays a foundation for industrialization of 2.5D advanced packaging silicon adapter plates, and has very wide application prospect and market potential and important strategic significance and social benefit.
Furthermore, by combining a resistance method and an electric field method, all the pads and networks on the covered silicon adapter plate are tested, potential defects can be identified, product performance and reliability are ensured, test credibility is ensured, yield and sufficiency are considered, and the method is suitable for production test of the silicon adapter plate.
Drawings
FIG. 1 is a schematic view of a stacked structure of a silicon interposer;
FIG. 2 is a schematic diagram of a front structure of an interconnect testing fixture according to an embodiment of the present invention;
FIG. 3 is an enlarged view of the portion A in FIG. 2 according to the present invention;
FIG. 4 is a schematic diagram of a front side structure of an interconnect testing fixture according to an embodiment of the present invention;
FIG. 5 is a flow chart of an interconnection testing method according to an embodiment of the present invention;
FIG. 6 is a schematic view of the distribution of the silicon interposer exposure area on the wafer;
fig. 7 is a schematic diagram illustrating a principle of an open circuit test of a silicon interposer according to an embodiment of the present invention;
fig. 8 is a schematic diagram illustrating a short-circuit testing principle of a silicon interposer according to an embodiment of the present invention.
Wherein: 1-front side bumps; 2-a third insulating medium layer on the front surface; 3-a front second metal wiring layer; 4-a second insulating medium layer on the front surface; 5-a front first metal wiring layer; 6-a first insulating medium layer on the front surface; 7-TSV; 8-a first insulating medium layer on the back; 9-back first metal wiring layer; 10-a second insulating medium layer on the back; 11-backside under bump metallurgy; 12-wafer size; 13-wafer edge area; 14-vacuum connection; 15-wafer placement ring; 16-a cavity; 17-vacuum adsorption grooves; 18-a scale; 19-a first annular sunken step; 20-second annular sunken step.
Detailed Description
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in sequences other than those illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Firstly, referring to fig. 1, a common laminated structure of a silicon interposer is described, wherein a front surface bump 1, a front surface third layer insulating medium layer 2, a front surface second layer metal wiring layer 3, a front surface second layer insulating medium layer 4, a front surface first layer metal wiring layer 5 and a front surface first layer insulating medium layer 6 are arranged on a front surface of the silicon interposer; a first back insulating dielectric layer 8, a first back metal wiring layer 9, a second back insulating dielectric layer 10 and a back Under Bump Metallurgy (UBM) are arranged on the back; the front side of the silicon interposer and the back side of the silicon interposer are connected by TSVs 7.
The interconnection test fixture and the interconnection test method of the silicon adapter plate are not limited to the laminated structure, and are suitable for the silicon adapter plate with TSV7, wherein the front surface and the back surface of the silicon adapter plate are provided with insulating medium layers with the number of layers larger than or equal to 2, and metal wiring layers with the number of layers larger than or equal to 1, and the silicon adapter plate without TSV7, wherein the number of the layers of the metal wiring layers is larger than or equal to 1.
Generally, the thickness of the silicon adapter plate can be as thin as 50 μm, the silicon adapter plate is made of silicon and has the characteristics of thinness, fragility, difficulty in holding and supporting, and the silicon adapter plate has the main function of realizing interconnection or redistribution of chip I/O leads and has the characteristic of front-back surface conduction, so that the test fixture is required to meet the requirement of double-sided test. The invention provides an interconnection test fixture of a silicon adapter plate.
The invention is described in further detail below with reference to the accompanying drawings:
referring to fig. 2 to 4, in an embodiment of the present invention, an interconnection testing fixture for a silicon interposer is provided, including a fixture body and a plurality of silica gel pads, wherein a through hole is formed in the fixture body, a wafer placing ring 15 is disposed on an inner wall of the through hole, a plurality of cavities 16 are disposed on the wafer placing ring 15, and a vacuum adsorption groove 17 and a plurality of mounting holes are formed in the cavities 16; the clamp body is provided with a plurality of vacuum joints 14 communicated with the vacuum adsorption grooves 17; the silica gel pad is provided with a plurality of vacuum holes and a plurality of bulges, the bulges are respectively connected with the mounting holes, and the vacuum holes are communicated with the vacuum adsorption grooves 17.
When the silicon adapter plate is in a use state, the silicon pad is arranged in the cavity 16 and slightly higher than the wafer placing ring 15, the silicon adapter plate is adsorbed through the vacuum holes distributed on the silicon pad, does not directly contact with the clamp body and is not limited by the thickness, size and shape of the silicon adapter plate, and the silicon adapter plate can be stably held and supported, and meanwhile, the risk of splintering can be effectively avoided.
Preferably, a first annular sinking step 19 is formed on one side of the clamp body, a second annular sinking step 20 is formed on the other side of the clamp body, the inner wall of the first annular sinking step 19 coincides with the outer wall of the wafer placing ring 15, and the inner wall of the second annular sinking step 20 coincides with the inner wall of the wafer placing ring 15. By arranging the two annular sinking steps, the test fixture can be effectively prevented from touching the needle arm of the test system.
Preferably, a plurality of scales 18 are uniformly arranged on the clamp body along the circumferential direction of the wafer placing ring 15. In this embodiment, four scales 18 are provided, which are respectively located at the upper, lower, left, and right positions of the fixture body, and are used for positioning the silicon interposer to be clamped.
Preferably, a plurality of handles are arranged on the clamp body. In this embodiment, set up the symmetry in command on the both sides of anchor clamps body, be convenient for test fixture get and put.
Preferably, both side walls of the cavity 16 are inclined inward, that is, the cavity 16 is designed with a top closed-up. Such design can play fine limiting displacement, can effectively prevent that inside silica gel pad from falling out.
The interconnection test content of the silicon adapter plate comprises a network connectivity test and an isolation test between networks, and open circuit and short circuit/leakage faults are detected respectively; the interconnection test of the silicon adapter plate is a contact test, the larger the wafer size is, the more obvious the shaking is, the smaller the bump size on the front side is to 15 microns, the smaller the center distance is to 30 microns, the contact is difficult, and the test pressure and the test speed must be controlled well in the process; meanwhile, the silicon adapter plate has a large number of microstructures, TSV is manufactured by a through Via (Via Last) process, the minimum diameter reaches 5 micrometers, the depth-width ratio reaches 20:1, the TSV has an MOS effect, the minimum line width/line spacing of a metal wiring layer reaches 5 micrometers/5 micrometers, potential defects are prone to being generated, the silicon adapter plate interconnection test judgment standard is not clear by the combination of a resistance method and an electric field method, the judgment threshold value of open-circuit and short-circuit tests can be defined by combining the characteristics of a silicon adapter plate product, and then open-circuit and short-circuit tests are achieved.
In particular, referring to fig. 5, in another embodiment of the present invention, a method for testing interconnection of a silicon interposer is provided, which includes the following steps. In this embodiment, a high-speed probe station is taken as a test system, and a silicon interposer to be tested is a 12-inch thin wafer (about 250 μm thick).
S1: and acquiring the shape of a measuring point, the coordinate of the measuring point and a measuring point network on the silicon adapter plate to be measured.
Specifically, reading in design data of the silicon adapter plate, performing layer definition according to the characteristics of the silicon adapter plate to be detected, checking each layer of circuit one by one, and confirming the positive and negative films of the circuit; aligning the inter-layer Via and TSV with the outer layer circuit; generating a test point; setting a reasonable adjacent distance value and network resolution according to the line width and line distance of the silicon adapter plate product to generate a correct test network, so as to ensure that test missing cannot be caused; an outer frame is arranged.
And finally outputting test data, wherein the specific contents comprise the shapes of the test points, the coordinates of the test points and the test point networks, including the relationship among the test point networks.
S2: setting the placing position of the silicon adapter plate according to the shape of the measuring point on the silicon adapter plate to be measured, the measuring point coordinate and the measuring point network, and loading the silicon adapter plate to be measured on the interconnection test fixture according to the placing position.
The test data is read in. Editing a test point of a silicon adapter plate to be tested; obtaining a distribution schematic diagram of a silicon adapter plate exposure area on a wafer, and typesetting as shown in FIG. 6; setting and optimizing the placement position of the silicon adapter plate; scanning points are arranged on the upper layer (Top) and the lower layer (Bottom) of the silicon adapter plate and are used for alignment before testing.
Setting the placing position of the silicon adapter plate, loading the silicon adapter plate to be tested on the interconnection test fixture according to the placing position, specifically, setting scanning points on both sides of the silicon adapter plate to be tested, loading the silicon adapter plate to be tested on the interconnection test fixture according to the placing position based on the scanning points and the scale 18 on the interconnection test fixture, and then integrally moving into the ideal position of the test system.
S3: and obtaining an open circuit test scheme and a short circuit test scheme of each test point network according to the distribution of the test point networks on the silicon adapter plate to be tested, and testing according to the open circuit test scheme and the short circuit test scheme.
The method comprises the following steps of setting the largest measuring point network on a silicon adapter plate to be measured as an antenna network, and when the coverage rate of the antenna network is greater than a preset threshold value, determining that the short circuit test scheme of each measuring point network is as follows: acquiring a measuring point network of a suspected short circuit by adopting an electric field short circuit testing method, and testing the measuring point network of the suspected short circuit by adopting a resistance method; otherwise, determining the short circuit test scheme of each test point network as follows: adopting a proximity distance method to obtain a measuring point network of a suspected short circuit, and testing the measuring point network of the suspected short circuit by a resistance method; the open circuit test scheme can select an electric field method open circuit test method and/or a resistance method open circuit test method.
The open circuit and short circuit test of the silicon adapter plate can obviously find defects by a resistance method based on ohm law (R ═ V/I) and also by detecting the change of capacitance or complex impedance value of one test network relative to another normal network by an electric field method. The electric field method can reduce the number of times or positions of contact, greatly improve the test efficiency, but may cause test escape.
Specifically, referring to fig. 7, the open circuit test scheme may select an electric field open circuit test method and/or a resistance open circuit test method, wherein the electric field open circuit test method simultaneously contacts two bumps of the same test network N0 through probes, and if there is no open circuit, a small resistance should be measured, and if there is an open circuit, a very large resistance value is obtained. According to the resistance method open circuit testing method, each testing network has a capacitance value relative to the antenna network, if the testing network is not open, the capacitance values measured by all testing points on the same testing network relative to the antenna network are the same, and if the testing network is open, the capacitance values are different.
Specifically, referring to fig. 8, in the present embodiment, the largest network (in the embodiment, the selected network) in the silicon interposer is set as the electric field signal reference point, i.e., the antenna network. The electric field method short circuit test method is that an electric field method applies signal excitation to an antenna network N1 through a probe contact, the antenna network N1 is the largest network on a silicon adapter plate, usually a power supply or a ground network, other probes are used for contacting a test network N2, a test network N3, a test network N4 and a test network N5, the amplitude and the phase of induction signals are calculated and analyzed, different test networks are usually different, the same or similar test networks are marked as suspicious short circuits, if the suspicious short circuits can be confirmed through a resistance method short circuit test method, for example, the resistance is 0 when the short circuits. When a suspected short circuit is obtained by the proximity distance method, the nearest distance between each test network and the adjacent test network is calculated, and if the nearest distance is smaller than a set proximity distance parameter, the nearest distance is listed in a network list file which needs to be in a short circuit relation with the network test, namely, a suspected short circuit test point network, for example: if the gap between test network N6 and test network N7 is greater than the proximity parameter, then no testing is required between test network N6 and test network N7. If the test network N8 is separated from the test network N10 by a distance parameter less than the proximity parameter and is segmented by the test network N9, no testing is required between the test network N8 and the test network N10 and no testing is required for a possible short between the layers.
And finishing the compiling operation according to the determined test scheme, wherein the specific results obtained after compiling are as follows: antenna files, scan files, net list files, proximity distance files, pad files, and the like.
Wherein, preferably, before testing, the correctness and precision of the voltage/current/capacitance excitation and detection of the test system, i.e. the high-speed probe station, are verified by the calibration board. During testing, a test program is loaded, test parameters are set, the test method is selected, test conditions, a test threshold value, test contact pressure, test speed and the like are set, and testing is performed according to the set test parameters.
Preferably, after the test, retesting is performed on the test point network with the open circuit fault so as to ensure the accuracy of the result.
S4: and outputting a test result, and unloading the silicon adapter plate to be tested.
Specifically, the output test result mainly includes a wafer map and an abnormal value. And drawing a wafer map according to the test pass/fail of each silicon adapter plate based on typesetting. The silicon adapter plate test pass/fail depends on a decision threshold, and an abnormal value is an actual value aiming at open circuit or short circuit faults. And then unloading the silicon adapter plate, unloading the silicon adapter plate after the test is quitted, and preparing the test of the next silicon adapter plate.
In another embodiment of the present invention, taking a tested silicon interposer as an example, the dimensions: 22mm × 22mm, number of single-chip test points: 6150, front points: 4301, counting the number of the back sides: 1849, number of monolithic networks: 662. by adopting the interconnection testing method of the silicon adapter plate, the time consumed for testing 1 silicon adapter plate is 15min4.2s, and no needle mark is observed under the condition of 10 times of magnification of a microscope.
In summary, the interconnection testing method of the silicon interposer in the invention adopts a direct testing mode, ensures light and reliable contact in the testing process, does not cause product damage and does not influence post-process processing, and tests all pads and networks covering the silicon interposer by combining a resistance method and an electric field method, so that potential defects can be identified, product performance and reliability are ensured, testing credibility is ensured, yield and sufficiency are considered, and the method is suitable for production testing of the silicon interposer. The silicon adapter plate is one of ideal solutions for realizing heterogeneous and heterogeneous integration, the invention lays a foundation for industrialization of 2.5D advanced packaging silicon adapter plates, has very wide application prospect and market potential, and has important strategic significance and social benefit.
The above-mentioned contents are only for illustrating the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and any modification made on the basis of the technical idea of the present invention falls within the protection scope of the claims of the present invention.
Claims (10)
1. The interconnection test fixture for the silicon adapter plate is characterized by comprising a fixture body and a plurality of silica gel pads, wherein the fixture body is provided with a through hole, the inner wall of the through hole is provided with a wafer placing ring (15), the wafer placing ring (15) is provided with a plurality of cavities (16), and the cavities (16) are provided with vacuum adsorption grooves (17) and a plurality of mounting holes;
the clamp body is provided with a plurality of vacuum joints (14) communicated with the vacuum adsorption grooves (17);
the silica gel pad is provided with a plurality of vacuum holes and a plurality of bulges, the bulges are respectively connected with the mounting holes, and the vacuum holes are communicated with the vacuum adsorption grooves (17).
2. The interconnection test fixture of silicon interposer as claimed in claim 1, wherein the fixture body has a first annular sinking step (19) formed on one side thereof and a second annular sinking step (20) formed on the other side thereof, and wherein an inner wall of the first annular sinking step (19) coincides with an outer wall of the wafer placing ring (15) and an inner wall of the second annular sinking step (20) coincides with an inner wall of the wafer placing ring (15).
3. The interconnection test fixture of silicon interposer as claimed in claim 1, wherein the fixture body has a plurality of scales (18) uniformly arranged along a circumferential direction of the wafer placing ring (15).
4. The interconnected test fixture of silicon interposer as recited in claim 1, wherein the fixture body has a plurality of handles disposed thereon.
5. The silicon interposer interconnect test fixture of claim 1, wherein both end sidewalls of the cavity (16) are inwardly sloped.
6. An interconnection testing method of a silicon interposer is characterized by comprising the following steps:
s1: acquiring the shape, coordinates and network of a measuring point on a silicon adapter plate to be measured;
s2: setting the placing position of the silicon adapter plate according to the shape of a measuring point, the measuring point coordinate and the measuring point network on the silicon adapter plate to be measured, and loading the silicon adapter plate to be measured on the test fixture of claim 1 according to the placing position;
s3: obtaining an open circuit test scheme and a short circuit test scheme of each test point network according to the distribution of the test point networks on the silicon adapter plate to be tested, and testing according to the open circuit test scheme and the short circuit test scheme;
s4: and outputting a test result, and unloading the silicon adapter plate to be tested.
7. The interconnection testing method of the silicon interposer as claimed in claim 6, wherein the specific method for loading the silicon interposer to be tested on the interconnection testing jig according to the placement position in S2 is as follows:
scanning points are arranged on two sides of the silicon adapter plate to be tested, and the silicon adapter plate to be tested is loaded on the interconnection test fixture according to the placing position based on the scanning points and the scale (18) on the interconnection test fixture.
8. The interconnection testing method of the silicon interposer as claimed in claim 6, wherein the short circuit testing scheme in S3 is obtained as follows:
setting the largest measuring point network on the silicon adapter plate to be measured as an antenna network, and when the coverage rate of the antenna network is greater than a preset threshold value, determining that the short circuit test scheme of each measuring point network is as follows: acquiring a measuring point network of a suspected short circuit by adopting an electric field short circuit testing method, and testing the measuring point network of the suspected short circuit by adopting a resistance method;
otherwise, determining the short circuit test scheme of each test point network as follows: and (3) acquiring a measuring point network of the suspected short circuit by adopting a proximity distance method, and testing the measuring point network of the suspected short circuit by adopting a resistance method.
9. The interconnection testing method of the silicon interposer as claimed in claim 6, wherein the open circuit testing scheme in S3 is an open circuit testing method by an electric field method and/or an open circuit testing method by a resistance method.
10. The interconnection testing method of a silicon interposer as claimed in claim 6, wherein the S4 further comprises: and retesting the measuring point network of the open circuit fault.
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