TWI431278B - Semiconductor test probe card space transformer - Google Patents

Description

Semiconductor test probe card space converter manufacturing method

The present invention relates to semiconductors, and more particularly to probe cards for testing integrated circuits formed on a semiconductor wafer.

The fabrication of modern semiconductors involves a number of steps with lithography, material deposition, and etching to form a plurality of individual semiconductor devices or integrated circuit wafers on a single semiconductor germanium wafer. The commonly used semiconductor wafers currently available can be six or more diapers in diameter, with wafers having a diameter of twelve turns being a common size. However, some individual wafers formed on the above wafers may have some drawbacks due to variations or problems that may occur in the fabrication of complex semiconductor fabrication processes. Before the wafer is diced to separate the integrated circuit wafer from the semiconductor wafer, electrical performance and reliability of the plurality of wafers are tested and simultaneously excited during a predetermined period (eg, wafer level burn-in) test). These tests may typically include layout versus schematic (LVS) acknowledgments, IDDq testing, and so on. The resulting electrical signal from each wafer or device under test (DUT) is captured and analyzed by an automatic test equipment (ATE) with test circuitry to determine if a wafer has defect.

To aid in wafer-level burn-in testing and simultaneous capture of electrical signals from multiple wafers on a wafer, conventional DUT boards or probe cards are used. The probe card is essentially a printed circuit board (PCB), and includes a plurality of metal electrical probes for a plurality of corresponding electrical contacts of the semiconductor wafer formed on the wafer (contact) or terminal. Each wafer has a plurality of contacts or connectors, each of which must be accessed for testing. Therefore, typical wafer level testing requires electrical connections between more than 1000 wafer contacts or connectors and ATE test circuitry.

Therefore, in order to perform accurate wafer level testing, it is important to accurately align a large number of probe card contacts with the wafer contacts on the wafer and form a positive electrical connection. The probe card is usually mounted in the above-described automatic test equipment and serves as an interface between the above-mentioned wafer or the device under test and the above-mentioned automatic test equipment.

As semiconductor process technology continues to evolve, the spacing or spacing between the electrical test contact pads of the wafers on the semiconductor wafer continues to shrink. As shown in FIG. 1, it is illustratively shown that a next-generation semiconductor wafer or device under test is visible on a wafer, and the test pad pitch is satisfactorily reduced to 50 microns or less. The distance between the test device test pads 110 may be greater than the spacing between the through silicon vias (TSV) contact pads 120 on the device under test connected via the connection lines 130, and in some examples may be 17 Micron. However, the technical bottleneck that occurs with existing test probe card designs is that they cannot support such small test pad spacing.

Known probe cards have a multilayer interconnect substrate or space transformer that is a test printed circuit board and probe (eg, a finger probe) placed on a test pad attached to the device under test. Between (fingers), needle probes (needles), etc.). The space transformer transmits an electrical test signal and a power signal between the printed circuit board and the probe. The space transformer generally has a ball grid array (BGA) interconnecting system on one side thereof, which is connected to the test printed circuit board and a C4 (controlled collapse chip connection) interconnecting system. Point-and-match, and the above contact is the first half of the above test. However, the minimum C4 contact pad spacing of these known space transformers is typically about 150 microns, and does not meet the pitch spacing of C4 contact pads of 50 microns or less required to support fine probe spacing.

Therefore, there is a need in the industry for improved test probe card space transformers that have a finer C4 contact pad spacing.

The present invention provides a method of fabricating a semiconductor test probe card space transformer to reduce the pitch distribution of a contact test pad. In one embodiment, the method includes providing a space transformer having a base at the bottom and a plurality of first contact test pads on one side thereof to perform an electrical test of the device under test, in the first contact Determining a first pitch distribution between the test pads; depositing a first metal layer as a ground plane on the substrate; depositing a first dielectric layer on the ground plane; forming a plurality of second contact test pads, Determining, between the second contact test pads, a second pitch distribution different from the first pitch distribution; and forming a plurality of redistribution pins on the first dielectric layer to test the first contact The pad is electrically connected to the second contact test pad described above. In an embodiment, the first contact test pad is embedded or sealed in a second protective layer.

In another embodiment, a method of fabricating a semiconductor test probe card space transformer includes providing a space transformer having a substrate and a plurality of first test contacts on a first side of the base to perform a The electrical test of the measuring device defines a first pitch distribution between the first test contacts, the first test contact has a plurality of first input/output pads and a plurality of first ground pads; a metal ground plane layer on the first side of the substrate; depositing a first dielectric layer on the metal ground plane layer; patterning the first dielectric layer to form a plurality of recesses therein; filling with a conductive metal And at least a portion of the recesses are formed to form a plurality of redoning pins; and a plurality of second test contacts are formed, and a second pitch distribution smaller than the first pitch distribution is defined between the second test contacts At least a portion of the second test contact is electrically coupled to at least a portion of the first test contact via the repeating pin. In one embodiment, the method further includes a step of encapsulating the first contact test pad therein with a protective layer.

In another embodiment, a method of fabricating a semiconductor test probe card space transformer includes providing a space transformer having a substrate and a plurality of first contact test pads on one side to perform electrical properties of the device under test Testing, a first pitch distribution is defined between the first contact test pads; a plurality of second contact test pads are formed on the substrate, and the second contact test pads are defined to be different from the first pitch distribution a second pitch distribution; and forming a plurality of redistribution pins to electrically connect the first contact test pad to the second contact test pad. In one embodiment, the method further includes encapsulating the first contact test pad and the second contact test pad therein with a protective layer. Preferably, the method comprises forming a plurality of conductor well channels extending through the protective layer to extend the second contact test pad to an exposed surface of the protective layer to form electrical contact with the plurality of test card probes, Used for wafer level testing of integrated circuit chips.

According to another aspect of the present invention, a finished semiconductor test probe card space transformer having a fine contact test pad pitch distribution includes: a substrate having a first side and a second side; a plurality of first The contact test pad is embedded in the substrate on the first side and the second side; and the plurality of second contact test pads are on the first side. In a preferred embodiment, the pitch distribution of the second contact test pads is smaller than the pitch distribution of the first contact test pads. In another embodiment, the space transformer has a plurality of redistribution pins electrically connected to at least some of the second contact test pads and the embedded first contact test pads. In still another embodiment, the substrate has a protective layer covering the first contact test pad.

In another embodiment, a method of fabricating a semiconductor test probe card space transformer to reduce a pitch distribution of a contact test pad includes: providing a substrate having a plurality of first contact tests on an upper surface of the substrate The pad is configured to perform an electrical test of the device under test, and a plurality of metal planes, and a first pitch distribution is defined between the first contact test pads, wherein the metal plane surrounds each of the first contact test pads and Each of the first contact test pads is electrically isolated, the metal plane is grounded as a ground plane; a first dielectric layer is deposited on the upper surface of the substrate, and the first test pad is exposed; a plurality of weights are formed The cloth pins are electrically connected to the first contact test pads on the first dielectric layer, and each of the redistributable pins is located between an end of the first dielectric layer, and the definition is different from the above A second pitch distribution of the first pitch distribution.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

An exemplary embodiment shown in FIG. 2 is a commercially available test probe card 200 having a spatial converter 240 having a fine pitch, which has been modified by the method proposed by the present invention. C4 contact pad array. Test probe card 200 can be any suitable commercially available test probe card such as, but not limited to, Cobra with needle probe from Wentworth Laboratories, Inc. of Brookfield, CT. Card, or available from FormFactor Of Livermore, CA obtained with MicroSpring Probe card for needle probes. Preferably, the probe card is selected from the test pads 110 having the same spacing or spacing on the device under test (see FIG. 1). Hehe.

Referring to FIG. 2, the test probe card 200 has a test printed circuit board 210 having an upper surface 212 and a lower surface 214, a mounting ring 220 adhered thereto, and supported by the mounting ring 220. A test probe head 260, and a space transformer 240. In one embodiment, the test probe head 260 has a plurality of commercially available test probes 230, which may be of any suitable type or architecture, such as a needle or pin, in a model or architecture An appropriate pitch distribution can be provided in embodiments to support test pad spacing of 50 microns or less. Each of the test probes 230 has a lower end point, and the structure or arrangement of the lower end points is used to match a corresponding test pad 252 on a device under test 250 to be tested. Test probe 230 preferably having a pitch P _N, P _N is the pitch measured on the test apparatus 250 by the pitch of the pads 252 P _T matchmaking. In an exemplary embodiment, the values of the pitches P _T and P _N may be about 50 microns.

With continued reference to FIG. 2, in one possible embodiment, each test probe 230 can each have an upper half 234 that is a penetrating intermediate probe holder within the test probe head 260. Supported by 232. The material of the transmissive intermediate probe holder 232 is preferably a non-conducting material such as polyamide mylar. The upper half 234 of each test probe 230 can extend to an enlarged contact end 236 of the uppermost portion to mate with a corresponding contact on the space transformer 240. In some embodiments, the test probe head 260 can further include a lower substrate 226, an upper substrate 222, and a spacer 224. As shown in FIG. 2, the extension of the test probe 230 is guided by the lower substrate 226. And passing through the lower substrate 226, the upper substrate 222 is configured to receive the upper half 234 of the probe and the enlarged contact end 236, and the spacer 224 is interposed between the lower substrate 226 and the upper substrate 222. The enlarged contact end 236 preferably extends through the upper substrate 222 for connection to a contact pad on the space transformer 240. The application of the present invention is not limited to the architecture or features of the test probe head 260 described herein, and the support structure of the test probe 230 of any other architecture may be provided and used.

In some embodiments, the bottom of the space transformer 240 can be a multi-layered organic (MLO) or multi-layered ceramic interconnect substrate 245. The space transformer 240 has a C4 side 400 and an opposite facing ball gate array side 402. The C4 side 400 has a lower surface 241 having a fine pitch contact test pad array 242 for use with the test probe head 260. The upper enlarged contact end 236 is engaged and meshed; the opposite side of the ball gate array side 402 has an upper surface 243 having an array of ball gates for testing the corresponding contact pads 211 on the printed circuit board 210. Match. The ball grid array may have a pitch P _B defined as a spacing between the spheroids, and the spheroid may be made of soft solder or other suitable material.

Next, referring to Figures 3 to 14, a first embodiment of the manufacturing flow of the method of modifying a commercially available test probe card 200, which is proposed by the present invention, will be sequentially described to manufacture a C4 having a fine pitch. A space transformer 240 of the contact pad array. The position of the space transformer 240 shown in Figs. 3 to 14 is the reverse position opposite thereto, as compared with the normal operation position when the space transformer 240 is mounted on a test machine shown in Figs. 2 and 15. Unless otherwise indicated, the various lithography, material deposition, and material removal processes described below can be made with reference to known processes conventionally used in microelectromechanical or semiconductor fabrication.

Referring to FIG. 3, a space transformer 240 is provided having an array of original C4 contact pads 410 formed on an interconnect substrate 245. In some embodiments, the interconnect substrate 245 can be a multilayer organic or multilayer ceramic substrate. In one embodiment, the existing C4 contact pad array 410 having an original pitch of about 150 microns between the distribution P _O contact pad. First, the lower surface 241 and the upper surface 243 are cleaned by ultrasonic waves so that the above surface is in a state in which the conductor material can be received.

In the next step shown in FIG. 4, a metal conductor 300, for example, in one embodiment, a copper layer is deposited on the opposite side of the ball gate array side 402 and on the space transformer 240 by sputtering. The surface 243 is such that each conductor channel 301 is electrically connected or shorted to each other. In some embodiments, the metal conductor 300 can be subsequently etched by conventional techniques to produce a conductor path having the desired pattern. Further, as shown, a metal conductor, such as copper in one embodiment, is deposited on the C4 side 400 and overlies the original C4 contact pad array 410 by a coating process such that the C4 contact pads conform to the lower surface 241. The height of the interconnect substrate 245 of the upper space transformer 240. As shown in FIG. 4, this step constructs the original plurality of C4 grounding (GND) test pads 303 and a plurality of C4 input/output (I/O) test pads 304.

Referring to FIG. 5, in some embodiments, a metal such as copper is deposited on the upper and lower surfaces 241 of the lower surface 241 to form a ground plane 302 for impedance control for high frequency 50 ohm testing. For example, a known known good die (KGD) test. In FIG. 6, a conventional lithography and etching step is applied to the ground plane 302 to isolate the input/output test pad 304 by establishing a gap 305 around the input/output test pad 304 as shown. . The above etching step can be carried out by any conventional process for the manufacture of microelectromechanical or semiconductor, for example, by wet etching.

Referring to FIG. 7, a first dielectric layer 310 is coated or deposited on the C4 or lower surface 241 and covers the ground plane 302 by any suitable conventional process for the fabrication of microelectromechanical or semiconductor. The first dielectric layer 310 is preferably an electrically insulating material to isolate active components and leads formed in the interconnect substrate 245. In a preferred embodiment, the first dielectric layer 310 may be a polyimide light resistor or an epoxy-based photoresist such as SU-8 light available from MicroChem Corporation of Newton, MA. Resistance, however, other suitable photoresists can be used.

Referring to FIG. 8, the first dielectric layer 310 is placed on the C4 ground test pad 303 and the C4 input/output test pad by conventional lithography and related photoresist removal processes such as ashing. The portion above 304 is removed, and the C4 ground test pad 303 and the C4 input/output test pad 304 are opened to expose them. In addition, a plurality of openings 311 are formed in the first dielectric layer 310 to expose a portion of the ground plane 302 for subsequent formation of a plurality of new C4 ground contacts 350 (see, for example, FIG. 14).

Referring to FIG. 9, a second conductive metal layer 320, such as preferably copper, is deposited on the C4 side 400 including the ground plane 302 by sputtering or other suitable means. The second conductor metal layer 320 is used in the subsequent deposition of the conductor metal described later in FIG.

In Fig. 10, a photoresist 330 is applied to the C4 side 400 and patterned by conventional microelectromechanical or semiconductor technology. The patterned photoresist 330 produces a series of recesses 332 for subsequent formation of a redistribution layer (RDL) having conductor redistribution pins 334 (see Figure 12) to change the new from the upcoming formation. The contact test pad array 242 having a finer pitch and the path of the electrical signal of the original, existing contact test pad array having a larger existing pitch. The patterning of the photoresist also retains a plurality of openings therein for the input/output test pads 304, the C4 ground test pads 303, and the new C4 ground contacts 350 (see, for example, Figure 14). In addition, a new recess 335 is formed through the photoresist 330 to expose the second conductor metal layer 320 for subsequent formation of a new input/output contact 352 (see, for example, FIG. 14).

Referring now to FIG. 11, a conductor metal, such as copper in one embodiment, is deposited on the C4 side 400 of the interconnect substrate 245 by plating, and the open recess 332 is filled. A redistribution layer having a plurality of conductor conductor redistribution pins 334. In one embodiment, the conductor redistribution pins 334 are preferably wound on the first dielectric layer 310 to connect the new contact test pad array 242 to the original C4 contact pad array 410. The top view shown in Figure 16 (actually the redistribution layer is connected to and connected between, for example, the input/output test pad 304 and the C4 ground test pad 303, with the corresponding new C4 ground contact 350 and the new input Between the output contacts 352, the above situation is not shown in the cross-sectional view for the sake of brevity. The metal deposition process illustrated in FIG. 11 also fills the recesses in the photoresist 330 associated with the input/output test pads 304 and C4 ground test pads 303, the new C4 ground contacts 350, and the new input/output contacts 352. The input/output test pad 304 and the C4 ground test pad 303 are completed in this step. However, this step simply establishes a copper substrate for the new C4 ground contact 350 and the new input/output contact 352, which will be completed in a subsequent step.

Referring to FIG. 12, next, as shown, the photoresist 330 is removed leaving an input/output test pad 304, a C4 ground test pad 303, a new C4 ground contact 350, and a new input/output contact. 352. Re-spin 334 with the conductor. Any conventional photoresist removal process can be used, such as using dry plasma gas ashing/etching, or a liquid solvent such as acetone. In addition to removing the photoresist 330, it is preferred to continue etching after the removal of the photoresist 330 is completed to etch back and remove portions of the second conductor metal layer 320 under the photoresist 330. As such, the first dielectric layer 310 between the conductor redistribution pins 334 and between the input/output test pads 304 and the C4 ground test pads 303 is exposed. The first dielectric layer 310 is preferably selected from materials having electrical insulator properties to electrically isolate the conductor redistribution pins 334 and the new input/output contacts 352 to the ground plane 302 as shown. After the etch back step described above, only a portion of the second conductive metal layer 320 remains between the conductor ground plane 302 and the metal layer deposited in the step shown in FIG. 11 to form a new conductor re-arrangement. Feet 334.

Referring to Figure 13, a protective layer 340 is deposited or coated on the C4 side 400 of the interconnect substrate 245 as shown. In some embodiments, the protective layer 340 is preferably formed of a dielectric material. The protective layer 340 is preferably an electrically insulating material to isolate active components and leads formed in the interconnect substrate 245. In one embodiment, the material of the protective layer 340 is preferably a photoresist material, more preferably an epoxy resin-based photoresist, such as SU-8 light available from MicroChem Corporation of Newton, MA. Resistance. However, other suitable protective layer materials and dielectrics can also be used. The lithography process is then preferably performed to pattern the protective layer 340 and form a plurality of recess openings 342 exposing the new C4 ground contacts 350 and the new input/output contacts 352.

Referring to Figure 14, a conductor metal is plated and filled into the recess opening 342 to form a plurality of well channels 351 that establish a new C4 ground contact 350 with the new input/output contact 352 to at least protect A second surface of layer 340, and in some embodiments is preferably slightly above the surface. In an exemplary embodiment, the conductor material for the well channel 351 may be NiCo (nickel cobalt), which is of a good hardness. The nickel-cobalt well channel 351 is plated on a previously established copper substrate, please refer to the description of Figure 11 above. In a preferred embodiment, gold is plated on the top end portion of the well channel 351 to form a new C4 ground contact 350 with the top contact surface 353 of the new input/output contact 352 to provide good conduction. Sex and corrosion resistance. The top contact surface 353 defines a fine pitch C4 contact test pad array 242 to engage and match the enlarged contact end 236 of the test probe head 260. Other suitable conductor metals and alloys may also be used to form the well channel 351 and the tip contact surface 353. In addition, other suitable conductor metals and alloys may be used in place of the exemplary materials recited in any of the foregoing process steps.

The reconstructed and modified spatial transducer 240 is shown in FIG. The spacing between the new C4 ground contact 350 and the new input/output contact 352 is a new fine pitch C4 contact test pad array 242 to engage and amplify the amplified contact end 236 of the test probe head 260. Hehe. C4 and the original with the original input pitch P _O / output pad 304 to the original test C4 ground test pads 303 defined by the original C4 pad, the new test pad contacting a C4 array 242 is preferably less than the pitch P The pitch of _O is P _O4 . In certain embodiments, the pitch P _{O4 is} preferably 50 microns or less. The original pitch P _{B of the} ball gate array 244 may remain on the opposite side of the C4 contact test pad array 242, that is, the opposite side of the ball gate array side 402. Moreover, the exemplary methods described herein still retain all of the internal lines or other conductor path traces in the interconnect substrate 245, such as a representative single trace 360 of FIG. 15 for clarity of display. Therefore, the pitch P _{B of} the ball gate array 244 is still compatible with the pitch P _BGA of the contact pads 211 on the test printed circuit board 210 (shown in FIG. 2). Please note that the C4 input/output test pad 304 and the C4 ground test pad 303 are embedded or sealed in the interconnect substrate 245 by the second protective layer 340 shown in FIG. 15 and can be separated by a single trace 360. The ball gate array side 402, which is electrically connected to the opposite side, is rewired by a conductor 334 and electrically coupled to the C4 side 400 via a new contact test pad array 242.

Figure 16 is a top plan view showing the C4 side 400 of the modified space transformer 240 depicted in Figure 15. The second protective layer 340 is removed from FIG. 16 to facilitate display of the contacts of the pre-existing original C4 contact pad array 410. As shown, the pitch P _C4 of the new C4 contact test pad array 242 in a preferred embodiment can be less than the pitch P _{O of the} original C4 contact test pad array 242. As shown, the new contact test pad array 242 is electrically connected to the original with the C4 input/output test pad 304 and the C4 ground test pad 303 by a new redistribution layer with conductor redistribution pins 334. C4 contact pad array 410.

In an alternative method and a modified space converter embodiment, the ground plane 302 shown in FIG. 5 or the first dielectric layer 311 shown in FIG. 7 may not be used, but the above has The new redistribution layer of the conductor redistribution pin 334 is directly established on the interconnect substrate 245 of the space transformer. This method also eliminates the need for the step of isolating the C4 input/output test pad 304 from the ground plane 302 as shown in FIG. In this alternative embodiment, after the steps shown in FIG. 4 described elsewhere in this specification, the coated photoresist layer 330 shown in FIG. 10 is then formed on the C4 side 400 and patterned. a step of forming a plurality of recesses 332 for forming a new redistribution layer having a plurality of conductor redistribution pins 334 electrically connected to the original C4 contact pad array 410 to the fifteenth A new fine pitch contact test pad array 242 is shown in FIG. Then, the steps shown in Figs. 11 to 14 described elsewhere in this specification are completed. Thereby, a conductor redistribution pin 334 is formed, which is electrically connected to the original C4 input/output test pad 304 by a new input/output contact 352, and is electrically connected to the original by a new C4 ground contact 350. C4 ground test pad 303. The appearance of the modified or reworked space transformer formed by this alternative method will be substantially as shown in Figures 15 and 16, but without the ground plane 320 and the first dielectric layer 310.

Next, referring to Figures 17 to 23, a second embodiment of the manufacturing flow of the method of modifying a commercially available test probe card 200, which is proposed in the prior art, will be sequentially described to manufacture a C4 having a fine pitch. A space transformer 540 (shown in Figure 23) of the contact pad array is substituted for the space transformer 240 shown in Figures 2 and 15. The position of the space transformer 540 shown in Figs. 17 to 23 is the reverse position opposite thereto, as compared with the normal operation position when the space transformer 240 is mounted on a test machine shown in Figs. 2 and 15. Unless otherwise indicated, the various lithography, material deposition, and material removal processes described below can be made with reference to known processes conventionally used in microelectromechanical or semiconductor fabrication.

Referring to Figure 17, an interconnect substrate 545 is provided having an original existing C4 contact pad array 710 on its upper surface 541 and a plurality of contact pads 601 on its lower surface 543. The plurality of contact test pads 603 and the contact pads 601 of the C4 contact pad array 710 are electrically connected by a plurality of conductor vias 660, respectively. In this embodiment, the conductor via 660 is formed by a multilayer circuit layer between the lower surface 543 and the upper surface 541 and a connecting conductor electrically connected between the circuits of the layers; in another embodiment, the interconnect substrate 545 has only two conductive layers on the lower surface 543 and the upper surface 541, respectively, and the conductor via 660 directly penetrates between the lower surface 543 and the upper surface 541. In addition, the upper surface 541 of the interconnect substrate 545 further has a plurality of metal planes 604 respectively surrounding each of the contact test pads 603 and electrically isolated from each contact test pad 603. The metal plane 604 is grounded as a ground plane. . In some embodiments, the interconnect substrate 545 can be a multilayer organic or multilayer ceramic substrate. In one embodiment, the C4 existing array of contact pads 710 having an original pitch of about 150 microns between the distribution P _O contact pads 604. First, the upper surface 541 and the lower surface 543 are cleaned by ultrasonic waves so that the surface is in a state of being able to receive other layers of materials laminated thereon.

Referring to Figure 18, in a next step, a first dielectric layer 610 is coated, adhered or deposited onto the upper surface 541 by any suitable conventional process for the fabrication of microelectromechanical or semiconductor, and is covered with a metal. Plane 604. The first dielectric layer 610 is preferably an electrically insulating material to isolate active components and leads formed in the interconnect substrate 545. In a preferred embodiment, the first dielectric layer 610 may be a polyimide layer having a photosensitive property, a polyimide layer or an epoxy-based layer, such as available from MicroChem Corporation of Newton. SU-8 has a photosensitive film of SU-8, but other suitable films having photosensitive properties or dielectric films having no photosensitive properties can also be used.

The first dielectric layer 610 is then patterned to expose the contact test pads 603. If the first dielectric layer 610 itself has photosensitive properties, the corresponding photomask can be directly used for exposure and development to complete the patterning; if the first dielectric layer 610 itself does not have photosensitive properties, a light can be formed thereon. The resist layer is patterned by conventional lithography, etching, and the like.

In the next step shown in Fig. 19, a metal conductor 600 and a seed layer 620, for example, copper in one embodiment, are deposited on the lower surface 543 of the interconnect substrate 545, respectively, by sputtering. The first dielectric layer 610 of the upper and upper surfaces 541 and the exposed contact test pads 603 are such that each contact pad 601 is electrically connected or short-circuited to each other, and each contact test pad 603 is electrically connected or short-circuited to each other to Subsequent metal deposition process.

Referring next to Figure 19, a photoresist 630 is applied to the seed layer 620 and patterned by conventional microelectromechanical or semiconductor techniques. The patterned photoresist 330 produces a series of recesses 632 for subsequent formation of a redistribution layer (RDL) having conductor redistribution pins 634 (see Figure 20) to change the new from the upcoming formation. The contact test pad array 542 (see FIG. 23) with a finer pitch and the path of the electrical signal of the original, existing contact test pad array having a larger existing pitch. Wherein, the seed layer 620 deposited directly above the contact test pad 603 is preferably at least partially located within the range of the recess 632.

Referring now to FIG. 20, a conductor metal, such as copper in one embodiment, is deposited in a recess 632 to form a plurality of conductor conductor redistributable pins 634 by plating, such as electroplating. A layer of cloth. In one embodiment, each of the conductor redistribution pins 634 is preferably wound on the first dielectric layer 610 such that one end thereof is electrically connected to the corresponding contact test pad 603 via the seed layer 620. The other end point 635 extends onto the first dielectric layer 610. At this time, the pitch of each end point 635 is distributed to have a pitch P _C4 different from the pitch P _O . In the present embodiment, the pitch P _C4 is smaller than the pitch P _O .

Next, referring to FIG. 21, the photoresist 630 is removed leaving the conductor redistribution pin 634 and its end point 635 on the first dielectric layer 610. Any conventional photoresist removal process can be used, such as using dry plasma gas ashing/etching, or a liquid solvent such as acetone. In addition to removing the photoresist 630, it is preferred to continue etching after the removal of the photoresist 630 to etch back and remove the seed layer 620 other than the conductor redistribution pins 634 under the photoresist 630. . As such, the first dielectric layer 610 other than the conductor redistribution pins 634 is exposed. As shown, the seed layer 620 under the conductor redistribution pin 634 is considered to be part of the conductor redistribution pin 634 and is no longer displayed.

Referring to FIG. 22, a second dielectric layer 640 is deposited or coated on the first dielectric layer 610 and the conductor redistribution pins 634 as shown. In some embodiments, the second dielectric layer 640 can serve as a protective or encapsulation layer to protect components and/or circuit layers inside the interconnect substrate 545 from external contamination and/or corrosion and destructive factors. Invasion. The second dielectric layer 640 is preferably an electrically insulating material to isolate active components and leads formed in the interconnect substrate 545. In one embodiment, the material of the second dielectric layer 640 is preferably a polyimide layer having a photosensitive property, a polyimide layer or a layer based on an epoxy resin, more preferably an epoxy. The photoresist of the resin as a substrate is, for example, SU-8 photoresist available from MicroChem Corporation of Newton, MA. However, other suitable protective layer materials and dielectrics can also be used. The second dielectric layer 640 is then preferably patterned to form a plurality of recess openings 642 that expose the end points 635.

Referring to FIG. 23, a conductor metal is filled into the recess opening 642 and electrically connected to the end point 635 of the conductor redistribution pin 634, respectively, to form a new C4 ground contact 650, and in some embodiments new The C4 ground contact 650 is preferably slightly above the surface. In an exemplary embodiment, the conductor material for the new C4 ground contact 650 may be NiCo (nickel cobalt), which is of a good hardness. Before forming a new C4 ground contact 650, it is preferred to first plate a gold layer on the end 635 exposed to the recess 632. The gold layer can serve as a protective layer for preventing corrosion of the end 635 and/or as a protective layer. The adhesive layer between the end point 635 and the new C4 ground contact 650 provides good conductivity and corrosion resistance. The gold layer and the new C4 ground contact 650 are formed by electroplating, respectively, and the side of the end 635 is immersed in a plating solution (not shown) from the metal located on the lower surface 543 of the interconnect substrate 545. The conductor 600 is connected to a power source (not shown). At this time, the terminal 635 is also electrically connected via the conductor redistributing pin 634, the contact test pad 603, the conductor path 660, the contact pad 601 to the metal conductor 600, and is also connected to the above. The power source becomes a cathode, and the aforementioned metal material can be plated at the end point 635. In addition, other suitable conductor metals and alloys may be used in place of the exemplary materials recited in any of the foregoing process steps. In a subsequent step, the metal conductor 600 can be removed as desired. In an embodiment, the new C4 ground contact 650 is an input/output C4 contact.

The pitch distribution of each new C4 ground contact 650 that has been completed is the same as the pitch P _C4 which is different from the pitch P _O . In the present embodiment, the pitch P _C4 is smaller than the pitch P _O . That is, the new C4 ground contact 650 is a new fine pitch C4 contact test pad array 542 that replaces the C4 contact test pad array 242 shown in FIG. 2 with the amplification of the test probe head 260. The contact end 236 is engaged and meshed. Contacting the original with the original C4 pitch P _O test pads 603 of the original C4 existing array of contact pads 710, the new array of C4 contacting the test pads 242 preferably have a pitch smaller than the pitch P _O P _C4. In certain embodiments, the pitch P _{C4 is} preferably 50 microns or less. A ball gate array (not shown) can be engaged with the contact pads 601 on the lower surface 543 of the interconnect substrate 545, and the original pitch P _{B of} the ball gate array and the contact pads 601 can remain in the C4 contact test pad array 542. Opposite side. Moreover, the exemplary method described herein still retains all internal lines or other conductor path traces in the interconnect substrate 545, thus still maintaining the pitch P _{B of} the ball gate array described above with the test printed circuit board 210 (shown in The pitch P _BGA of the contact pads 211 on Fig. 2 is compatible. Although the present invention has been disclosed in the above preferred embodiments, the present invention is not intended to limit the invention, and it is possible to make a few changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

110. . . Test pad 110

120. . .矽through contact pad

130. . . Cable

200. . . Test probe card

210. . . Test printed circuit board

211. . . Contact pad

212. . . Upper surface

214. . . lower surface

220. . . Mounting ring

222. . . Upper substrate

224. . . Spacer

226. . . Lower substrate

230. . . Test probe

232. . . Penetrating intermediate probe holder

234. . . Upper half

236. . . Magnified contact

240. . . Space transformer

241. . . lower surface

242. . . Contact test pad array

243. . . Upper surface

244. . . Ball gate array

245. . . Insulator base

250. . . Device under test

252. . . Test pad

260. . . Test probe head

300. . . Metal conductor

301. . . Conductor channel

302. . . Ground plane

303. . . C4 ground test pad

304. . . Input/output test pad

305. . . gap

310. . . First dielectric layer

311. . . Opening

320. . . Second conductor metal layer

330. . . Photoresist

332. . . Concave

334. . . Conductor redistribution pin

335. . . New recess

340. . . The protective layer

342. . . Concave opening

350. . . New C4 ground contact

351. . . Well channel

352. . . New input/output contacts

353. . . Tip contact surface

360. . . Single trace

400. . . C4 side

402. . . Opposite side of the ball gate array side

410. . . C4 contact pad array

541. . . Upper surface

542. . . C4 contact test pad array

543. . . lower surface

545. . . Insulator base

600. . . Metal conductor

601. . . Contact pad

603. . . Contact test pad

604. . . Metal plane

610. . . First dielectric layer

620. . . Seed layer

630. . . Photoresist

632. . . Concave

634. . . Conductor redistribution pin

635. . . End point

640. . . Second dielectric layer

642. . . Concave opening

650. . . New C4 ground contact

660. . . Conductor path

710. . . C4 contact pad array

P _B . . . spacing

P _BGA . . . spacing

P _C4 . . . spacing

P _N . . . spacing

P _O . . . spacing

P _T . . . spacing

Figure 1 is a top plan view of an exemplary semiconductor device under test, showing the architecture and spacing of the next generation of electrical test pads.

2 is a cross-sectional side view of a test probe card having a space transformer in accordance with an embodiment of the present invention.

Figures 3 through 14 are a series of cross-sectional side views showing the manufacturing flow of the space transformer of the test probe card shown in Figure 2.

Figure 15 is a detailed partial cross-sectional side view of the space transformer of Figure 2.

Figure 16 is an upper plan view of the space transformer of Figure 15, in which a second protective layer of the top end is removed to show the electrical contacts underneath.

17 to 23 are a series of partial cross-sectional side views showing the manufacturing process of the space converter of the test probe card of another embodiment, and the space converter manufactured can replace the test probe shown in FIG. Space converter for the needle card.

240. . . Space transformer

242. . . Contact test pad array

243. . . Upper surface

244. . . Ball gate array

245. . . Insulator base

302. . . Ground plane

303. . . C4 ground test pad

304. . . Input/output test pad

310. . . First dielectric layer

334. . . Conductor redistribution pin

340. . . The protective layer

350. . . New C4 ground contact

352. . . New input/output contacts

400. . . C4 side

402. . . Opposite side of the ball gate array side

P _B . . . spacing

P _C4 . . . spacing

P _O . . . spacing

Claims (28)

A method for fabricating a semiconductor test probe card space transformer to reduce a pitch distribution of a contact test pad, comprising: providing a space transformer having a base at the bottom and a plurality of first contact test pads on the upper portion thereof for execution An electrical test of the device under test defines a first pitch distribution between the adjacent first contact test pads; depositing a first metal layer as a ground plane on the substrate; depositing a first dielectric layer An electrical layer is disposed on the ground plane; a plurality of redistributable pins and a plurality of contacts are formed on the first dielectric layer, wherein an end of the redistributable pins is electrically connected to the first contact tests respectively The other end of the pad is electrically connected to the contacts; a metal is plated on the contacts to form a plurality of top contact surfaces, and a plurality of second contact test pads are defined by the adjacent top contact surfaces And defining a second pitch distribution between the adjacent second contact test pads that is less than the first pitch. The method for manufacturing a semiconductor test probe card space transformer according to claim 1, wherein the first metal layer has a plurality of metal planes, each of which surrounds each of the first contact test pads, And electrically isolated from each of the first contact test pads. The method for manufacturing a semiconductor test probe card space transformer according to claim 1, further comprising sealing the first contact test pads with a protective layer. The method of manufacturing a semiconductor test probe card space transformer according to claim 3, wherein the protective layer is made of a dielectric light The resist material is formed. The method for manufacturing a semiconductor test probe card space transformer according to claim 1, further comprising the step of patterning the first dielectric layer to form a plurality of recesses for subsequently forming the re-distribution The foot and the second contact test pads. The method for manufacturing a semiconductor test probe card space transformer according to claim 5, wherein the redistributing pins and the second contact test pads are formed by depositing a conductor metal In the recess. The method for manufacturing a semiconductor test probe card space transformer according to claim 1, wherein the redistributing pins and the second contact test pads are formed by depositing a second metal layer On the substrate. The method of manufacturing a semiconductor test probe card space transformer according to claim 1, wherein the second contact test pads comprise at least one input/output C4 contact, the input/output C4 contact being isolated from The ground plane is electrically connected to at least one ground contact of the ground plane. A method for fabricating a semiconductor test probe card space transformer to reduce a pitch distribution of a C4 contact test pad, comprising: providing a space transformer having a substrate and a plurality of first test contacts on the substrate The upper surface is configured to perform an electrical test of the device under test, and a first pitch distribution is defined between the first test contacts, and the adjacent first test contacts have a plurality of first input/output pads and a plurality of first ground pads; Depositing a metal ground plane layer on the upper surface of the substrate; depositing a first dielectric layer on the metal ground plane layer; patterning the first dielectric layer to form a plurality of recesses therein; The metal fills at least a portion of the recesses to form a plurality of redoning pins and a plurality of second test contacts, wherein the adjacent second test contacts define a distribution less than the first pitch a second pitch distribution, at least a portion of the second test contacts being electrically connected to at least a portion of the first test contacts via the redistribution pins. The method for manufacturing a semiconductor test probe card space transformer according to claim 9, further comprising a step of sealing the first contact test pads with a protective layer. The method of fabricating a semiconductor test probe card space transformer according to claim 10, wherein the protective layer is formed of a dielectric photoresist material. The method of fabricating a semiconductor test probe card space transformer according to claim 9, wherein the first input/output pad is electrically isolated from the metal ground plane layer. The method of manufacturing a semiconductor test probe card space transformer according to claim 9, wherein the filling step comprises simultaneously filling at least a portion of the recesses with the conductor metal to form the second test contacts. Conductor substrate. The method for manufacturing a semiconductor test probe card space transformer according to claim 9, further comprising depositing a protective layer on the plurality of A test contact with the steps of re-spinning the pins. The method for manufacturing a semiconductor test probe card space transformer according to claim 14, further comprising forming a plurality of recesses in the protective layer and depositing a conductor metal in the recesses of the protective layers for forming The second test contacts. The method of fabricating a semiconductor test probe card space transformer according to claim 9, wherein the substrate has a second side opposite to the first side and defines a plurality of conductor channels of a ball gate array . The method of fabricating a semiconductor test probe card space transformer according to claim 16 further comprising the step of depositing a conductor metal layer on the second side. A method of fabricating a semiconductor test probe card space transformer to reduce a pitch distribution of a contact test pad, comprising: providing a space transformer having a substrate and a plurality of first contact test pads to perform a device under test Electrically testing, defining a first pitch distribution between the adjacent first contact test pads; depositing a first dielectric layer on the upper surface of the substrate and exposing the first contact test pads Forming a plurality of redoning pins and a plurality of contacts on the first dielectric layer, wherein one end of the redistributing pins is electrically connected to the first contact test pads and the other end is respectively Electrically connecting to the contacts; plating a metal on the contacts to form a plurality of top contact surfaces, and defining a plurality of second contact test pads from the adjacent top contact surfaces, the adjacent ones A second pitch distribution that is less than the first pitch is defined between the second contact test pads. The method for manufacturing a semiconductor test probe card space transformer according to claim 18, further comprising sealing the first contact test pads and the second contact test pads with a protective layer. The method for manufacturing a semiconductor test probe card space transformer according to claim 19, further comprising forming a plurality of conductor well channels extending through the protective layer to extend the second contact test pads to the protection An exposed surface of the layer is in electrical contact with a plurality of test card probes for wafer level testing of the integrated circuit wafer. The method for fabricating a semiconductor test probe card space transformer according to claim 18, further comprising forming a ground plane. A method of fabricating a semiconductor test probe card space transformer for reducing a pitch distribution of a contact test pad, comprising: providing a substrate having a plurality of first contact test pads on an upper surface of the substrate to perform a device under test Electrically testing, and a plurality of metal planes, defining a first pitch distribution between the adjacent first contact test pads, the metal planes surrounding each of the first contact test pads, and each The first contact test pads are electrically isolated, the metal planes are grounded as a ground plane; a first dielectric layer is deposited on the upper surface of the substrate, and the first test pads are exposed; and formed a plurality of redistributable pins are electrically connected to the first contact test pads, wherein the redistributable pins have an end electrically connected to the first contact test pad and the other end a point extending to the first dielectric layer, the redistributable pins having between each adjacent two of the end points on the first dielectric layer, defined differently than the first pitch distribution One The second pitch distribution. The method for manufacturing a semiconductor test probe card space transformer according to claim 22, further comprising forming a second dielectric layer and enclosing the red cloth pins, but exposing the re-distribution The endpoints of the foot. The method of fabricating a semiconductor test probe card space transformer according to claim 23, wherein the second dielectric layer is formed of a dielectric photoresist material. The method for fabricating a semiconductor test probe card space transformer according to claim 22, further comprising a step of patterning the first dielectric layer to form a plurality of recesses for subsequent formation of the end points The red cloth pins. The method of fabricating a semiconductor test probe card space transformer according to claim 25, wherein the rewiring pins having the end points are formed by depositing a first conductor metal In the recess. The method for fabricating a semiconductor test probe card space transformer according to claim 23, further comprising depositing a second conductor metal on the end points exposed in the second dielectric layer, thereby The second conductor metal respectively becomes a plurality of second contact test pads, and the pitch distribution between the second contact test pads is the same as the second pitch distribution. The method of manufacturing a semiconductor test probe card space transformer according to claim 27, wherein the second contact test pads are input/output C4 contacts.