KR20100131287A - Space transformer of probe card for electrical tester of semiconductor wafer and manufacturing method therefor - Google Patents

Abstract

PURPOSE: The space transformer of a probe card for testing the electric characteristic of a semiconductor substrate and a method for manufacturing the same are provided to reduce failure rate by performing an electric test before the semiconductor substrate is completely manufactured. CONSTITUTION: One or more slits are formed on a first board(31). A plurality of conductive wirings(34) is formed on a second board(33) to the passing direction of the first board. The second board is inserted into the slit of the first board. A first metal pad is formed on the upper side of the first board and is in electric connection with the wirings of the second board. A second metal pad(36) is formed on the lower side of the first board and is in electric connection with the wirings of the second board.

Description

Space transducer of probe card for device for testing electrical characteristics of semiconductor substrate and manufacturing method thereof {space transformer of probe card for electrical tester of semiconductor wafer and manufacturing method therefor}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a probe card for use in an electrical property inspection device of a semiconductor substrate, and more particularly, to a space transducer of a probe card for electrically connecting a probe to a semiconductor substrate and to conducting electrical property inspection.

In general, a plurality of semiconductor integrated circuit devices are formed on a semiconductor substrate, that is, a silicon wafer or a glass substrate, and then completed through a plurality of processes such as dicing, wire bonding, and packaging. In order to test the operation of such semiconductor integrated circuit devices, a method of inspecting electrical characteristics in a wafer state and a method of testing a completed semiconductor integrated circuit device have been performed.

In the wafer state, electrical property inspection is performed by an electrical die sorting (EDS) process, which includes a tester for determining whether an individual die in a wafer is defective by applying an electrical signal onto the wafer. An electrical property inspection device, which consists of a prober that moves up, down, left, and right by loading a wafer in conjunction with the tester, is generally used.

1 is a view schematically showing an electrical inspection apparatus for a semiconductor integrated circuit device in a wafer or a wafer according to the prior art.

Referring to FIG. 1, a different electrical test apparatus includes a tester head for mounting a probe card 2 to apply an electrical signal to a semiconductor integrated circuit device in a wafer to test a semiconductor integrated circuit device in a wafer. 1), a probe card (2) attached with a probe contacting the wafer, and a wafer (4) being tested to be applied at a designated point of the wafer to apply an electrical signal for checking the electrical operation state from the tester, and the appropriate temperature And a prober (3) which includes a wafer chuck for applying a force and moves the wafer to the X, Y, Z axis and the like to bring each integrated circuit element in the wafer into contact with the probe at a designated point.

Fig. 2 (a) is a diagram schematically showing the structure of the probe card 2 according to the prior art.

Referring to FIG. 2 (a), the probe card 2 generally includes a printed circuit board 21, a connecting portion 22 of a space transducer 23 and a printed circuit board 21 formed of a connection pin, and the like. It consists of a space transducer 23 to which the probe is attached.

The space transducer 23 has a pad (not shown) made of metal on the top and bottom surfaces of the space transducer, and the pad gap formed on the top surface and the pad gap formed on the bottom surface are different from each other, thereby converting the gaps. Performs the function of. The pads formed on the upper surface and the pads formed on the lower surface are electrically connected by wiring inside the space transducer, so that a plurality of microstructured probes are attached to the lower surface collectively and individually, and the pads on the upper surface are printed circuit boards. It has a structure which electrically connects with.

Currently used space transducers are manufactured in the form of MLC (Multi Layer Ceramic) in which a ceramic substrate is formed in multiple layers as shown in FIGS. 2 (b) to 2 (d).

However, the MLC-type spatial transducer is not only complicated in its fabrication process such as preparation for a plurality of individual layers, but also requires a high cost and a long time in manufacturing. Also, as the substrate size increases, the yield increases. Because of the sharp drop, the price increase is very large, and as the number of devices on the wafer to be inspected is rapidly increased, the area of the MLC-type spatial transducer is increased despite the fact that the driving area of the probe card becomes larger and the spatial transducer is also larger. The response is limited in terms of production cost.

In addition, in the technical aspect, the MLC-type spatial transducer has a difference in via position due to expansion / contraction by high temperature sintering, and in particular, as the size increases, defects of the via increase rapidly, resulting in poor applicability to the area. The distance and the number of vias due to electrical short / open / liquidity between the vias are limited.

Furthermore, it is possible to conduct electrical tests only after the fabrication process is completed, which has a problem that the defective rate of the final completed space transducer is high, and the available materials are limited to alumina (Al ₂ O ₃ ), which is required by the probe card. There are constraints to overcome the difference in thermal expansion with the wafer. That is, the limit is shown in the position control by the change of shrinkage rate at high temperature firing.

        Therefore, the problem or object to be solved by the present invention is that the manufacturing process is simple, the manufacturing specifications can be unified, short manufacturing time and low manufacturing cost, the defect rate is reduced even when applied to large area semiconductor substrate To provide a space transducer of a probe card for an electrical property inspection device of a semiconductor substrate with improved large-area substrate correspondence in cost and technical aspects, and a method of manufacturing the same.

In order to achieve the above object, in accordance with the present invention, the spatial transducer of the probe card for electrical property inspection apparatus of the semiconductor substrate comprises a first substrate formed of a single layer and one or more slits; A second substrate having a plurality of conductive wires formed in a direction penetrating the first substrate and inserted into and fixed to one or more slits of the first substrate; A first metal pad formed on an upper surface of the first substrate and electrically connected to a wiring of the second substrate; And a second metal pad formed on the bottom surface of the first substrate and electrically connected to the wiring of the second substrate.

Preferably, the first substrate is made of a material having the same or similar thermal expansion coefficient as that of the semiconductor substrate.

In addition, preferably, a plurality of grooves in a direction passing through the first substrate are formed in the second substrate, and the grooves are filled with a conductive material to form the plurality of conductive wires.

In addition, a plurality of through holes in a direction penetrating the first substrate is formed in the second substrate, and a conductive material is filled in the groove to form the plurality of conductive wires.

More preferably, the first substrate is made of one material selected from ceramic, silicon wafer, tempered glass, alumina (Al ₂ O ₃ ), aluminum nitride (AlN), and silicon carbide (SiC).

     On the other hand, the second substrate is made of a material selected from silicon wafer, alumina, aluminum nitride (AlN), ceramic, FR4, printed circuit board.

In addition, in order to achieve the above object, the manufacturing method of the space transducer of the probe card for the electrical property test apparatus of the semiconductor substrate according to the present invention is to process one or more slits into which the second substrate is inserted into the first substrate made of a single layer. Making; Forming a conductive wiring on the second substrate; Inserting the second substrate into a slit of the first substrate and then positioning and fixing the second substrate to be joined; Forming metal pads on upper and lower surfaces of the first substrate, the metal pads being electrically connected to the metal wires of the second substrate.

Preferably, the step of processing the slit is carried out by a machining process.

     In addition, the step of processing the slit may be performed by an etching process.

     In addition, preferably, the forming of the conductive wiring on the second substrate may include forming a plurality of grooves in a direction penetrating the first substrate on the second substrate, inserting a conductive material into the plurality of grooves; And surface-processing the conductive materials inserted into the plurality of grooves to be separated from each other to form conductive lines.

    The forming of the conductive wiring in the second substrate may include forming a plurality of through holes in the second substrate in a direction passing through the first substrate, and inserting a conductive material into the plurality of through holes. It may include.

According to the present invention, it is possible to insert the second substrate by a variety of simple processing such as machining using a single-layer substrate having low manufacturing cost and simple processing, without using an MLC substrate having a multilayered ceramic substrate. It is possible to reduce the manufacturing time and manufacturing cost of the space transducer by forming a slit and inserting a second substrate in which the manufacturing process is simple and the manufacturing specifications are unified.

In addition, since the conductive wiring is formed on the second substrate and then inserted into and fixed to the first substrate, the sintering process is unnecessary as compared with the MLC-type spatial transducer, so that more accurate vias, that is, the position of the wiring can be realized. It is easy to control the distance and the number of vias only by the fine wiring process of two substrates.

In addition, unlike the MLC-type spatial transducer that can be electrically tested after the final fabrication, it is possible to perform an electrical test before the final fabrication process, that is, a test on the second substrate to reduce the defective rate and reduce the manufacturing cost.

Furthermore, the material of the space transducer can be easily selected, and considering the thermal expansion and / or thermal conductivity of only the first substrate, it is possible to cope with the large-area semiconductor substrate only by securing the machinability for forming the slit. .

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, a spatial transducer according to an embodiment of the present invention will be described with reference to the drawings.

3 (a) is a plan view of a space transducer according to an embodiment of the present invention, and FIGS. 3 (b) and 3 (c) are perspective views of a space transducer according to another embodiment, respectively.

4 and 5 (a) to 5 (d) show a modification of the position and shape of the slit of the first substrate according to various embodiments of the present invention.

Referring to the drawings, the space transducer according to the embodiment of the present invention comprises a first substrate 31 having a single layer and having at least one slit 32 and a plurality of conductive wires 34 in a direction penetrating the first substrate. ) Is formed on the second substrate 33 and the upper surface of the first substrate and formed on the lower surface of the first substrate and the first metal pad 35 electrically connected to the wiring of the second substrate. And a second metal pad 36 electrically connected thereto.

The first substrate 31 may be manufactured by selecting various materials from ceramics, glass, silicon wafers, tempered glass, alumina (Al ₂ O ₃ ), aluminum nitride (AlN), silicon carbide (SiC), and the like.

The material of the first substrate is selected from the same or similar material as the thermal expansion coefficient of the semiconductor substrate, so that it can correspond to the large area semiconductor substrate.

 That is, the material of the first substrate, such as a semiconductor substrate to be tested, that is, a first wafer is manufactured using an implementation cone wafer when the wafer is a silicon wafer, and a first substrate is manufactured using the same tempered glass when the tempered glass is used. It can be selected as the material of the same coefficient of thermal expansion as the semiconductor substrate.

In addition, when considering thermal conductivity, it is more preferable to select a material having a thermal expansion rate similar to that of a semiconductor substrate and excellent in thermal conductivity or similar to a thermal conductivity of the semiconductor substrate.

In other words, when the semiconductor substrate is tested, the temperature required for the test is generated in the chuck so that the probe card is heated through the wafer and the probe, and the thermal expansion rate is similar, but if the thermal conductivity is good or similar to the wafer, the temperature is saturated. Less time is required to shorten the test time of the semiconductor substrate, resulting in increased productivity.

 Thus, for example, when the semiconductor substrate is a silicon wafer, it is preferable to fabricate the first substrate by selecting a material of the first substrate from aluminum nitride (AlN) having similar thermal conductivity as well as thermal expansion coefficient with silicon.

For reference, the thermal conductivity of silicon (Si) is 157 RT [W / mK], the coefficient of thermal expansion is 3.9 [x106 / oC], and the aluminum nitride (AlN) has thermal conductivity of 160 to 170 RT [W / mK] and thermal expansion. The coefficient is 4.2 [x106 / oC] and the coefficient of thermal expansion and thermal conductivity are most similar to that of silicon.

 The slit 32 of the first substrate 31 may be formed by machining, such as drilling, milling, scribing, and manufactured to form a second substrate upright. When the first substrate is made of glass or silicon wafer, the brittleness is higher than that of ceramics, so glass may be used for tempered glass, and silicon wafer may be manufactured by dry or wet etching.

Since the first substrate must have insulating properties, in the case of a conductive material (including a semiconductor material), an insulating layer (not shown) is additionally formed on the surface after processing.

In addition, the position and shape of the slit 32 is determined in consideration of the position where the probe to the probe tip is formed, the size is made slightly larger than the thickness of the second substrate so that the second substrate can stand up and inserted.

 6 to 8 show modifications of the form of the conductive wiring of the second substrate according to various embodiments of the present invention.

Referring to the drawings as well, the second substrate 33 may be formed by dicing saw, scribing, or the like on a substrate made of a ceramic or the like, which has a size that can be inserted into the slit 32 processed on the first substrate 31. After forming a plurality of grooves in a direction penetrating the first substrate by mechanical processing, and then filling the groove with a plating and conductive epoxy, it can be produced by separating the wirings filled in the plurality of grooves through the surface processing.

As the material of the second substrate, silicon wafer, alumina, aluminum nitride (AlN), other ceramics, FR4, or the like may be used.

According to an embodiment, as shown in FIG. 7B, the second substrate is formed by forming a plurality of through holes in a direction penetrating the first substrate through drilling or the like, and then filling the through holes with a conductive material to form a wiring. May be formed.

In addition, according to the embodiment, as shown in Fig. 7 (c), both the grooves and the through holes may be formed, and a conductive material may be inserted into them to form a wiring.

Further, according to the embodiment, the printed circuit board on which the wiring circuit is formed may be used as it is.

The second substrates may be manufactured, respectively, or may be manufactured by simultaneously cutting a plurality of second substrate portions on a large substrate.

The second substrate manufactured as described above is inserted into and fixed to the slit of the first substrate. The second substrate may be fixed by filling the gap between the first substrate and the second substrate with a non-conductive epoxy or the like after inserting the slit into the slit of the first substrate.

In addition, according to the embodiment, when using non-conductive epoxy and semi-sintered ceramic as the material of the second substrate, the materials are first semi-processed (not hard) into a size that can be inserted into the first substrate, and then conductive A needle or the like may be directly inserted into a desired position to be cured, or may be removed after insertion to form a through hole, and later, the through hole may be filled with a conductive material to form a second substrate inserted and fixed to the first substrate.

      Referring to FIG. 3, metal pads 35 made of metal are formed on the top and bottom surfaces of the space converter, respectively, and the gaps between the pads formed on the top surface and the pad gaps formed on the bottom surface are different from each other. Performs the function of. The pads formed on the upper surface and the pads formed on the lower surface are electrically connected by the wiring inside the space transducer, and a plurality of microstructured probes are attached to the lower surface collectively and individually, and the pads on the upper surface are connected to the printed circuit board. It has a structure to electrically connect.

The metal pad may be formed on the upper and lower surfaces of the first substrate into which the second substrate is inserted, in order to sequentially connect various known substrates, ie, chemical vapor deposition (CVD), physical vapor deposition (PVD), or electroless plating. seed layer), patterned photoresist through photolithography process, metal (Cu / Au / Ni, etc.) wiring through plating, removing photoresist and remaining seed layer It can be produced by forming a conductive wiring by forming a pattern with a photoresist, or forming a metal wiring layer thereon, and a lift-off method for removing the photoresist.

Hereinafter, referring to FIGS. 4 and 9 (a) to 9 (c), a method of manufacturing a space transducer of a probe card for an electrical characteristic inspection device for a semiconductor substrate according to an embodiment of the present invention will be described. It shall be described in a range that does not overlap with the description.

9 (a) to 9 (c) are diagrams illustrating a manufacturing process of the space transducer according to the embodiment of the present invention.

      According to an aspect of the present invention, there is provided a method of fabricating a space transducer of a probe card for a device for testing electrical characteristics of a semiconductor substrate, the method including: forming one or more slits into which a second substrate is inserted into a first substrate formed of a single layer; Forming a conductive wire, inserting the second substrate into a slit of the first substrate, and then aligning and fixing the second substrate; a metal electrically connected to the metal wiring of the second substrate on the upper and lower surfaces of the first substrate; Forming a pad.

The step of forming one or more slits on the single layered substrate is performed by machining such as drilling, milling and scribing. When fabricating the first substrate from silicon wafer, the brittleness is higher than that of ceramics. Therefore, the silicon wafer may be manufactured by dry or wet etching. The slit is formed in a shape that can be fitted to stand up the second substrate.

In addition, the position and shape of the slit is determined in consideration of the position where the probe to the probe tip is formed, the size is made slightly larger than the thickness of the second substrate so that the second substrate can stand up and inserted.

The forming of the conductive wiring on the second substrate may be performed by mechanical processing through dicing sawing and scribing, etc., on the second substrate manufactured to a size that can be inserted into the slit of the first substrate according to the form of wiring required. 1 After forming a plurality of grooves in a direction penetrating the substrate, and filling the grooves with plating and conductive epoxy, etc. and then separating the wirings filled in the plurality of grooves through the surface processing can be performed by the required wiring Depending on the form, a plurality of through holes may be formed in a direction penetrating the first substrate through drilling or the like, and then wiring may be formed by filling the through holes with a conductive material. In addition, depending on the wiring form, the wiring may be formed by a process of forming both the groove and the through hole and inserting a conductive material therein.

      Here, the process of forming a plurality of grooves to form a wire includes: forming a plurality of grooves in a direction penetrating the first substrate in a second substrate, inserting a conductive material into the plurality of grooves, and And conducting the surface processing so that the conductive materials inserted into the plurality of grooves are separated from each other to form conductive wires. The process of forming the plurality of holes to form the wiring may be performed in a direction penetrating the first substrate to the second substrate. Forming a plurality of through holes, and inserting a conductive material into the plurality of through holes.

Further, in the case of using the printed circuit board on which the wiring circuit is formed according to the embodiment, in the above step, the conductive wiring required is formed on the second substrate in accordance with a process for manufacturing a general printed circuit board.

Inserting the second substrate into the slit of the first substrate, and then aligning and fixing the second substrate by inserting the second substrate at the correct position in the slit of the first substrate, the gap between the first substrate and the second substrate after the alignment. It is carried out by the process of hardening after filling with non-conductive epoxy etc. However, the present invention is not limited thereto, and the second substrate may be performed by various chemical and mechanical methods depending on the material features and structures of the substrates.

According to the embodiment, in the case of using non-conductive epoxy and semi-sintered ceramic as the material of the second substrate, first of all, these materials are semi-processed (not rigid) into a size that can be inserted into the first substrate, and then conductive needles and the like. Is inserted directly into a desired position and cured or removed after insertion to form a through hole, and then the through hole is filled with a conductive material to form a second substrate inserted and fixed to the first substrate. Forming the conductive wiring in the step and inserting the second substrate into the slit of the first substrate, and then aligning, fixing and coupling may be performed simultaneously or in different orders.

      Forming a metal pad electrically connected to the metal wires of the second substrate on the upper and lower surfaces of the first substrate, the metal pad may be wired to various known substrates sequentially on the upper and lower surfaces of the first substrate into which the second substrate is inserted. In other words, a process of forming a seed layer for plating by using chemical vapor deposition (CVD), physical vapor deposition (PVD) or electroless plating on one surface of the second substrate to which the second substrate is bonded. To form a pattern with photoresist through a photolithography process, to form metal (Au / Ni / Cu, etc.) wiring through plating, and to remove the photoresist and seed layer in order. Forming a photoresist mold or forming a metal wiring layer and removing a photoresist sequentially to form a required conductive wiring can do.

The present invention has been described above with reference to the embodiments shown in the drawings according to the embodiments, but these are exemplary and the scope of the present invention is not limited to these, including the embodiments of various modifications and equivalent ranges claimed The scope of the present invention is determined according to the matters described in the scope.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 schematically shows an electrical inspection apparatus for a semiconductor integrated circuit device in a wafer or a wafer according to the prior art.

Figure 2 (a) schematically shows the structure of the probe card according to the prior art.

Figure 2 (b) to Figure 2 (d) is an exemplary view in the case of manufacturing a spatial transducer according to the prior art in the form of MLC (Multi Layer Ceramic) in which a ceramic substrate is formed in multiple layers.

Figure 3 (a) is a plan view of a space transducer according to an embodiment of the present invention.

3 (b) and 3 (c) are perspective views of a space transducer according to another embodiment of the present invention.

4 is a perspective view of a first substrate according to an embodiment of the present invention;

And (a) to (d) show a modification of the position and shape of the slit of the first substrate according to various embodiments of the present invention.

6 is a perspective view of a second substrate according to an embodiment of the present invention;

7A to 7C are plan views showing modifications of the form of the conductive wiring of the second substrate according to various embodiments of the present invention.

8A to 8E are cross-sectional views showing modifications of the form of the conductive wiring of the second substrate according to various embodiments of the present invention.

9 (a) to 9 (c) are views for explaining the manufacturing process of the space transducer according to the embodiment of the present invention.

Claims (11)

In the space transducer of the probe card for the electrical property inspection device of the semiconductor substrate, A first substrate composed of a single layer and formed with at least one slit, A second substrate having a plurality of conductive wires formed in a direction passing through the first substrate and inserted into and fixed to one or more slits of the first substrate, respectively; A first metal pad formed on an upper surface of the first substrate and electrically connected to a wiring of the second substrate; And a second metal pad formed on the bottom surface of the first substrate and electrically connected to the wiring of the second substrate.       The method of claim 1,      And the first substrate is made of a material having the same or similar thermal expansion coefficient as that of the semiconductor substrate. The method of claim 1, And a plurality of grooves in a direction penetrating the first substrate and filled with a conductive material in the groove to form the plurality of conductive wires.       The method of claim 1,      And a plurality of through holes in a direction penetrating the first substrate and filled with a conductive material in the groove to form the plurality of conductive wires in the second substrate.      The method of claim 1, And the first substrate is made of one material selected from ceramic, silicon wafer, tempered glass, alumina (Al ₂ O ₃ ), aluminum nitride (AlN), and silicon carbide (SiC).      The method of claim 1,      And the second substrate is made of a material selected from silicon wafer, alumina, aluminum nitride, ceramic, FR4, and printed circuit board.      In the manufacturing method of the space transducer of the probe card for the electrical property inspection device of the semiconductor substrate,      Forming at least one slit into which the second substrate is inserted into the first substrate formed of a single layer;       Forming a conductive wiring on the second substrate;      Inserting the second substrate into a slit of the first substrate and then positioning and fixing the second substrate to be joined;      And forming a metal pad on the upper and lower surfaces of the first substrate, the metal pad being electrically connected to the metal wires of the second substrate. The method of claim 7, wherein And processing the at least one slit is performed by a machining process.       The method of claim 7, wherein      And processing the one or more slits is performed by an etching process.       The method of claim 7, wherein       Forming the conductive wiring on the second substrate,       Forming a plurality of grooves in the second substrate in a direction passing through the first substrate,       Inserting a conductive material into the plurality of grooves, and      And processing the surface of the conductive material inserted into the plurality of grooves so as to be separated from each other to form a conductive wire.       The method of claim 7, wherein       Forming the conductive wiring on the second substrate,      And forming a plurality of through holes in the second substrate in a direction penetrating through the first substrate, and inserting a conductive material into the plurality of through holes.

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