KR20220148682A - Method of repairing space transformer for probe card and space transformer using the same - Google Patents

Abstract

The present invention relates to a method for repairing a space transformer for a probe card and a space transformer for a probe card using the same, the method comprising the steps of: providing a ceramic substrate having a first main surface and a second surface opposite to the first main surface; forming a multilayer wiring layer by alternately stacking an insulating layer and a wiring pattern layer on the first main surface of the ceramic substrate once or more; forming a first via hole and a second via hole for exposing the upper surface of a first wiring pattern layer and the upper surface of a second wiring pattern layer from the uppermost insulating layer, respectively, with respect to each of the first wiring pattern layer and the second wiring pattern layer on a disconnection defect path in the multilayer wiring layer; and forming a bypass conductive path by forming a conductive wiring structure connected to the uppermost insulating layer while filling the first via hole and the second via hole. Therefore, provided is a method for repairing a space transformer for a probe card, wherein production efficiency can be increased.

Description

Method of repairing space transformer for probe card and space transformer using the same

The present invention relates to a semiconductor test apparatus, and more particularly, to a method for repairing a space converter for a probe card and a space converter using the same.

In general, a probe card is used to inspect electrical defects of a wafer on which a plurality of semiconductor devices such as a memory are formed. The probe card is disposed between a printed circuit board connected to the tester and a plurality of probes connected to a device under test (DUT) of a wafer to be tested, and is an interposer for relaying power and signals. space transformer (also called STF).

In the electrical failure inspection using the space transducer, after a plurality of probe pins are brought into contact with the connection terminals of the DUT, power supply and various signals necessary for testing are input/output between the tester and the semiconductor device, thereby Defects such as disconnection and short circuit (open or short) or processing errors can be determined.

By the way, in recent years, in order to increase the throughput of the electrical inspection of the semiconductor element, it is required to simultaneously inspect the DUT to be inspected for the entire wafer level at the same time. As the semiconductor device is highly integrated, the pitch between the electrode pads of the semiconductor device is further refined, and accordingly, the pitch of the probes is further reduced. In response to the high integration of the semiconductor device, in order to secure reliable contact between probes in the spatial converter, the wiring layer of the STF is gradually multi-layered for pitch conversion. The wiring layer may be manufactured by alternately repeatedly laminating an insulating layer and a wiring layer on a ceramic substrate. As described above, during a process of alternately repeatedly laminating the insulating layer and the wiring layer, a disconnection defect between different wiring layers may occur.

In the related art, when such poor contact between wiring layers occurs, the defect caused by the disconnection is repaired by removing the corresponding layer or removing the entire layer and then forming the insulating layer and the wiring layer again. However, such a conventional repair process is cumbersome and takes a lot of process time, and it is a great obstacle to increase the throughput of the space converter.

An object of the present invention is to provide a repair method of a space converter for a probe card capable of increasing production efficiency by removing a disconnection defect between wiring layers without removing a wiring layer and an insulating layer of the space converter in which the defect has occurred.

In addition, the technical problem to be achieved by the present invention is to provide a space converter for a probe card having the above advantages.

A method of repairing a space converter for a probe card for solving the above technical problem includes providing a ceramic substrate having a first main surface and a second surface opposite to the first main surface; forming a multilayer wiring layer by alternately stacking an insulating layer and a wiring pattern layer at least once on the first main surface of the ceramic substrate; exposing the upper surface of the first wiring pattern layer and the upper surface of the second wiring pattern layer from the uppermost insulating layer for each of the first wiring pattern layer and the second wiring pattern layer on the disconnection defect path of the multilayer wiring layer, respectively forming a first via hole and a second via hole; and forming a bypass conductive path by forming a conductive wiring structure connected on the uppermost insulating layer while filling the first via hole and the second via hole.

In an embodiment, the conductive wiring structure may include copper (Cu), silver (Ag), gold, or an alloy thereof. The insulating layer is a polyimide resin, polyphenylene sulfide resin, polyester resin, benzocyclobutene (BCB) resin, epoxy resin, bismaleimide triazine resin, polyphenylene ether resin, polyquinoline resin, fluororesin, or a combination thereof. may include

In an embodiment, the conductive wiring structure may include: melting and dropping a conductive metal material to form a first filling conductive material filling the first via hole; forming a second filling conductive material filling the second via hole; and forming a bridge conductor connecting the first charging conductor and the second charging conductor on the uppermost insulating layer. and sintering the first filling conductive material, the second filling conductive material, and the bridge conductive material. The sintering of the first filling conductive material, the second filling conductive material, and the bridge conductive material may be performed by laser annealing.

In an embodiment, any one of the first wiring pattern layer and the second wiring pattern layer may be an uppermost layer to which a probe pin is bonded. Also, in an embodiment, the second via hole may have a greater depth than the first via hole, and a depth of the first via hole or the second via hole may be in a range of 10 μm to 50 μm. Also, in an embodiment, a diameter of the first via hole or the second via hole may be in a range of 20 μm to 100 μm.

In an embodiment, the first via hole or the second via hole may have a plurality of sub via holes, and the plurality of sub via holes may be arranged at predetermined intervals. The first via hole or the second via hole may be formed by laser drilling or mechanical drilling.

A space converter for a probe card according to an embodiment of the present invention for achieving the other technical problem is a ceramic substrate; a multilayer wiring layer disposed on the ceramic substrate and including an insulating layer and a wiring pattern layer alternately stacked at least once; a plurality of conductive via electrodes connecting the wiring pattern layers; and for each of the first wiring pattern layer and the second wiring pattern layer associated with the via electrode having the disconnection defect to replace the via electrode having the disconnection defect among the plurality of conductive via electrodes, the first wiring pattern from the uppermost insulating layer The first via hole and the second via hole exposing the upper surface of the layer and the upper surface of the second wiring pattern layer, respectively, and the conductive wiring connected on the uppermost insulating layer while filling the first via hole and the second via hole A bypass conductive path comprising a structure may be included.

In an embodiment, the conductive wiring structure may be made of copper (Cu) or silver (Ag). In addition, the insulating layer is a polyimide resin, polyphenylene sulfide resin, polyester resin, BCB (Benzocyclobutene) resin, epoxy resin, bismaleimide triazine resin, polyphenylene ether resin, polyquinoline resin, It may include a fluororesin or a combination thereof.

The ceramic substrate may be a low temperature co-fired ceramic (LTCC) substrate. In an embodiment, a depth of the first via hole or the second via hole may be in a range of 10 μm to 50 μm. Also, a diameter of the first via hole or the second via hole may be in a range of 20 μm to 100 μm.

According to embodiments of the present invention, at least two via holes having different depths to be respectively connected to the first wiring layer and the second wiring layer are formed in order to repair a disconnection defect between the wiring layers, and a first of the at least two via holes is formed. For a probe card capable of increasing production efficiency by eliminating disconnection defects between wiring layers by forming a bypass conductive path by sintering a conductive metal material to connect a via hole and a second via hole having a greater depth than the first via hole A method of repairing a spatial converter may be provided.

In addition, according to embodiments of the present invention, a space converter for a probe card having the above advantages can be provided.

1A and 1B are cross-sectional views of a space converter for a probe card according to an embodiment of the present invention.
2A and 2B are diagrams for explaining a repair method of a space converter for a probe card according to an embodiment of the present invention.
3A and 3B are diagrams for explaining a repair method of a space converter for a probe card according to another embodiment of the present invention.
4A and 4B are diagrams for explaining a repair method of a space converter for a probe card according to another embodiment of the present invention.
5A and 5B are diagrams for explaining a repair method of a space converter for a probe card according to another embodiment of the present invention.
6 is a plan view illustrating a method of forming a via hole for forming a bypass conductive path according to another embodiment of the present invention.
7A to 7C are views for explaining the formation of a bypass conductive path using a transparent substrate according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Examples of the present invention to be described below are provided to more clearly explain the present invention to those of ordinary skill in the art, and the scope of the present invention is not limited by the following examples, The embodiment may be modified in many different forms.

The terminology used herein is used to describe specific embodiments, not to limit the present invention. As used herein, terms in the singular form may include the plural form unless the context clearly dictates otherwise. Also, as used herein, the terms "comprise" and/or "comprising" refer and does not exclude the presence or addition of one or more other shapes, steps, numbers, actions, members, elements, and/or groups thereof. In addition, as used herein, the term “connection” not only means that certain members are directly connected, but also includes indirectly connected members with other members interposed therebetween.

In addition, in the present specification, when a member is said to be “on” another member, this includes not only a case in which a member is in contact with another member but also a case in which another member is present between the two members. As used herein, the term “and/or” includes any one and any combination of one or more of the listed items. In addition, as used herein, terms such as "about", "substantially", etc. are used in the meaning of the range or close to the numerical value or degree, in consideration of inherent manufacturing and material tolerances, and to help the understanding of the present application The exact or absolute figures provided for this purpose are used to prevent the infringer from using the mentioned disclosure unfairly.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The size or thickness of the regions or parts shown in the accompanying drawings may be slightly exaggerated for clarity and convenience of description. Like reference numerals refer to like elements throughout the detailed description.

1A and 1B are cross-sectional views of a space converter 100 for a probe card according to an embodiment of the present invention.

Referring to FIGS. 1A and 1B , the space converter 100 for a probe card may include a ceramic substrate S1 and a multilayer wiring layer S2 . Although not shown, the probe card is printed on the second surface of the ceramic substrate S1 opposite to the first surface in contact with the multilayer wiring layer S2 of the ceramic substrate S1, for example, through a signal transmission means such as a pogo pin. A connection terminal connected to the circuit board PCB may be accommodated, and a probe pin may be bonded to the first surface of the ceramic substrate S1. 1A and 1B show that the thickness of the ceramic substrate S1 is smaller than the thickness of the multi-layer wiring layer S2, but this is for convenience of explanation, and the thickness of the ceramic substrate S1 is the thickness of the multi-layer wiring layer S2. can be larger than

In an embodiment, the ceramic substrate S1 may be manufactured by laminating a plurality of green sheets and then sintering the resulting laminate. Internal wiring patterns may be formed on the surfaces of the green sheets, and internal via conductors connecting between the stacked upper internal wiring patterns and the lower internal wiring patterns may be formed through the respective green sheets. In addition, the plurality of green sheets may include a mixture of ceramic powder components including a glass component for Low Temperature Cofired Ceramics (LTCC). In this case, the metal constituting the internal wiring pattern and the via conductor may mainly include a low-resistance metal component having a low melting point, such as silver and copper.

The multilayer wiring layer S2 formed on the ceramic substrate S1 has a structure in which insulating layers P0 to P3 and wiring pattern layers EP0 to EP3 are alternately stacked, and each other through internal vias V1 to V3. The interconnection pattern layers EP0 to EP3 of different layers may be connected. Although not shown, the multilayer wiring layer S2 may further include a through via penetrating in the thickness direction of the multilayer wiring layer S2 . 1A to 1B illustrate a structure in which the insulating layers P0 to P4 and the wiring pattern layers EP0 to EP3 are alternately stacked four times in the multilayer wiring layer S2, but the present invention is limited thereto. In order to achieve a pitch conversion corresponding to a suitable inter-probe pitch, the multilayer wiring layer S2 is formed by alternately stacking the insulating layers P0 to P4 and the wiring pattern layers EP0 to EP3 4 times or less or 4 or more times. may be configured.

In one embodiment, the insulating layers (P0 to P3) are resin insulating layers, polyimide resin, polyphenylene sulfide resin, polyester resin, BCB (Benzocyclobutene) resin, epoxy resin, bismaleimide triazine resin, polyphenyl It may be composed of an organic insulating material such as a lenether resin, a polyquinoline resin, or a fluororesin. However, the present invention is not limited to these materials. Preferably, in the present invention, the insulating layers (P0 to P4) may include a polyimide resin.

In an embodiment, the insulating layers P0 to P3 may be formed on the upper surface of the ceramic substrate S1 through a coating method such as a spin coating method, a dip coating method, a curtain coating method, or a printing method. After coating, the insulating layers P0 to P4 having a thickness of about 5 μm to about 50 μm may be formed by curing with heat of about 400° C. Among these coating methods, the spin coating method is preferable from a viewpoint of the uniformity of a large area of a coating film.

In one embodiment, after the formation of each of the insulating layers P0 to P4, the wiring pattern layers EP0 to EP3 may be alternately formed on the inside or surface of a portion of the insulating layers P0 to P4, and the insulating layer ( Internal vias V1 to V3 passing through P0 to P4 to connect the interlayer wiring pattern layers to each other may be formed. In order to form the internal vias V1 to V3 , first via holes having a diameter of about 20 μm to 100 μm may be formed in the insulating layers P0 to P4 . The method of forming the via hole is performed by using a resist film having an opening in the insulating layer P0 to P4 as an etching mask and etching a part of the insulating layer P0 to P4 corresponding to the opening, or by laser drilling or ion drilling. A part of the insulating layers P0 to P4 may be directly removed by the same material method to expose a part of the underlying wiring baton layer. As another example, an insulating layer having via holes may be simultaneously formed by patterning the photosensitive resin by a photolithography method using a photosensitive resin as the insulating layer. To form a via conductor, the via hole may be filled with a metal conductor such as copper or silver. For this purpose, the via hole can be filled in the same way as a doctor blade using a conductor paste.

In order to form the wiring pattern layers EP1 to EP3, the first conductor layer as a seed layer (not shown) is applied to the entire surface of the insulating layers P1 to P3 by a thin film deposition method such as a vapor deposition method, a sputtering method, or an ion plating method. ) can be formed. Thereafter, a mask film having a wiring pattern-shaped opening, for example, a photoresist film (not shown) is formed on the first conductor layer, and then a suitable potential is applied to the first conductor layer to form the openings by electrolytic plating. A wiring pattern can be formed inside. In another embodiment, in a state in which the via hole is formed in the insulating layer, a seed layer is formed on the upper surface of the insulating layer and the side and bottom surfaces of the via hole as described above, and then the via hole is exposed on the seed layer. After forming a photoresist film having an opening for forming a wiring pattern layer and an opening for forming a wiring pattern layer, electrolytic plating is performed to fill the via hole formed in the insulating layer and at the same time fill the opening for forming the wiring pattern layer. The conductor and the wiring pattern layer can be formed at the same time. The photoresist layer is removed by dissolving it with plasma ashing or an organic solvent, and the unnecessary seed layer is removed by etching, so that the wiring pattern layers EP1 to EP3 and the via conductor may remain. A noble metal layer such as a nickel plated layer and a gold plated layer may be sequentially formed on the surface of the connection pad (not shown) provided on the uppermost surface of the multilayer wiring layer S2 for corrosion prevention or connectivity with the probe.

In the process of forming the multilayer wiring layer S2 by alternately stacking the insulating layers P1 to P3 and the wiring pattern layers EP1 to EP3 on the ceramic substrate S1 as described above, the internal vias V1 to V3 and A disconnection defect may occur between the wiring pattern layers EP1 to EP3 . In the prior art, defects were repaired by removing the wiring layer and the insulating layer and then forming the insulating layer and the wiring layer again as in the above-described process, or removing the entire multilayer wiring layer S2 and newly forming the multilayer wiring layer S2.

For example, as shown in FIG. 1A , when the contact between the wiring pattern layer EP2 of the insulating layer P2 and the internal via V3 is poor OP1, the insulating layer P1 to the insulating layer P3 or the insulating layer After removing (P2) and the insulating layer (P3) and the corresponding wiring pattern layers, the insulating layer (P1) to the insulating layer (P3) or the insulating layer (P2) and the insulating layer (P3) and the corresponding wiring pattern layer are formed again. The short-circuit defective area OP1 may be repaired. In another embodiment, as in FIG. 1B , when the contact OP2 between the wiring pattern layer EP1 of the insulating layer P1 and the internal via V2 is poor OP2, the insulating layer P0 to the insulating layer P3 or the insulating After removing the layers (P1) to (P3) and the corresponding wiring pattern layer, the insulating layer (P0) to the insulating layer (P3) or the insulating layer (P1) to the insulating layer (P3) and the corresponding wiring layers are formed to form a short circuit defect The area OP2 is repaired. The short-circuit defective regions OP1 and OP2 may be short-circuited or referred to as deterioration of insulation characteristics. In the present invention, in order to solve the inconvenience of removing the insulating layer and the wiring pattern layer when a defect occurs, the repair method of the space converter for the probe card of FIGS. 2A to 5B may be used below.

In an embodiment, the defective position OP1 or OP2 may be detected through an open/short (O/S) inspection, and the open/short (O/S) inspection is performed whenever the insulating layer and the wiring layer are stacked one by one. can Therefore, when a defect occurs, it can be expected as a defect between the wiring pattern layer of the uppermost layer and another wiring pattern layer of the lower layer of the uppermost layer. In another embodiment, the open/short (O/S) test may be performed after alternately stacking both the insulating layer and the wiring pattern layer.

2A and 2B are diagrams for explaining a repair method of a space converter for a probe card according to an embodiment of the present invention. As shown in Fig. 1a, whenever the insulating layer (P0) to the insulating layer (P3) are stacked one by one in the space converter 100 for the probe card, a defect detection of the space converter 100 for the probe card is performed through O/S inspection In this case, it is assumed that no defect is detected in the insulating layer P0 to the insulating layer P2 and the defect is detected OP1 after the insulating layer P4 is formed. 2A to 2B are cross-sectional views of the space transducer 100 for the probe card enlarged with the defective position OP1 occurring in the space transducer 100 for the probe card of FIG. 1A .

Referring to FIG. 2A , first, providing a ceramic substrate S1 having a first main surface and a second surface opposite to the first main surface, and insulating layers P0 to P0 on the first main surface of the ceramic substrate S1 P3) and the wiring pattern layers EP0 to EP3 are alternately stacked at least once to form the multi-layer wiring layer S2, whereby a space converter for a probe card may be manufactured.

When a disconnection defect OP1 occurs between the first wiring pattern layer EP3 of the insulating layer P3 and the second wiring pattern layer EP2 of the insulating layer P2 in the space converter 100 for the probe card, For repair, two via holes VH1 and VH2 are formed using, for example, laser drilling or mechanical drilling.

In an embodiment, the via hole VH1 is connected to the second wiring pattern layer EP2 of the insulating layer P2, and the via hole VH1 is connected to the second wiring pattern layer EP2 of the insulating layer P2. may be connected, and a depth of the via hole VH1 may be greater than a depth of the via hole VH2. In addition, with respect to the plane direction of the space converter 100 for the probe card, a non-overlapping region O1 is partially present in the first wiring pattern layer EP3 and the second wiring pattern layer EP2, and the non-overlapping region exists. By forming the via hole VH1 through O1 , the via hole VH1 does not penetrate the first wiring pattern layer EP3 . The first wiring pattern layer EP3 of the insulating layer P3 is the uppermost layer of the multi-layer wiring layer S2 and a probe pin may be bonded thereto.

In one embodiment, for each of the first wiring pattern layer EP3 and the second wiring pattern layer EP2 on the disconnection defect path of the multilayer wiring layer S2, from the uppermost insulating layer P3 to the first wiring pattern layer EP3 ) and a first via hole VH1 and a second via hole VH2) exposing the upper surface of the second wiring pattern layer EP2, respectively, may be formed.

after, Referring to FIG. 2B , the first via hole VH1 and the second via hole VH2 are respectively formed by melting a conductive metal material to electrically connect the first via hole VH1 and the second via hole VH2. A bridge that forms a filling first charging conductor RT1_1 and a second charging conductor RT1_2, and connecting upper surfaces of the first and second charging conductors RT1_1 and RT1_2 on the uppermost insulating layer P3 After the conductive material RT1_3 is formed, the conductive materials RT1_1 , RT1_2 , and RT1_3 are sintered to form the bypass conductive path RT1 to repair the disconnection defect OP1 of the space converter 100 for the probe card. . In one embodiment, the step of forming the bypass conductive path RT1 by melting and sintering the conductive metal material may include: preparing a transparent substrate on which the conductive metal material is coated on one surface, for example, a glass stick; The other surface of the transparent substrate is irradiated with a laser to convert the coated conductive metal material on the one surface into a liquid phase, and the liquid conductive metal material is filled in the first via hole (VH1) and the second via hole (VH2) At the same time, a bridge conductor connecting the filled first via hole VH1 and the second via hole VH2 is formed on the insulating layer P3 . The conductive metal material may include copper (Cu) or silver (Ag), but the present invention is not limited thereto. The sintering of the conductive materials may be performed through laser annealing.

In one embodiment, the depth of the first via hole VH1 and the second via hole VH2 is preferably 10 μm to 50 μm. In addition, the diameter of the first via hole VH1 and the second via hole VH2 is preferably 20 μm to 100 μm.

3A and 3B are views for explaining a repair method of a space converter for a probe card according to another embodiment of the present invention, and FIGS. 4A and 4B are views of a space converter for a probe card according to another embodiment of the present invention. A diagram for explaining a repair method. As shown in FIG. 1B, after stacking some multi-layer wiring layers including insulating layers P0 to P3 in the space converter 100 for the probe card, the space converter 100 for the probe card is defective through O/S inspection. When the detection is performed, it is assumed that a disconnection defect is detected OP2 in the region of the insulating layer P1 to the insulating layer P2 level.

Referring to FIG. 3A , it is assumed that the space converter 100 for the probe card has a disconnection defect at the position OP2 as illustrated in FIG. 1B . First, when the space transducer 100 for the probe card manufactured by alternately stacking the insulating layer and the wiring layer at least once on the ceramic substrate S1 is prepared, the insulating layer P1 in the space transducer 100 for the probe card is prepared. Laser drilling or mechanical drilling of the two via holes VH1' and VH2' to repair the disconnection defect region OP2 between the first wiring layer EP1 and the second wiring pattern layer EP2 of the insulating layer P2 is formed using Here, since the first wiring layer EP1 of the insulating layer P1 and the wiring pattern layer EP2 of the insulating layer P2 overlap, the via hole VH1 ′ is formed through the second wiring pattern layer EP2 . can be

In one embodiment, the via hole VH1' penetrates the wiring pattern layer EP2 to expose the upper surface of the first wiring layer EP1 of the insulating layer P1, and the via hole VH2' is formed in the insulating layer ( The upper surface of the third wiring pattern layer EP3 of P3 may be exposed. The depth of the first via hole VH1' is greater than the depth of the second via hole VH2'. In addition, some non-overlapping regions O1 exist in the first wiring layer EP1 and the third wiring pattern layer EP3 based on the planar direction of the space converter 100 for the probe card, and the non-overlapping region O2 ) through the first via hole VH1 ′, so that the first via hole VH1 ′ does not penetrate the wiring pattern layer EP3 . The third wiring pattern layer EP3 of the insulating layer P3 is the uppermost layer of the multi-layer wiring layer S2 and a probe pin may be bonded thereto.

after, Referring to FIG. 3B , a conductive metal material is melted so as to be electrically connected between the first via hole VH1 ′ and the second via hole VH2 ′ and a bridge is formed to connect the upper portion and then sintered. By forming the bypass conductive path RT2 , the disconnection defect region OP2 of the space converter 100 for the probe card may be repaired. In one embodiment, the step of forming the bypass conductive path RT2 by melting and sintering the conductive metal material includes preparing a transparent substrate coated with the conductive metal material on one surface, and irradiating a laser on the other surface of the transparent substrate to melt the conductive metal material deposited on the one surface, and fill the first via hole (VH1') and the second via hole (VH2') with the liquid conductive metal material and fill the first via hole ( The method may include forming a bridge line connecting between VH1 ′ and the second via hole VH2 ′ on the insulating layer P3 . The conductive metal material may include copper (Cu) or silver (Ag), but the present invention is not limited thereto.

In FIGS. 3A and 3B , the first wiring layer EP1 of the insulating layer P1 and the wiring pattern layer EP2 of the insulating layer P2 overlap so that the via hole VH1' forms the second wiring pattern layer EP2. Although the case of penetrating has been described as an example, a region that does not overlap between the first wiring layer EP1 of the insulating layer P1 and the wiring pattern layer EP2 of the insulating layer P2 as shown in FIGS. 4A and 4B below. (O3) may be present. In this case, the first via hole VH1 ′ may be directly connected to the first wiring layer EP1 without passing through the second wiring pattern layer EP2 . The descriptions of FIGS. 4A and 4B may refer to the descriptions of FIGS. 3A and 3B as long as they are not contradictory.

In the above-described embodiments, an example of forming a bypass conductive path by forming two via holes VH1 and VH2 has been described. However, one via hole VH1 is formed and the other via hole VH2 is replaced. A pre-formed opening OE may be utilized.

5A and 5B are diagrams for explaining a repair method of a space converter for a probe card according to another embodiment of the present invention.

Referring to FIG. 5A , a disconnection defect OP1 between the first wiring pattern layer EP3 of the insulating layer P3 and the second wiring pattern layer EP2 of the insulating layer P2 in the space converter 100 for the probe card. ), one via hole VH1 is formed using laser drilling or mechanical drilling.

5B, the space converter 100 for the probe card is formed by sintering a conductive metal material to form a bypass conductive path RT1 to be electrically connected between the first via hole VH1' and the opening OE. The disconnection defective area OP2 may be repaired. A portion of the upper portion of the first wiring pattern layer EP3 is exposed through the opening OE, so that the via hole VH2 may be filled with a conductive metal material without newly forming the via hole VH2 . This may be more efficient than the repair process time of FIGS. 2A to 2B .

In the repair method disclosed with reference to FIGS. 2A to 5B, the formation of one via hole in each of the first wiring pattern layer and the second wiring pattern layer has been described as an embodiment. However, as will be described later, the first wiring pattern A good conductive path may be formed by forming a plurality of sub-via holes for each of the layer and the second wiring pattern layer.

6 is a plan view illustrating a method of forming a via hole for forming a bypass conductive path according to another embodiment of the present invention.

Referring to FIG. 6 , each of the first wiring pattern layer E3 and the second wiring pattern layer E2 has a plurality of sub-via holes to form a bypass conductive path, and the plurality of sub-via holes are predetermined. They may be arranged in a row at intervals. For example, although the plurality of sub-via holes is shown as three in FIG. 6 , the number of the plurality of sub-via holes may be three or less or three or more.

7A to 7C are views for explaining the formation of bypass conductive paths RT1 and RT2 using a transparent substrate according to an embodiment of the present invention.

Referring to FIGS. 7A to 7C , two via holes are formed to repair a disconnection defect between wiring layers using a laser, and then, a transparent substrate, for example, a glass stick, is formed to electrically connect between the two via holes. By irradiating a laser on one surface, the conductive metal material deposited on the other surface can be converted into a liquid phase (DM), and the liquid metal (DM) fills the via hole and the upper portion of the metal liquid phase filling the via hole on the insulating layer P3 It is possible to form a bridge connecting them to each other.

Referring to FIG. 7A , the conductive metal material is melted to fill the first filling conductive material in the first via hole VH1', and referring to FIG. 7B , the conductive metal material is melted to form the second filling conductive material. After filling the via hole VH2 ′, referring to FIG. 7C , a bridge conductor connecting the first filling conductive material and the second filling conductive material may be formed on the uppermost insulating layer P3 . The first filling conductive material, the second filling conductive material, and the bridge conductive material may be formed in various orders. Specifically, after forming and sintering the first filling conductive material, the bridge conductive material may be formed and sintered, and then the second filling conductive material may be formed and sintered. Alternatively, after forming and sintering the second filling conductive material, the bridge conductive material may be formed and sintered, and then the first filling conductive material may be formed and sintered. Alternatively, after forming and sintering the bridge conductive material, the first filling conductive material or the second filling conductive material may be formed and sintered.

In one embodiment, the transparent substrate includes a conductive metal material (copper, silver, gold, etc.) in the form of a thin film on one surface and a laser may be irradiated on the other surface. The conductive metal material in the region to which the laser is irradiated may change into a liquid metal (or molten metal). Preferably, the glass stick may be transparent glass.

The space converter 100 for a probe card manufactured by using the repair method described above is disposed on one surface of the ceramic substrate S1 and the ceramic wiring substrate S1, and the insulating layers P0 to P3 alternately stacked at least once or more. ) and the multilayer wiring layer S2 including the wiring pattern layers EP0 to EP3, the second of the plurality of internal conductive vias V1 to V3 and the internal conductive vias V1 to V3 connecting between the wiring pattern layers EP0 to EP3. The first via hole VH1 and the second via hole having a greater depth than the first via hole VH1 are connected to each other to replace the internal conductivity (internal vias in the OP1 and OP2 regions) associated with a disconnection defect between the first and second wiring layers. It may include bypass conductive paths RT1 and RT2 composed of (VH2).

It is common in the art to which the present invention pertains that the present invention described above is not limited to the above-described embodiments and the accompanying drawings, and that various substitutions, modifications, and changes are possible within the scope without departing from the technical spirit of the present invention. It will be clear to those who have knowledge.

100: space converter for probe card EP0 to EP3: wiring pattern layer
P0 to P3: insulating layers V1 to V3: internal vias
OP1 to OP2: Defect location S1: Ceramic substrate
S2: multi-layer wiring layer

Claims (16)

providing a ceramic substrate having a first main surface and a second surface opposite to the first main surface;
forming a multilayer wiring layer by alternately stacking an insulating layer and a wiring pattern layer at least once on the first main surface of the ceramic substrate;
exposing the upper surface of the first wiring pattern layer and the upper surface of the second wiring pattern layer from the uppermost insulating layer for each of the first wiring pattern layer and the second wiring pattern layer on the disconnection defect path of the multilayer wiring layer, respectively forming a first via hole and a second via hole;
and forming a bypass conductive path by forming a conductive wiring structure connected on the uppermost insulating layer while filling the first via hole and the second via hole. The method of claim 1,
The conductive wiring structure includes copper (Cu), silver (Ag), gold, or an alloy thereof. The method of claim 1,
The insulating layer is a polyimide resin, polyphenylene sulfide resin, polyester resin, benzocyclobutene (BCB) resin, epoxy resin, bismaleimide triazine resin, polyphenylene ether resin, polyquinoline resin, fluororesin, or a combination thereof. A repair method of a space converter for a probe card comprising a. The method of claim 1,
The conductive wiring structure comprises:
forming a first filling conductive material filling the first via hole by melting and dropping a conductive metal material; forming a second filling conductive material filling the second via hole; and forming a bridge conductor connecting the first charging conductor and the second charging conductor on the uppermost insulating layer. and sintering the first charging conductor, the second charging conductor, and the bridge conductor. 5. The method of claim 4,
The step of sintering the first charging conductor, the second charging conductor, and the bridge conductor is a repair method of a space transducer for a probe card performed by laser annealing. The method of claim 1,
Any one of the first wiring pattern layer and the second wiring pattern layer is the uppermost layer, the repair method of the space converter for a probe card. The method of claim 1,
The second via hole has a greater depth than the first via hole,
The depth of the first via hole or the second via hole is in a range of 10 μm to 50 μm. The method of claim 1,
A repair method of a space converter for a probe card having a diameter of the first via hole or the second via hole in a range of 20 μm to 100 μm. The method of claim 1,
The first via hole or the second via hole has a plurality of sub via holes, and the plurality of sub via holes are arranged at predetermined intervals. The method of claim 1,
wherein the first via hole or the second via hole is formed by laser drilling or mechanical drilling. ceramic substrate;
a multilayer wiring layer disposed on the ceramic substrate and including an insulating layer and a wiring pattern layer alternately stacked at least once;
a plurality of conductive via electrodes connecting the wiring pattern layers; and
For each of the first wiring pattern layer and the second wiring pattern layer associated with the via electrode having the disconnection defect to replace the via electrode having the disconnection defect among the plurality of conductive via electrodes, the first wiring pattern layer from the uppermost insulating layer A conductive wiring structure connected on an uppermost insulating layer while filling a first via hole and a second via hole exposing an upper surface of the second wiring pattern layer and an upper surface of the second wiring pattern layer, respectively, and filling the first via hole and the second via hole A space transducer for a probe card comprising a bypass conductive path comprising: 12. The method of claim 11,
The conductive wiring structure is a space converter for a probe card of copper (Cu) or silver (Ag). 12. The method of claim 11,
The insulating layer is a polyimide resin, polyphenylene sulfide resin, polyester resin, BCB (Benzocyclobutene) resin, epoxy resin, bismaleimide triazine resin, polyphenylene ether resin, polyquinoline resin, fluororesin or a space converter for a probe card comprising a combination thereof. 12. The method of claim 11,
The ceramic substrate is a LTCC (Low Temperature Co-Fired Ceramic) substrate, a space converter for a probe card. 12. The method of claim 11,
A space transducer for a probe card having a depth of the first via hole or the second via hole in a range of 10 μm to 50 μm. 12. The method of claim 11,
A space transducer for a probe card having a diameter of the first via hole or the second via hole in a range of 20 μm to 100 μm.

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