CN112234045A - 包括桥式晶片的半导体封装 - Google Patents

包括桥式晶片的半导体封装 Download PDF

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Publication number
CN112234045A
CN112234045A CN201911219865.6A CN201911219865A CN112234045A CN 112234045 A CN112234045 A CN 112234045A CN 201911219865 A CN201911219865 A CN 201911219865A CN 112234045 A CN112234045 A CN 112234045A
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China
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package
semiconductor
wafer
sub
bridge
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CN201911219865.6A
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Chinese (zh)
Inventor
任尚赫
成基俊
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SK Hynix Inc
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SK Hynix Inc
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Publication of CN112234045A publication Critical patent/CN112234045A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
CN201911219865.6A 2019-07-15 2019-12-03 包括桥式晶片的半导体封装 Pending CN112234045A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020190085391A KR102687751B1 (ko) 2019-07-15 2019-07-15 브리지 다이를 포함한 반도체 패키지
KR10-2019-0085391 2019-07-15

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CN112234045A true CN112234045A (zh) 2021-01-15

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KR (1) KR102687751B1 (ko)
CN (1) CN112234045A (ko)
TW (1) TWI844580B (ko)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI781009B (zh) * 2021-12-15 2022-10-11 力晶積成電子製造股份有限公司 半導體封裝及其製造方法

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030017647A1 (en) * 2001-07-19 2003-01-23 Samsung Electronics Co., Ltd. Wafer level stack chip package and method for manufacturing same
US20100133704A1 (en) * 2008-12-01 2010-06-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias
US20120306075A1 (en) * 2011-05-31 2012-12-06 Kim Tae-Hun Semiconductor package apparatus
CN104364902A (zh) * 2012-05-25 2015-02-18 Nepes株式会社 半导体封装、其制造方法及封装体叠层
US20160043047A1 (en) * 2014-08-07 2016-02-11 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Double-Sided Fan-Out Wafer Level Package
CN106169466A (zh) * 2015-05-19 2016-11-30 联发科技股份有限公司 半导体封装组件及其制造方法
US20170011993A1 (en) * 2015-07-09 2017-01-12 Broadcom Corporation Thin Recon Interposer Package Without TSV for Fine Input/Output Pitch Fan-Out
CN106952879A (zh) * 2016-01-06 2017-07-14 爱思开海力士有限公司 包括贯通式模具连接器的半导体封装件及其制造方法
CN108122863A (zh) * 2016-11-29 2018-06-05 台湾积体电路制造股份有限公司 半导体结构及其制造方法
CN108630551A (zh) * 2017-03-19 2018-10-09 南亚科技股份有限公司 半导体结构及其形成方法
US20190131241A1 (en) * 2017-10-31 2019-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Package with fan-out structures
US20190139784A1 (en) * 2017-11-08 2019-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of fabricating the same

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3059560B2 (ja) * 1991-12-25 2000-07-04 株式会社日立製作所 半導体装置の製造方法およびそれに使用される成形材料
KR101362715B1 (ko) * 2012-05-25 2014-02-13 주식회사 네패스 반도체 패키지, 그 제조 방법 및 패키지 온 패키지
US9768090B2 (en) * 2014-02-14 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030017647A1 (en) * 2001-07-19 2003-01-23 Samsung Electronics Co., Ltd. Wafer level stack chip package and method for manufacturing same
US20100133704A1 (en) * 2008-12-01 2010-06-03 Stats Chippac, Ltd. Semiconductor Device and Method of Forming an Interposer Package with Through Silicon Vias
US20120306075A1 (en) * 2011-05-31 2012-12-06 Kim Tae-Hun Semiconductor package apparatus
CN104364902A (zh) * 2012-05-25 2015-02-18 Nepes株式会社 半导体封装、其制造方法及封装体叠层
US20160043047A1 (en) * 2014-08-07 2016-02-11 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Double-Sided Fan-Out Wafer Level Package
CN106169466A (zh) * 2015-05-19 2016-11-30 联发科技股份有限公司 半导体封装组件及其制造方法
US20170011993A1 (en) * 2015-07-09 2017-01-12 Broadcom Corporation Thin Recon Interposer Package Without TSV for Fine Input/Output Pitch Fan-Out
CN106952879A (zh) * 2016-01-06 2017-07-14 爱思开海力士有限公司 包括贯通式模具连接器的半导体封装件及其制造方法
CN108122863A (zh) * 2016-11-29 2018-06-05 台湾积体电路制造股份有限公司 半导体结构及其制造方法
CN108630551A (zh) * 2017-03-19 2018-10-09 南亚科技股份有限公司 半导体结构及其形成方法
US20190131241A1 (en) * 2017-10-31 2019-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Package with fan-out structures
US20190139784A1 (en) * 2017-11-08 2019-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method of fabricating the same

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TWI844580B (zh) 2024-06-11
TW202117997A (zh) 2021-05-01
KR20210008780A (ko) 2021-01-25
KR102687751B1 (ko) 2024-07-23

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