CN112234045A - Semiconductor package including bridge die - Google Patents

Semiconductor package including bridge die Download PDF

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Publication number
CN112234045A
CN112234045A CN201911219865.6A CN201911219865A CN112234045A CN 112234045 A CN112234045 A CN 112234045A CN 201911219865 A CN201911219865 A CN 201911219865A CN 112234045 A CN112234045 A CN 112234045A
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China
Prior art keywords
package
semiconductor
wafer
sub
bridge
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CN201911219865.6A
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Chinese (zh)
Inventor
任尚赫
成基俊
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SK Hynix Inc
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SK Hynix Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto

Abstract

A semiconductor package including a bridge die is provided. A semiconductor package includes first and second semiconductor dies, first and second redistribution line structures, a first bridge die, and a vertical connector. The first semiconductor die and the first bridge die are disposed on the first redistribution line structure. The first bridge wafer is configured to provide a level difference between the first semiconductor wafer and the first bridge wafer, the first bridge wafer having a height that is less than a height of the first semiconductor wafer. The second redistribution line structure has a protrusion that protrudes laterally from a side surface of the first semiconductor wafer when viewed in a plan view, and a bottom surface of the second redistribution line structure is in contact with a top surface of the first semiconductor wafer. A second semiconductor wafer is disposed on the second redistribution line structure. The vertical connector is disposed between the bridge wafer and the protrusion of the second redistribution line structure to support the protrusion.

Description

Semiconductor package including bridge die
Technical Field
Various embodiments of the present disclosure relate generally to semiconductor packaging technology and, more particularly, to a semiconductor package including a bridge die.
Background
Recently, semiconductor packages having high density and capable of high-speed operation have been required in various electronic systems. In addition, semiconductor packages have been developed that have structures with relatively small form factors. In order to realize these semiconductor packages, a great deal of effort has been focused on the flip-chip stacking technique. In addition, in order to realize a semiconductor package with a reduced thickness, a great deal of effort has been concentrated on wafer level packaging techniques.
Disclosure of Invention
According to one embodiment, a semiconductor package includes: a first semiconductor die disposed on the first redistribution line structure; a first bridge wafer disposed on the first redistribution line structure to provide a level difference between the first semiconductor wafer and the first bridge wafer, the first bridge wafer having a height less than a height of the first semiconductor wafer; and a second redistribution line structure stacked on the first semiconductor wafer such that a bottom surface of the second redistribution line contacts a top surface of the first semiconductor wafer. The second redistribution line structure is provided to have a protrusion that protrudes laterally from a side surface of the first semiconductor wafer when viewed in a plan view. A second semiconductor wafer is disposed on the second redistribution line structure. The vertical connector is disposed between the first bridge wafer and the protrusion of the second redistribution line structure to support the protrusion. The first bridge wafer includes a first via.
According to another embodiment, a semiconductor package includes: a first sub-package including a middle portion and a recessed edge portion, a top surface of the recessed edge portion being lower than a top surface of the middle portion. The second sub-package is stacked on the first sub-package such that a bottom surface of the second sub-package is in contact with a top surface of the middle portion of the first sub-package. The second sub-package has a protrusion vertically spaced apart from the recessed edge portion of the first sub-package. The vertical connector is disposed on the recessed edge portion to support the protruding portion of the second sub-package. The first sub-package includes: a first redistribution line structure; a first semiconductor die disposed on the first redistribution line structure; and a first bridge wafer disposed on the first redistribution line structure to provide a level difference between the first semiconductor wafer and the first bridge wafer, the first bridge wafer having a height less than a height of the first semiconductor wafer. The first bridge wafer includes a first via and a first pillar bump. The first molding layer surrounds the first bridge wafer and the first semiconductor wafer to expose top surfaces of the first pillar bumps. The vertical connector is connected to the first stud bump.
Drawings
Fig. 1, 2 and 3 are sectional views illustrating a semiconductor package according to an embodiment.
Fig. 4 and 5 are plan views illustrating a semiconductor package according to an embodiment.
Fig. 6 is a sectional view illustrating a semiconductor package according to an embodiment.
Fig. 7 is a sectional view illustrating a semiconductor package according to an embodiment.
Fig. 8 is a sectional view illustrating a semiconductor package according to an embodiment.
Fig. 9 is a sectional view illustrating a semiconductor package according to an embodiment.
Fig. 10 is a sectional view illustrating a sub-package of a semiconductor package according to an embodiment.
Fig. 11 is a plan view illustrating a sub-package of a semiconductor package according to an embodiment.
Fig. 12 is a cross-sectional view illustrating a bridge wafer of a semiconductor package according to an embodiment.
Fig. 13 is a sectional view illustrating a sub-package of a semiconductor package according to an embodiment.
Fig. 14 is a sectional view illustrating a semiconductor package according to an embodiment.
Fig. 15 is an enlarged view of a bridge wafer included in the semiconductor package of fig. 14.
Fig. 16 is a sectional view illustrating a semiconductor package according to an embodiment.
Fig. 17 is a block diagram illustrating an electronic system employing a memory card including at least one semiconductor package according to various embodiments.
Fig. 18 is a block diagram illustrating another electronic system including at least one semiconductor package according to various embodiments.
Detailed Description
Terms used herein may correspond to words selected in consideration of their functions in the embodiments of the present disclosure, and the meanings of the terms may be construed to be different according to those of ordinary skill in the art to which the embodiments of the present disclosure belong. If defined in detail, the terms may be construed in accordance with the definition. Unless defined otherwise, terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of the present disclosure belong.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and are not used to define the elements themselves or to imply a particular order.
It will also be understood that when an element or layer is referred to as being "on," "over," "under," "beneath," or "external" to another element or layer, it can be directly in contact with the other element or layer or intervening elements or layers may be present. Other words used to describe the relationship between elements or layers should be interpreted in a similar fashion (e.g., "between …" and "directly between …" or "adjacent" and "directly adjacent").
Spatially relative terms such as "below …," "below …," "below …," "above …," "above …," "top," "bottom," and the like may be used to describe one element and/or feature's relationship to another element and/or feature as illustrated, for example, in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and/or operation in addition to the orientation depicted in the figures. For example, when the device in the figures is turned over, elements described as below or beneath other elements or features would then be oriented above the other elements or features. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
A semiconductor package may include an electronic device such as a semiconductor die or a semiconductor die. A semiconductor chip or semiconductor chip can be obtained by dividing a semiconductor substrate such as a wafer into pieces using a die sawing process. The semiconductor wafer may correspond to a memory chip, a logic chip (including an Application Specific Integrated Circuit (ASIC) chip), or a system on a chip (SoC). The memory chip may include a Dynamic Random Access Memory (DRAM) circuit, a Static Random Access Memory (SRAM) circuit, a NAND-type flash memory circuit, a NOR-type flash memory circuit, a Magnetic Random Access Memory (MRAM) circuit, a resistive random access memory (ReRAM) circuit, a ferroelectric random access memory (FeRAM) circuit, or a phase change random access memory (PcRAM) circuit integrated on a semiconductor substrate. The logic chip may include logic circuitry integrated on a semiconductor substrate. The semiconductor package may be employed in a communication system such as a mobile phone, an electronic system associated with biotechnology or healthcare, or a wearable electronic system.
Like reference numerals refer to like elements throughout the specification. A reference number may be referred to or described with reference to another figure even if the reference number is not referred to or described with reference to one figure. In addition, even if a reference numeral is not shown in one drawing, the reference numeral may be referred to or described with reference to another drawing.
Fig. 1, 2 and 3 are sectional views illustrating a semiconductor package 10 according to an embodiment. Fig. 4 and 5 are plan views illustrating the semiconductor package 10 of fig. 1 to 3. Fig. 1 is a sectional view taken along line X1-X1' of fig. 4 and 5. Fig. 2 is an enlarged sectional view taken partially along line X1-X1' of fig. 4 and 5. Fig. 3 is an enlarged sectional view taken partially along line X2-X2' of fig. 4 and 5. Fig. 4 is a plan view taken at the level of the first surface 101 of the semiconductor wafer 100 included in the semiconductor package 10 of fig. 1. The dielectric layer 390 and the connector 600 illustrated in fig. 1 are omitted in fig. 4 for the purpose of easy and convenient explanation. Fig. 5 is a plan view taken at the level of the second surface 102 of the semiconductor wafer 100 included in the semiconductor package 10 of fig. 1.
Referring to fig. 1, a semiconductor package 10 may be configured to include a semiconductor die 100, a bridge die 200, and redistribution lines 300. The bridge wafer 200 may be disposed spaced apart from the semiconductor wafer 100 in plan view. The bridge wafer 200 may include one wafer disposed on only one side of the semiconductor wafer 100, or may include two wafers disposed on both sides of the semiconductor wafer 100, respectively. Each of the redistribution lines 300 may be configured to include a conductive pattern that electrically connects the semiconductor wafer 100 to the bridge wafer 200. The semiconductor package 10 may also include conductive pillar bumps 400 and a mold layer 500 attached to the bridge wafer 200. In addition, the semiconductor package 10 may further include connectors 600, each of the connectors 600 being connected to a portion of each of the redistribution lines 300. The dielectric layer 390 may be disposed to cover the redistribution lines 300 to electrically insulate the redistribution lines 300 from each other.
Referring to fig. 1 and 2, the semiconductor wafer 100 may have a first surface 101 on which a dielectric layer 390 is disposed, a second surface 102 located opposite the dielectric layer 390, and a second side surface 103 extending from an edge of the first surface 101 to an edge of the second surface 102. The first surface 101 of the semiconductor wafer 100 may correspond to an active surface on which integrated circuits are disposed. The second surface 102 of the semiconductor wafer 100 may correspond to a bottom or back side surface of the semiconductor wafer 100 opposite the active surface. The terms "first" and "second" in the first surface 101 and the second surface 102 are only used to distinguish the surfaces from each other, and are not used to mean a particular order of the surfaces.
Contact pads 110 may be provided on the first surface 101 of the semiconductor wafer 100. The contact pads 110 may be conductive patterns used as paths for electrically connecting the semiconductor wafer 100 to an external device or system. The contact pads 110 may be intermediate pads arranged in an intermediate region 121 of the semiconductor wafer 100, as illustrated in fig. 4. The contact pads 110 may be arranged in two columns on the first surface 101 of the intermediate region 121. The semiconductor wafer 100 may include a middle region 121 and two edge regions 123 respectively located at both sides of the middle region 121.
Referring to fig. 2, the bridge wafer 200 may be disposed spaced apart from the second side surface 103 of the semiconductor wafer 100. The bridge wafer 200 may have third and fourth surfaces 201 and 202 opposite to each other and third and fourth side surfaces 203 and 204 opposite to each other. The bridge wafer 200 may be disposed such that the third surface 201 of the bridge wafer 200 faces in the same direction as the first surface 101 of the semiconductor wafer 100. The third surface 201 of the bridge wafer 200 may be coplanar with the first surface 101 of the semiconductor wafer 100. That is, the third surface 201 of the bridge wafer 200 may be located at substantially the same level as the first surface 101 of the semiconductor wafer 100.
Referring to fig. 2 and 4, the bridge wafer 200 may be disposed beside the semiconductor wafer 100 such that the third side surface 203 of the bridge wafer 200 faces the second side surface 103 of the semiconductor wafer 100. The bridge wafer 200 may be spaced apart from the semiconductor wafer 100 by a distance S.
Referring to fig. 2, there may be a level difference H between the fourth surface 202 of the bridge wafer 200 and the second surface 102 of the semiconductor wafer 100. The bridge wafer 200 may be disposed beside the semiconductor wafer 100 such that the fourth surface 202 of the bridge wafer 200 and the second surface 102 of the semiconductor wafer 100 form a stepped structure. The bridge wafer 200 may be thinner than the semiconductor wafer 100. A thickness T1 (also referred to as a first thickness) corresponding to a distance between the third surface 201 and the fourth surface 202 of the bridge wafer 200 may be less than a thickness T2 (also referred to as a second thickness) corresponding to a distance between the first surface 101 and the second surface 102 of the semiconductor wafer 100. In one embodiment, the thickness T1 of bridge wafer 200 may be approximately half the thickness T2 of semiconductor wafer 100.
The bridge wafer 200 may include a through-hole 210, the through-hole 210 penetrating through a body of the bridge wafer 200 to extend from the third surface 201 to the fourth surface 202. The body of the bridge wafer 200 may comprise a semiconductor material such as a silicon material. If the body of the bridge wafer 200 comprises a silicon material, a silicon processing technique may be used to form the vias 210. In this case, the via 210 may be a Through Silicon Via (TSV) (also referred to as a first diameter in this specification) having a relatively fine diameter D1. The via 210 may be formed of a conductive metal material (e.g., a metal material including a copper material).
Since the thickness T1 of the bridge wafer 200 is relatively small compared to the thickness T2 of the semiconductor wafer 100, the length (corresponding to the height) of the via 210 may be relatively short. For example, if bridge wafer 200 is replaced with a thick bridge wafer having substantially the same thickness as semiconductor wafer 100, the length of the through-hole penetrating the thick bridge wafer may be greater than the length of through-hole 210. However, according to an embodiment, the via hole 210 may be formed to penetrate the bridge wafer 200 thinner than the semiconductor wafer 100. Accordingly, the through-hole 210 may be formed to have a relatively short length. In order to form a via penetrating through a thick bridge wafer and having a fine diameter, it may be necessary to increase the aspect ratio of the full via of the via. There may be a limit to increasing the aspect ratio of the full via without increasing the diameter of the full via. That is, if the length of the through-hole is increased, the diameter of the through-hole may also be increased. However, according to the depicted embodiment, the thickness T1 of the bridge wafer 200 may have a relatively small value. Accordingly, the through-hole 210 penetrating the bridge wafer 200 may be formed to have a relatively short length with a fine diameter D1. Therefore, the number of the through holes 210 provided in the bridge wafer 200 can be increased because the through holes 210 are formed to have the fine diameter D1.
Referring to fig. 2, conductive pillar bumps 400 may be disposed to protrude from the fourth surface 202 of the bridge wafer 200. The conductive pillar bumps 400 may be electrically connected to the vias 210, respectively. The conductive pillar bumps 400 may be disposed to overlap the through-holes 210, respectively, in a plan view. The conductive pillar bumps 400 may protrude from the fourth surface 202 of the bridge wafer 200 such that a side surface of the first side surface 401 of each of the conductive pillar bumps 400 faces an upper portion of the second side surface 103 of the semiconductor wafer 100.
The semiconductor package 10 may include a mold layer 500 covering the fourth surface 202 of the bridge wafer 200. The mold layer 500 may be formed to cover the fourth surface 202 of the bridge wafer 200. The mold layer 500 may be formed to surround the side surfaces of the conductive pillar bump 400. The mold layer 500 may be formed to directly cover the first side surface 401 of the conductive pillar bump 400. The mold layer 500 may be formed to expose the top surface 402 of the conductive pillar bump 400. The top surface 402 of the conductive pillar bump 400 may be coplanar with the top surface 501 of the mold layer 500.
Other connectors (not illustrated) may be attached or connected to the top surface 402 of the conductive pillar bump 400 to electrically connect the conductive pillar bump 400 to another semiconductor package or an external device. The conductive pillar bump 400 may be surrounded by a mold layer 500. The conductive pillar bumps 400 may substantially penetrate the portion of the mold layer 500 covering the fourth surface 202 of the bridge wafer 200. Thus, the conductive pillar bump 400 may act as an extension line for extending the electrical path of the via 210 up to the top surface 501 of the mold layer 500.
Although the spaces between the vias 210 are filled with a semiconductor material such as a silicon material, the spaces between the conductive pillar bumps 400 may be filled with a dielectric layer such as a mold layer 500 containing an Epoxy Molding Compound (EMC) material.
Since the via holes 210 penetrate the body of the bridge wafer 200 including the semiconductor material, the impedance component of each of the via holes 210 may be increased as compared to the case where the via holes 210 penetrate the insulating substrate. In addition, if the through holes 210 are disposed in a limited area or a limited space, the distance between the through holes 210 may be reduced, thereby causing a crosstalk phenomenon due to a noise signal occurring more frequently. When the semiconductor package operates at a high frequency, the crosstalk phenomenon may affect a signal transmission characteristic or a signal integrity characteristic of the semiconductor package. According to the described embodiment, the space between the pillar bumps 400 may be filled with a dielectric material, for example, an Epoxy Molding Compound (EMC) material. Therefore, even if the via hole 210 is provided to penetrate the bridge wafer 200 including the semiconductor material, since the dielectric material (i.e., the mold layer 500) filling the space between the pillar bumps 400 is present, it is possible to improve suppression of the overall crosstalk phenomenon of the semiconductor package 10. For example, a silicon material may have a dielectric constant of about 11.68 at room temperature and at a frequency of 1.0kHz, while an EMC material may have a dielectric constant of about 3.7 at room temperature and at a frequency of 1.0 kHz. Such a difference in dielectric constant between the bridge wafer 200 and the mold layer 500 may affect electrical characteristics such as signal transmission characteristics or signal integrity characteristics of the semiconductor package 10.
Each of the stud bumps 400 may have a second diameter D2 that is greater than the first diameter D1 of each of the through-holes 210. Since the first diameter D1 of each of the through-holes 210 is smaller than the second diameter D2 of each of the pillar bumps 400 connected to the through-holes 210, the distance between the through-holes 210 may be relatively larger than the distance between the pillar bumps 400. That is, the pillar bumps 400 may be disposed such that the distance between the pillar bumps 400 is smaller than the distance between the through-holes 210. For example, the distance between adjacent pillar bumps may be less than the distance between corresponding adjacent vias. In addition, the spaces between the pillar bumps 400 may be filled with a dielectric material, and the spaces between the through-holes 210 may be filled with a semiconductor material. Since the distance between the through holes 210 may be relatively greater than the distance between the pillar bumps 400, noise generated due to interference between signals transmitted through the adjacent through holes 210 can be reduced.
As described above, in order to reduce noise generated due to interference between signals transmitted through adjacent through holes 210, it may be necessary to increase the distance between the through holes 210. To increase the distance between the vias 210 without changing the pitch size of the vias 210, it may be desirable to decrease the first diameter D1. To form the via 210 having the first diameter D1 corresponding to a fine diameter smaller than the second diameter D2 penetrating the bridge wafer 200, it may be desirable to reduce the thickness T1 of the bridge wafer 200. According to an embodiment, bridge wafer 200 may be configured to have a thickness T1 that is less than a thickness T2 of semiconductor wafer 100. Accordingly, each of the vias 210 may be formed to have a Through Silicon Via (TSV) shape. As a result, the distance between the through holes 210 can be increased to suppress noise generated due to interference between signals transmitted through adjacent through holes 210.
Each of the pillar bumps 400 may have the shape of a metal pillar including a copper material. The length L (i.e., height) of the pillar bump 400 may be less than the second diameter D2 of the pillar bump 400. For example, the length L of each of the pillar bumps 400 may be about 60 microns. The length L of the pillar bump 400 may be substantially the same as the first thickness T1 of the bridge wafer 200. For example, the first thickness T1 of the bridge wafer 200 may be about 50 microns. Each of the pillar bumps 400 may have a second diameter D2 of about 100 microns. In contrast, the first diameter D1 of each of the vias 210 may be about 0.5 microns. Since the pillar bump 400 is formed to have a relatively large diameter (i.e., the second diameter D2) compared to the through-hole 210, a connector (not illustrated) such as a solder bump may be directly connected to each top surface 402 of the pillar bump 400. Therefore, an additional conductive pad for increasing a contact area between a connector (not illustrated) and the top surface 402 of the pillar bump 400 is not required.
The mold layer 500 may extend to fill the space between the second side surface 103 of the semiconductor wafer 100 and the first side surface 401 of the pillar bump 400. The mold layer 500 may extend to cover substantially the entire portion of the second side surface 103 of the semiconductor wafer 100. The mold layer 500 may also extend to cover the third side surface 203 of the bridge wafer 200 facing the second side surface 103 of the semiconductor wafer 100. The mold layer 500 may also extend to fill the space between the second side surface 103 of the semiconductor wafer 100 and the third side surface 203 of the bridge wafer 200.
Referring to fig. 2 and 5, the mold layer 500 may be formed to expose the second surface 102 of the semiconductor wafer 100. The second surface 102 of the semiconductor wafer 100 may be coplanar with the top surface 501 of the mold layer 500. That is, the top surface 501 of the mold layer 500 may be located at substantially the same level as the second surface 102 of the semiconductor wafer 100. The top surfaces 402 of the pillar bumps 400 may be coplanar with the second surface 102 of the semiconductor wafer 100. Since the mold layer 500 is formed to expose the second surface 102 of the semiconductor wafer 100, the total thickness of the semiconductor package 10 may have a reduced thickness as compared to a case where the mold layer 500 is formed to cover the entire portion of the semiconductor wafer 100.
The mold layer 500 may be formed to expose a fourth side surface 204 of the bridge wafer 200 opposite the semiconductor wafer 100. The heat radiation efficiency of the semiconductor package 10 may be improved by forming the mold layer 500 to expose the fourth side surface 204 of the bridge wafer 200. The fourth side surface 204 of the bridge wafer 200 and the second surface 102 of the semiconductor wafer 100 exposed by the mold layer 500 may serve as a heat radiation path for the semiconductor package 10.
The mold layer 500 may cover the third side surface 203 of the bridge wafer 200 and the second side surface 103 of the semiconductor wafer 100, and may extend to cover the fourth surface 202 of the bridge wafer 200 and the first side surfaces 401 of the pillar bumps 400. Accordingly, the bonding force of the mold layer 500 to the bridge wafer 200 can be improved because the pillar bump 400 is coupled to the through-hole 210 and the mold layer 500 extends to surround the first side surface 401 of the pillar bump 400.
Referring again to fig. 2 and 4, the semiconductor package 10 may further include a redistribution line 300. The redistribution line 300 may be provided to electrically connect the semiconductor wafer 100 to the via 210. Each of the redistribution lines 300 may include a conductive pattern that electrically connects one of the contact pads 110 of the semiconductor wafer 100 to any one of the vias 210. The redistribution line 300 may be formed to include a metal material such as an aluminum (Al) material, a copper (Cu) material, a gold (Au) material, or the like.
Each of the redistribution lines 300 may include a pad overlapping portion 310, an extension line 320 or 330+340, and a via pad 370. The extension lines 320 and 330+340 may include a first extension line 320, a second extension line 330, and a third extension line 340. The pad overlapping portion 310 may be bonded to any one of the contact pads 110 of the semiconductor wafer 100. The pad overlapping portion 310 may contact one of the contact pads 110 of the semiconductor wafer 100 to electrically connect one of the contact pads 110 to any one of the extension lines 320, 330, and 340. The pad overlapping portion 310 may overlap any one of the contact pads 110 of the semiconductor wafer 100 to have a pad shape. The via pads 370 of the redistribution line 300 may be arranged to have a pitch size greater than a pitch size of the contact pads 110.
The via pads 370 may be conductive patterns connected to any of the vias 210 of the bridge wafer 200. First ends of the vias 210 may be respectively connected to the pillar bumps 400, and second ends of the vias 210 may be respectively connected to the via pads 370 of the redistribution lines 300. The via pads 370 of the redistribution line 300 may be disposed on the third surface 201 of the bridge wafer 200 opposite the pillar bumps 400, and the pillar bumps 400 may be disposed on the fourth surface 202 of the bridge wafer 200 opposite the via pads 370. The via 210 may correspond to a conductive pattern that electrically connects the via pad 370 to the corresponding pillar bump 400. The via pads 370 may be disposed to overlap the respective vias 210 in a plan view, and the pillar bumps 400 may be disposed to overlap the respective vias 210 in a plan view. Therefore, the via pads 370 may also be disposed to overlap the pillar bumps 400, respectively, when viewed from a plan view. The via pad 370 may be a conductive pattern having a third diameter D3 that is substantially equal to or substantially the same as the second diameter D2 of the pillar bump 400. The via pad 370 may have a third diameter D3 that is greater than the first diameter D1 of the via 210.
The via pads 370 of the redistribution lines 300 may be arranged in a plurality of columns on the third surface 201 of the bridge wafer 200. As illustrated in the plan view of fig. 4, via pads 370 may include via pad 371 arranged in a first column, via pad 372 arranged in a second column, via pad 373 arranged in a third column, via pad 375 arranged in a fourth column, and via pad 377 arranged in a fifth column. The first to fifth columns may be sequentially positioned to be gradually distant from the semiconductor wafer 100. As illustrated in fig. 4, the via pads 370 may be arranged in a checkerboard shape (i.e., a matrix form). However, the embodiment illustrated in fig. 4 may be only one of various embodiments of the present disclosure. For example, in some other embodiments, the via pads 370 in each column may be arranged in a zigzag manner along the column direction when viewed from a plan view.
The first extension line 320 of the redistribution line 300 may correspond to an extension line that electrically connects the via pads 371 arranged in the first column to the first group of pad overlapping portions 310. That is, the first extension line 320 may electrically connect the via pads 371 arranged in the first column to the first group of contact pads 110. Some of the vias 210 may be electrically connected to some of the contact pads 110 of the semiconductor wafer 100 through the via pads 371, the first extension line 320, and the first group of pad overlapping portions 310 arranged in the first column. The first extension line 320 may be a conductive pattern extending from the first surface 101 of the semiconductor wafer 100 across the mold layer 500 onto the third surface 201 of the bridge wafer 200.
Referring to fig. 3 and 4, the second extension line 330 of the redistribution line 300 may correspond to an extension line electrically connecting the via pads 372 arranged in the second column to the second group of pad overlapping portions 310. That is, the second extension line 330 may electrically connect the via pads 372 arranged in the second column to the second group of contact pads 110. Some of the vias 210 may be electrically connected to some of the contact pads 110 of the semiconductor wafer 100 through the via pads 372 arranged in the second column, the second extension line 330, and the second set of pad overlapping portions 310. The second extension line 330 may be a conductive pattern extending from the first surface 101 of the semiconductor wafer 100 across the mold layer 500 onto the third surface 201 of the bridge wafer 200. As illustrated in fig. 4, the first extension lines 320 and the second extension lines 330 may be alternately disposed.
The third extension line 340 of the redistribution line 300 may correspond to an extension line that electrically connects the via pad 372 arranged in the second column to the via pad 373 arranged in the third column. Since the third extension line 340 electrically connects the via pad 372 arranged in the second column to the via pad 373 arranged in the third column, the first via 212 coupled with the via pad 372 of the second column among the vias 210 may be electrically connected to the second via 213 coupled with the via pad 373 of the third column among the vias 210. The third extension line 340 may electrically connect the first via 212 to the second via 213 adjacent to the first via 212. The third extension line 340 may be disposed on the third surface 201 of the bridge wafer 200.
One of the first vias 212 and one of the second vias 213 may be electrically connected to any one of the second extension lines 330 through any one of the third extension lines 340. Even if the signal is abnormally transmitted through the first via 212, the signal may be normally transmitted to the second extension line 330 through the second via 213. Accordingly, a reliable signal path of the semiconductor wafer 100 included in the semiconductor package 10 can be achieved. Although the second extension line 330 provides a data signal path, the first extension line 320 may be used as a power supply line including a power voltage line and a ground voltage line.
Via pads 375 arranged in a fourth column and via pads 377 arranged in a fifth column may be disposed on the third surface 201 of the bridge wafer 200 to act as first dummy pads. That is, the via pads 375 and 377 in the fourth and fifth columns may be electrically disconnected and isolated from the first, second, and third extension lines 320, 330, and 340. Since via pad 375 in the fourth column and via pad 377 in the fifth column correspond to the first dummy pad, via 210 connected to via pad 375 in the fourth column and via pad 377 in the fifth column may also correspond to electrically insulated first dummy via 215. The pillar bump 400 connected to the first dummy via 215 may also correspond to the electrically insulating first dummy pillar bump 413. The first dummy pads 375 and 377, the first dummy via 215, and the first dummy pillar bump 413 may be provided as a redundancy preparation member.
Referring again to fig. 2, the semiconductor package 10 may include a dielectric layer 390, the dielectric layer 390 exposing the via pad 370 to cover the first, second, and third extension lines 320, 330, and 340 and the pad overlapping portion 310 to electrically insulate the extension lines 320, 330, and 340 from each other. Dielectric layer 390 may be formed to cover first surface 101 of semiconductor wafer 100, third surface 201 of bridge wafer 200, and mold layer 500 between semiconductor wafer 100 and bridge wafer 200. Dielectric layer 390 may include a solder resist layer that exposes via pad 370.
The connector 600 may be attached to the exposed through-hole pad 370 to electrically connect the semiconductor package 10 to an external device or another semiconductor package. The connector 600 may be implemented using solder bumps or balls.
Fig. 6 is a sectional view illustrating a semiconductor package 11 according to an embodiment. In fig. 6, members having the same shape as illustrated in fig. 1 to 5 represent substantially the same elements. In fig. 6, the same reference numerals as used in fig. 1 to 5 denote substantially the same elements.
Referring to fig. 6, the semiconductor package 11 may include a mold layer 500-1, the mold layer 500-1 having an expanded shape of the mold layer 500 included in the semiconductor package 10 of fig. 2. The mold layer 500-1 may surround the first side surface 401-1 of the pillar bump 400-1 and may expose the top surface 402-1 of the pillar bump 400-1. The pillar bump 400-1 may penetrate the mold layer 500-1 to have the same function as the pillar bump 400 illustrated in fig. 2. The mold layer 500-1 may cover the fourth surface 202 of the bridge wafer 200 and may extend to cover the fourth side surface 204 of the bridge wafer 200 opposite the semiconductor wafer 100. Since the mold layer 500-1 covers the fourth surface 202 of the bridge wafer 200 to protect the bridge wafer 200, the bridge wafer 200 is not exposed to the external environment. Accordingly, the mold layer 500-1 may suppress damage of the bridge wafer 200 or formation of cracks in the bridge wafer 200 due to an external environment. In addition, the mold layer 500-1 may extend to cover the second surface 102 of the semiconductor wafer 100 opposite the contact pads 110.
Fig. 7 is a sectional view illustrating the semiconductor package 12 according to the embodiment. Fig. 8 is a sectional view illustrating a semiconductor package 12-S according to an embodiment. The semiconductor package 12-S illustrated in fig. 8 may correspond to a package-on-package including a pair of semiconductor packages 12 vertically stacked. In fig. 7 and 8, members having the same shape as illustrated in fig. 1 to 5 represent substantially the same elements. In fig. 7 and 8, the same reference numerals as used in fig. 1 to 5 denote substantially the same elements.
Referring to fig. 7, the semiconductor package 12 may include a bridge die 200-2 on one side of the semiconductor die 100. Semiconductor package 12 may also include redistribution lines 300-2 that electrically connect vias 210 of bridge wafer 200-2 to contact pads 110 of semiconductor wafer 100. Dummy wafer 250 may be located on the opposite side of semiconductor wafer 100 from bridge wafer 200-2.
Unlike the bridge wafer 200-2, the dummy wafer 250 may be devoid of vias. However, a second dummy pad 370-5 may be disposed on dummy wafer 250. When the connector 600-2 is attached to a via pad 370-2 connected to a via 210 penetrating the body of the bridge wafer 200-2, the dummy connector 600-5 may be attached to a second dummy pad 370-5. The second dummy pad 370-5 may be electrically insulated from the semiconductor wafer 100. The second dummy pillar bump 400-5 disposed on the dummy wafer 250 may also be electrically insulated from the semiconductor wafer 100.
Dummy wafer 250 may correspond to a semiconductor wafer having a width W2 that is less than width W1 of bridge wafer 200-2. Therefore, the overall width W3 of the semiconductor package 12 can be reduced as compared to the case where the dummy wafer 250 has the same width as the bridge wafer 200-2. The dummy wafer 250 and the bridge wafer 200-2 may have substantially the same length in a direction perpendicular to the width direction in plan view. In other embodiments, the dummy wafer 250 may have substantially the same size as the bridge wafer 200-2. Alternatively, the dummy wafer 250 may be approximately the same size as the bridge wafer 200-2.
Referring to fig. 7 and 8, since the dummy wafer 250 and the bridge wafer 200-2 are respectively located at both sides of the semiconductor wafer 100, the semiconductor package 12 may have a stable structure due to the bump connection structure of the dummy wafer 250. Therefore, the semiconductor package 12-S can be well balanced when the first sub-package 12-1 having the same configuration as the semiconductor package 12 and the second sub-package 12-2 having the same configuration as the semiconductor package 12 are vertically stacked to provide the semiconductor package 12-S.
The first sub-package 12-1 and the second sub-package 12-2 may be physically coupled to each other and may be electrically connected to each other through the connector 600-2. In this case, the second dummy pillar bump 400-5 disposed on the dummy wafer 250-1 of the first sub-package 12-1 may be bonded to the second dummy pad 370-5 disposed on the dummy wafer 250-2 of the second sub-package 12-2 using the dummy connector 600-5. The dummy connector 600-5, the second dummy pillar bump 400-5, the second dummy pad 370-5, and the dummy wafers 250-1 and 250-2 may act as a balancer for preventing the second sub-package 12-2 from tilting. That is, the dummy connector 600-5, the second dummy pillar bump 400-5, the second dummy pad 370-5, and the dummy wafers 250-1 and 250-2 may be introduced to maintain balance when the second sub-package 12-2 is stacked on the first sub-package 12-1. Accordingly, the dummy connector 600-5, the second dummy pillar bump 400-5, the second dummy pad 370-5, and the dummy wafers 250-1 and 250-2 may provide a symmetric structure of the semiconductor package 12-S to prevent physical defects of the semiconductor package 12-S due to the asymmetric structure of the semiconductor package 12-S.
Fig. 9 is a sectional view illustrating the semiconductor package 13 according to the embodiment. In fig. 9, members having the same shape as illustrated in fig. 1 to 5 represent substantially the same elements. In fig. 9, the same reference numerals as used in fig. 1 to 5 denote substantially the same elements.
Referring to fig. 9, the semiconductor package 13 may be configured to include a plurality of sub-packages (i.e., a first sub-package 10-1, a second sub-package 10-2, a third sub-package 10-3, and a fourth sub-package 10-4) vertically stacked on a package substrate 700. The package substrate 700 may include an interconnect structure layer, such as a Printed Circuit Board (PCB) or an interposer, with circuit interconnect lines. Although fig. 9 illustrates an example in which the semiconductor package 13 includes the first sub-package 10-1, the second sub-package 10-2, the third sub-package 10-3, and the fourth sub-package 10-4, the number of sub-packages may be set to be different according to various embodiments. An external connector 750 may be attached to the package substrate 700 to electrically connect the semiconductor package 13 to another electronic system.
Each of the first sub-package 10-1, the second sub-package 10-2, the third sub-package 10-3, and the fourth sub-package 10-4 may have substantially the same configuration as the semiconductor package 10 described with reference to fig. 1 to 5. Each of the first sub-package 10-1, the second sub-package 10-2, the third sub-package 10-3, and the fourth sub-package 10-4 may be configured to include a semiconductor wafer 100, a pair of bridge wafers 200 respectively disposed at both sides of the semiconductor wafer 100, pillar bumps 400, a mold layer 500 (hereinafter, referred to as a first mold layer), and redistribution lines 300. The first sub-package 10-1, the second sub-package 10-2, the third sub-package 10-3, and the fourth sub-package 10-4 may be electrically connected to each other through a connector 600. The connector 600 may electrically connect the via pads 370 of the upper sub-package (e.g., the second sub-package 10-2) to the pillar bumps 400 of the lower sub-package (e.g., the first sub-package 10-1). The connector 600 may be directly bonded to the pillar bump 400 of the lower sub-package (e.g., the first sub-package 10-1). The top surface 402 of each of the pillar bumps 400 may have an area sufficient to contact any of the connectors 600. Therefore, no additional conductive pad may be required on the pillar bump 400.
The semiconductor package 13 may further include a second mold layer 500-3 covering and protecting the stacked structure of the first sub-package 10-1, the second sub-package 10-2, the third sub-package 10-3, and the fourth sub-package 10-4. The second mold layer 500-3 may extend to fill the space between the first sub-package 10-1, the second sub-package 10-2, the third sub-package 10-3, and the fourth sub-package 10-4. The second mold layer 500-3 may contain an encapsulant material such as an Epoxy Molding Compound (EMC) material.
The semiconductor package 13 in fig. 9 illustrates an example in which the semiconductor package 10 of fig. 1 is used in a module package or as a sub-package capable of being stacked in a stack package. The bridge wafer (200 in fig. 1) of the semiconductor package (10 in fig. 1) may provide a vertical interconnection structure for electrically connecting the vertically stacked first sub-package 10-1, second sub-package 10-2, third sub-package 10-3, and fourth sub-package 10-4 to each other. The semiconductor package 11 or 12 illustrated in fig. 6 or 7 may also be used as a sub-package constituting a package-on-package such as the semiconductor package 13 in fig. 9.
As described above, the semiconductor package 13 in fig. 9 may employ the semiconductor package 10 of fig. 1 as each of the sub-packages vertically stacked to constitute the semiconductor package 13. Therefore, the semiconductor package 13 can provide a compact package having a large capacity.
According to various embodiments, a semiconductor package 10 may be provided that includes a semiconductor die 100 and a bridge die 200 spaced apart from the semiconductor die 100. In addition, the semiconductor package 10 including the semiconductor wafer 100 and the bridge wafer 200 spaced apart from the semiconductor wafer 100 may be used as each of a plurality of sub-packages vertically stacked to provide the semiconductor package 13 corresponding to the stacked package.
Fig. 10 is a cross-sectional view illustrating a first sub-package 1010 of a semiconductor package according to an embodiment.
Referring to fig. 10, according to an embodiment, a first sub-package 1010 may be a unit component of a semiconductor package. The unit components (e.g., the first sub-package 1010) may be repeatedly and vertically stacked to form a semiconductor package. The first sub-package 1010 may be configured to include a first redistribution line structure 1100, a first semiconductor wafer 1200, a first bridge wafer 1300, and a first molding layer 1400. In the following description, the terms "first," "second," and the like are used only to distinguish one element from another, and are not used to denote a particular order of elements.
The first semiconductor die 1200 may be disposed on the first redistribution line structure 1100. The first redistribution line structure 1100 may comprise a top surface 1102 and a bottom surface 1101, which are opposite to each other. The first semiconductor wafer 1200 may also include a bottom surface 1201 and a top surface 1202 opposite each other. The first semiconductor die 1200 may be mounted on the first redistribution line structure 1100 such that the bottom surface 1201 of the first semiconductor die 1200 faces the top surface 1102 of the first redistribution line structure 1100. The first semiconductor die 1200 may be electrically connected to the first redistribution structure 1100.
The first bridge wafer 1300 may be disposed on the first redistribution line structure 1100. The first bridge wafer 1300 may be disposed laterally spaced apart from the first semiconductor wafer 1200. In this case, the first bridge wafer 1300 may be disposed on both sides of the first semiconductor wafer 1200, respectively. The first redistribution line structure 1100 may be extended to have an extension laterally protruding from a side surface of the first semiconductor wafer 1200 when viewed from a plan view. The first bridge wafer 1300 may be disposed on an extension of the first redistribution line structure 1100.
The first molding layer 1400 may be formed to cover a portion of the top surface 1102 of the first redistribution line structure 1100. The first molding layer 1400 may extend to contact the top surface 1102 of the first redistribution line structure 1100. The first molding layer 1400 may fix the first semiconductor wafer 1200 and the first bridge wafer 1300. The first molding layer 1400 may extend to partially cover the side surface 1203 of the first semiconductor wafer 1200. The first molding layer 1400 may surround the side surface 1203 of the first semiconductor wafer 1200.
The first molding layer 1400 may be disposed to expose an upper portion 1203U of a side surface 1203 of the first semiconductor wafer 1200. The first molding layer 1400 may be disposed to expose a top surface 1202 of the first semiconductor wafer 1200. Since the first molding layer 1400 is disposed to expose the upper portion 1203U of the side surface 1203 of the first semiconductor wafer 1200 and the entire portion of the top surface 1202 of the first semiconductor wafer 1200, heat generated by the operation of the first semiconductor wafer 1200 can be more easily dissipated from the first semiconductor wafer 1200 toward the outer region of the first semiconductor wafer 1200. Accordingly, the performance degradation of the first semiconductor wafer 1200 due to the heat confined in the first semiconductor wafer 1200 can be suppressed or prevented.
The first molding layer 1400 may extend to fill a space between the first semiconductor wafer 1200 and the first bridge wafer 1300. The first molding layer 1400 may extend to partially surround a side surface of the first bridge wafer 1300.
The first molding layer 1400 may be formed to include one of various types of encapsulation materials or any one of various types of dielectric materials. For example, the first molding layer 1400 may be formed using an Epoxy Molding Compound (EMC) material using a molding process. After forming the EMC layer to cover the first semiconductor wafer 1200 and the first bridge wafer 1300, the EMC layer may be recessed (accessed) to expose the top surface 1202 of the first semiconductor wafer 1200.
The EMC layer covering the first semiconductor wafer 1200 and the first bridge wafer 1300 may be recessed by partially etching the EMC layer, thereby exposing an upper portion 1203U of the side surface 1203 of the first semiconductor wafer 1200. The first molding layer 1400 may be recessed to expose top surfaces 1340U of the first pillar bumps 1340 included in each of the first bridge wafers 1300.
Unlike a Printed Circuit Board (PCB) or a silicon interposer (interposer), the first redistribution structure 1100 may directly contact the first semiconductor wafer 1200, the first bridge wafer 1300, and the first molding layer 1400. The first redistribution line structure 1100 may have a multi-layered structure including a first dielectric layer 1110, a second dielectric layer 1120, and a first redistribution line pattern 1130 disposed between the first dielectric layer 1110 and the second dielectric layer 1120.
The structure (i.e., the first redistribution line structure 1100) integrated with the first dielectric layer 1110, the first redistribution wiring pattern 1130, and the second dielectric layer 1120 may be in direct contact with the bottom surface of the structure including the first semiconductor wafer 1200, the first bridge wafer 1300, and the first molding layer 1400. In this way, since the first redistribution line structure 1100 has a stacked structure, the first sub-package 1010 may have a relatively thin structure compared to a case where the first redistribution line structure 1100 is replaced by a PCB or an interposer.
The first redistribution line structure 1100 may serve as an interconnect structure electrically connecting the first semiconductor die 1200 to the first bridge die 1300. The first redistribution wiring pattern 1130 of the first redistribution line structure 1100 may be a conductive pattern for electrically connecting the first connection pad 1210 of the first semiconductor wafer 1200 to the first via pad 1320 of the first bridge wafer 1300. The first connection pads 1210 of the first semiconductor wafer 1200 may be electrical connection terminals disposed on the bottom surface 1201 of the first semiconductor wafer 1200. The first via pads 1320 of the first bridge wafer 1300 may be electrical connection terminals disposed on a bottom surface of the first bridge wafer 1300 (i.e., the bottom surface 1311 of the first body 1310 of the first bridge wafer 1300).
A first end of the first re-distribution wiring pattern 1130 may be bonded to the first connection pad 1210, and a second end of the first re-distribution wiring pattern 1130 may be bonded to the first via pad 1320. The first redistribution wiring pattern 1130 may be formed by depositing a conductive material on the first dielectric layer 1110 and by patterning the conductive material using an etching process. Alternatively, the first redistribution wiring pattern 1130 may be formed by an electroplating process. The first redistribution wiring pattern 1130 may be formed to include a metal layer such as a copper layer.
The first redistribution line structure 1100 may also serve as an interconnection structure for electrically connecting the first semiconductor wafer 1200 to an external device, an external substrate, or an external module. The external connector 1500 may be electrically connected to the first redistribution trace pattern 1130 of the first redistribution trace structure 1100. The external connectors 1500 may be solder balls.
Fig. 11 is a plan view illustrating the first sub-package 1010 of fig. 1. Fig. 10 is a sectional view taken along line X-X' of fig. 11. Fig. 11 corresponds to a bottom view of the first semiconductor wafer 1200, the first bridge wafer 1300, and the first molding layer 1400.
Referring to fig. 10 and 11, an additional first semiconductor wafer 1200-1 may be disposed to be spaced apart from the first semiconductor wafer 1200. In this case, two additional first bridge wafers 1300 may also be disposed on both sides of the additional first semiconductor wafer 1200-1, respectively. Each first bridge wafer 1300 may include a plurality of first vias 1330, and the first via pads 1320 may be connected to respective first vias 1330.
Fig. 12 is a cross-sectional view illustrating a first bridge wafer 1300 included in a semiconductor package according to an embodiment.
Referring to fig. 10 and 12, the first bridge wafer 1300 may be configured to include a first body 1310, a first via pad 1320, a first via 1330, and a first pillar bump 1340. The first body 1310 may be a substrate having a bottom surface 1311 and a top surface 1312 opposite to each other. The first body 1310 may be a semiconductor substrate such as a silicon substrate. In some other embodiments, the first body 1310 may be a dielectric substrate. When the first body 1310 is a silicon substrate, it may be advantageous to form the first via 1330 using a semiconductor process.
The first through hole 1330 may vertically penetrate the first body 1310. That is, the first through-hole 1330 may extend from the bottom surface 1311 of the first body 1310 to the top surface 1312 of the first body 1310. In forming the first via 1330, some semiconductor processes (including a photolithography process applied to a silicon wafer) may be used.
Accordingly, the first via 1330 may be a Through Silicon Via (TSV) having a fine diameter D11. The first via 1330 may include a copper layer. TSVs may have a relatively small diameter compared to Through Mold Vias (TMVs). Accordingly, the number of the first through holes 1330 formed in a limited area may be increased. Since the diameter of the TMV is greater than that of the TSV, it may be difficult to densely form the TMV in a limited area, as opposed to the TSV.
As described above, the first via 1330 may be formed using a TSV technique. Accordingly, the first via 1330 may be formed in a limited area of the first body 1310, such that the first via 1330 corresponds to many input/output (I/O) terminals and power/ground terminals of the first bridge wafer 1300.
If the diameter D11 of the first via 1330 is decreased, the length L of the first via 1330 may also decrease. The first body 1310 may be configured to include a core 1315 through which the first through hole 1330 substantially penetrates and a third dielectric layer 1316 covering the core 1315. The third dielectric layer 1316 may be a dielectric layer that electrically isolates and insulates the first via pads 1320 from each other. The core 1315 may be a silicon substrate. The first via pad 1320 may be a connection element connecting the first via 1330 to the first redistribution trace pattern (1130 of fig. 10) of the first redistribution trace structure (1100 of fig. 10).
The first through hole 1330 may be formed to have a length L corresponding to a thickness T12-1 of the core 1315, and a thickness T12-1 of the core 1315 may be less than a thickness T12 of the first body 1310. In this case, there may be a limitation in reducing the diameter D11 of the first via 1330 in the first bridge wafer 1300 due to a limitation in the aspect ratio of the via in which each first via 1330 is formed. To reduce the diameter D11 of the first vias 1330 in the first bridge wafer 1300, the thickness T12 of the first body 1310 or the thickness T12-1 of the core 1315 may need to be reduced to overcome the limitation of the aspect ratio of the vias forming each first via 1330. The diameter D11 of the first via 1330 may also be reduced if the thickness T12 of the first body 1310 becomes smaller than the thickness of the first semiconductor wafer 1200 (T11 of fig. 10). Accordingly, the number of the first through holes 1330 formed in the first body 1310 may be increased.
The first via pad 1320 of the first bridge wafer 1300 may be disposed on a bottom surface of the first bridge wafer 1300 (i.e., the bottom surface 1311 of the first body 1310) to connect to the first via 1330. The first via pad 1320 may be an electrical connection terminal disposed to overlap the first via 1330.
The first pillar bump 1340 may be connected to the first through hole 1330. A first pillar bump 1340 may be disposed on a top surface of the first via 1330 opposite the first via pad 1320. The first pillar bump 1340 may be disposed to protrude from the top surface 1312 of the first body 1310. The first post bump 1340 may have a diameter D12, with a diameter D12 greater than a diameter D11 of the first through-hole 1330. The first pillar bump 1340 may have a vertical height corresponding to a thickness T13 from the top surface 1312 of the first body 1310 to compensate for the thickness T12 of the first body 1310.
As a result, the first bridge wafer 1300 may have a first height H11 corresponding to the sum of the thickness T12 of the first body 1310 and the thickness T13 of the first pillar bump 1340. Due to the presence of the first pillar bump 1340, the thickness T12 of the first body 1310 may be relatively reduced without reducing the first height H11 of the first bridge wafer 1300. Accordingly, the diameter D11 of the first through-hole 1330 may be further reduced to increase the number of first through-holes 1330 formed in a limited area of the first body 1310.
Referring again to fig. 10, the first bridge wafer 1300 may have a first height H11 and may be disposed on the first redistribution structure 1100. The first height H11 may correspond to a distance between a level of the top surface 1102 of the first redistribution line structure 1100 and a level of the top surface 1340U of the first pillar bump 1340. The first semiconductor die 1200 may have a second height H12 and may be disposed between the first bridge die 1300. The second height H12 may correspond to a distance between a level of the top surface 1102 of the first redistribution line structure 1100 and a level of the top surface 1202 of the first semiconductor die 1200. The first height H11 of the first bridge wafer 1300 may be less than the second height H12 of the first semiconductor wafer 1200. Thus, there may be a level difference H13 between the first bridge wafer 1300 and the first semiconductor wafer 1200. Because the first height H11 of the first bridge wafer 1300 is less than the second height H12 of the first semiconductor wafer 1200, there may be a level difference H13. The top surface 1340U of the first pillar bump 1340 may be located at a level lower than the level of the top surface 1202 of the first semiconductor die 1200 by the level difference H13.
Because there is a level difference H13 between the first bridge wafer 1300 and the first semiconductor wafer 1200, the first sub-package 1010 may have a middle portion 1010H and a recessed edge portion 1010R, the top surface of the recessed edge portion 1010R being lower than the top surface of the middle portion 1010H. Accordingly, the middle portion 1010H and the recessed edge portion 1010R of the first sub-package 1010 may provide a stepped structure due to the level difference H13.
The middle portion 1010H of the first sub-package 1010 may be a region where the first semiconductor wafer 1200 is disposed. The top surface of the first sub-package 1010 may correspond to the top surface 1202 of the first semiconductor die 1200. The recessed edge portion 1010R of the first sub-package 1010 may be a region where the first bridge wafer 1300 is disposed. The top surface of the recessed edge portion 1010R of the first sub-package 1010 may include the top surface 1340U of the first pillar bump 1340 and the top surface of the first molding layer 1400. A top surface 1340U of the first pillar bump 1340 may be exposed at a top surface of the first molding layer 1400. The first molding layer 1400 may be disposed to surround a side surface of the first pillar bump 1340 and cover the first body 1310.
Fig. 13 is a cross-sectional view illustrating a second sub-package 1020 of the semiconductor package according to the embodiment.
Referring to fig. 13, the second sub-package 1020 may be configured to have substantially the same shape as the first sub-package 1010 shown in fig. 10. The second sub-package 1020 may be configured to include substantially the same elements as the first sub-package 1010 shown in fig. 10. The second sub-package 1020 may have substantially the same structure as the first sub-package 1010 shown in fig. 10. The second sub-package 1020 may be configured to include a second redistribution line structure S1100, a second semiconductor wafer S1200, a second bridge wafer S1300, and a second molding layer S1400.
The second bridge wafer S1300 may have a fourth height H14 and may be disposed on the second redistribution line structure S1100. The fourth height H14 may correspond to a distance between a level of the top surface S1102 of the second redistribution line structure S1100 and a level of the top surface S1340U of the second stud bump S1340 in the second bridge wafer S1300. The second semiconductor wafer S1200 may have a fifth height H15 and may be disposed between the second bridge wafers S1300. The fifth height H15 may correspond to a distance between a level of the top surface S1102 of the second redistribution line structure S1100 and a level of the top surface S1202 of the second semiconductor wafer S1200. The fourth height H14 of the first bridge wafer S1300 may be less than the fifth height H15 of the second semiconductor wafer S1200. Therefore, there may be a level difference H16 between the second bridge wafer S1300 and the second semiconductor wafer S1200. Since the fourth height H14 of the second bridge wafer S1300 is less than the fifth height H15 of the second semiconductor wafer S1200, there may be a level difference H16.
Because there is a level difference H16 between the second bridge wafer S1300 and the second semiconductor wafer S1200, the second sub-package 1020 may have a middle portion 1020H and a recessed edge portion 1020R, the top surface of the recessed edge portion 1020R being lower than the top surface of the middle portion 1020H. Accordingly, the middle portion 1020H and the recessed edge portion 1020R of the second sub-package 1020 may provide a stepped structure due to the level difference H16.
Each of the second bridge wafers S1300 may be configured to include a second body S1310, a second via pad S1320, a second via S1330, and a second pillar bump S1340. The second molding layer S1400 may surround the side surface of the second bridge wafer S1300 and the side surface of the second semiconductor wafer S1200 to expose the top surface S1340U of the second pillar bump S1340. The second redistribution line structure S1100 may include a second redistribution line pattern S1130, a third dielectric layer S1110, and a fourth dielectric layer S1120. The third and fourth dielectric layers S1110 and S1120 may be disposed to electrically isolate and insulate the second redistribution line patterns S1130 from each other.
The second redistribution line structure S1100 may be used as an interconnection structure for electrically connecting the second semiconductor wafer S1200 to the first semiconductor wafer (1200 of fig. 10), the first bridge wafer (1300 of fig. 10), or an external device. The vertical connector S1500 may be electrically connected to the second redistribution line pattern S1130 of the second redistribution line structure S1100. The vertical connector S1500 may be used as a connecting member for connecting an upper element to a lower element located below the upper element. The vertical connectors S1500 may be solder balls or conductive bumps.
Fig. 14 is a cross-sectional view illustrating a semiconductor package 1030 according to an embodiment. Fig. 15 is an enlarged view of a first bridge wafer 1300 and a second bridge wafer S1300 included in the semiconductor package 1030 of fig. 14.
Referring to fig. 14, a semiconductor package 1030 may be configured to include a first sub-package 1010 and a second sub-package 1020 which are sequentially stacked. The second sub-package 1020 may be vertically stacked on the first sub-package 1010. The bottom surface of the second sub-package 1020 may be in direct contact with the top surface of the first sub-package 1010. The bottom surface of the second sub-package 1020 may correspond to the bottom surface S1121 of the second redistribution line structure S1100. The top surface of the first sub-package 1010 may correspond to the top surface 1202 of the first semiconductor die 1200. Accordingly, the bottom surface S1121 of the second redistribution line structure S1100 may be in direct contact with the top surface 1202 of the first semiconductor wafer 1200. The top surface of the middle portion 1010H of the first sub-package 1010 may be in direct contact with the bottom surface of the second sub-package 1020 corresponding to the bottom surface S1121 of the second redistribution line structure S1100.
Since the bottom surface of the second sub-package 1020 is in direct contact with the top surface 1202 of the first sub-package 1010, the total thickness of the first and second sub-packages 1010 and 1020 (i.e., the thickness T14 of the semiconductor package 1030) may be minimized. That is, the thickness T14 of the semiconductor package 1030 including the first sub-package 1010 and the second sub-package 1020 vertically contacting each other may be reduced as compared to a comparative example in which the first sub-package and the second sub-package are stacked to be vertically spaced apart from each other.
Referring to fig. 14 and 15, in the semiconductor package 1030, the concave portion 1020R of the second sub-package 1020 may correspond to a portion laterally protruding from the second semiconductor wafer S1200 to vertically overlap with the concave edge portion 1010R of the first sub-package 1010. Hereinafter, the concave portion 1020R of the second sub-package 1020 may be referred to as a protrusion of the second sub-package 1020. The protrusion 1020R of the second sub-package 1020 may protrude to be located above the concave edge portion 1010R of the first sub-package 1010. The protrusion 1020R of the second sub-package 1020 may include a protrusion of the second redistribution line structure S1100. The protrusion of the second redistribution line structure S1100 may not protrude to vertically overlap the first semiconductor wafer 1200.
The protrusion 1020R of the second sub-package 1020 may be vertically spaced apart from the concave edge portion 1010R of the first sub-package 1010. The first sub-package 1010 may have a middle portion 1010H and a recessed edge portion 1010R lower than the middle portion 1010H, thereby providing a stepped structure. Accordingly, the protrusion 1020R corresponding to the edge portion of the second sub-package 1020, which is in contact with the first sub-package 1010, may laterally protrude from the second semiconductor wafer S1200 as an overhang.
The vertical connector S1500 may be disposed between the protrusion 1020R of the second sub-package 1020 and the recessed edge portion 1010R of the first sub-package 1010. The vertical connector S1500 may be disposed on the recessed edge portion 1010R of the first sub-package 1010 to support the protrusion 1020R of the second sub-package 1020.
The vertical connector S1500 may have a third height CH. The third height CH may correspond to a distance between a level of a top surface of the concave edge portion 1010R of the first sub-package 1010 and a level of a bottom surface S1121 of the second redistribution line structure S1100 (i.e., a bottom surface of the second sub-package 1020). The third height CH of the vertical connector S1500 may have an appropriate value for compensating a level difference H13 corresponding to a distance between the protrusion 1020R of the second sub-package 1020 and the recessed edge portion 1010R of the first sub-package 1010. Since the vertical connector S1500 compensates for the level difference H13, the third height CH of the vertical connector S1500 may correspond to a difference between the first height H11 of the first bridge die 1300 and the second height H12 of the first semiconductor die 1200.
The vertical connector S1500 may electrically connect the first pillar bump 1340 of the first bridge die 1300 of the first sub-package 1010 to the second redistribution line pattern S1130 of the second redistribution line structure S1100 of the second sub-package 1020. As a result, the vertical connector S1500 may provide a vertical path that electrically connects the first sub-package 1010 to the second sub-package 1020. The vertical connector S1500 may electrically connect the first semiconductor wafer 1200 and the second semiconductor wafer S1200 to each other. The vertical connector S1500 may be located on the recessed edge portion 1010R of the first sub-package 1010. Accordingly, the upper portion 1203U of the side surface 1203 of the first semiconductor wafer 1200 may face the side surface S1503 of the vertical connector S1500.
Referring again to fig. 14 and 15, because the first sub-package 1010 includes a middle portion 1010H and a recessed edge portion 1010R lower than the middle portion 1010H to provide a stepped structure, the vertical connector S1500 on the recessed edge portion 1010R may extend in a downward direction from the level of the top surface 1202 of the first sub-package 1010. Thus, the bottom surface of the second sub-package 1020 may be in contact with the top surface 1202 of the first sub-package 1010. In the comparative example, if the first sub-package corresponding to the first sub-package 1010 has a flat top surface without any stepped structure, the vertical connector corresponding to the vertical connector S1500 may be disposed to protrude from the flat top surface of the first sub-package. In this case, the second sub-package corresponding to the second sub-package 1020 may be vertically spaced apart from the first sub-package by the height of the vertical connector. Therefore, the semiconductor package according to the comparative example including the first sub-package and the second sub-package vertically spaced apart from each other by the vertical connector may have a thickness greater than the thickness T14 of the semiconductor package 1030 shown in fig. 14. That is, the thickness T14 of the semiconductor package 1030 shown in fig. 14 may be smaller than that of the semiconductor package according to the comparative example. Therefore, the present embodiment can provide a thin and compact semiconductor package.
Fig. 16 is a cross-sectional view illustrating a semiconductor package 1040 according to an embodiment.
Referring to fig. 16, the semiconductor package 1040 may further include an organic material layer 1600 disposed between the top surface 1202 of the first sub-package 1010 and the bottom surface of the second sub-package 1020 (i.e., the bottom surface S1121 of the second redistribution line structure S1100, as compared to the semiconductor package 1030). The organic material layer 1600 may be a film-like layer. The organic material layer 1600 may be an adhesive layer attaching the second sub-package 1020 to the first sub-package 1010. The organic material layer 1600 serving as an adhesive layer may fix the second sub-package 1020 to the first sub-package 1010 to prevent or suppress any undesired positional change of the second sub-package 1020.
Fig. 17 is a block diagram illustrating an electronic system including a memory card 7800 employing at least one semiconductor package according to an embodiment of the present disclosure. The memory card 7800 may include a memory 7810 such as a nonvolatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 may store data or read stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one semiconductor package according to an embodiment of the present disclosure.
The memory 7810 may include a nonvolatile memory device manufactured according to an embodiment of the present disclosure. The memory controller 7820 may control the memory 7810 so that stored data is read out or stored data is stored in response to a read/write request from the host 7830.
Fig. 18 is a block diagram illustrating an electronic system 8710 including at least one semiconductor package according to embodiments of the present disclosure. The electronic system 8710 may include a controller 8711, an input/output device 8712, and a memory 8713. The controller 8711, the input/output device 8712, and the memory 8713 may be coupled to each other by a bus 8715 that provides a path for data movement.
In an embodiment, the controller 8711 can include one or more microprocessors, digital signal processors, microcontrollers, and/or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include one or more semiconductor packages according to embodiments of the present disclosure. The input/output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch screen, and the like. The memory 8713 is a device for storing data. The memory 8713 can store data and/or commands, etc. to be executed by the controller 8711.
The memory 8713 may include a volatile memory device such as a DRAM and/or a non-volatile memory device such as a flash memory. For example, the flash memory may be mounted to an information processing system such as a mobile terminal or a desktop computer. The flash memory may constitute a Solid State Disk (SSD). In this case, the electronic system 8710 can stably store a large amount of data in the flash memory system.
Electronic system 8710 can also include an interface 8714, with interface 8714 configured to send and receive data to and from a communication network. The interface 8714 may be of a wired or wireless type. For example, interface 8714 may include an antenna or a wired or wireless transceiver.
The electronic system 8710 may be implemented as a mobile system, a personal computer, an industrial computer, or a logic system performing various functions. For example, the mobile system may be any one of a Personal Digital Assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information transmission/reception system.
If electronic system 8710 is a device capable of performing wireless communication, electronic system 8710 may be used for a communication system using a technology of CDMA (code division multiple access), GSM (global system for mobile communication), NADC (north american digital cellular), E-TDMA (enhanced time division multiple access), WCDMA (wideband code division multiple access), CDMA2000, LTE (long term evolution), or WiBro (wireless broadband internet).
Embodiments of the present disclosure have been disclosed for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the disclosure and the accompanying claims.
Cross Reference to Related Applications
This application is a priority of korean patent application No.10-2019-0085391, filed on 7/15/2019.

Claims (20)

1. A semiconductor package, the semiconductor package comprising:
a first semiconductor die disposed on a first redistribution line structure;
a first bridge wafer disposed on the first redistribution line structure to provide a level difference between the first semiconductor wafer and the first bridge wafer, the first bridge wafer having a height that is less than a height of the first semiconductor wafer;
a second redistribution line structure stacked on the first semiconductor wafer such that a bottom surface of the second redistribution line structure is in contact with a top surface of the first semiconductor wafer, wherein the second redistribution line structure is provided to have a protrusion laterally protruding from a side surface of the first semiconductor wafer when viewed in a plan view;
a second semiconductor wafer disposed on the second redistribution line structure; and
a vertical connector disposed between the first bridge wafer and the protrusion of the second redistribution line structure to support the protrusion,
wherein the first bridge wafer includes a first via.
2. The semiconductor package of claim 1, wherein the first bridge die comprises:
a first body through which the first through hole vertically passes; and
a first pillar bump disposed on the first body to protrude upward from the first body, and electrically connected to the first via hole;
wherein the vertical connector electrically connects the first pillar bump to the protrusion of the second redistribution line structure.
3. The semiconductor package of claim 2, wherein the level difference exists because a first height from the first redistribution line structure to a level of a top surface of the first pillar bump is less than a second height from the first redistribution line structure to a level of a top surface of the first semiconductor die.
4. The semiconductor package of claim 3, wherein the vertical connector has a third height corresponding to a difference between the first height and the second height.
5. The semiconductor package of claim 4, wherein the vertical connectors comprise solder balls.
6. The semiconductor package of claim 2, further comprising a first molding layer surrounding the first bridge wafer and the first semiconductor wafer,
wherein the first molding layer surrounds the first pillar bump and covers the first body of the first bridge wafer.
7. The semiconductor package according to claim 6, wherein the first molding layer is provided to expose an upper portion of a side surface of the first semiconductor wafer and a top surface of the first semiconductor wafer.
8. The semiconductor package of claim 2, wherein the first pillar bump has a second diameter that is greater than a first diameter of the first via.
9. The semiconductor package of claim 1, wherein the first redistribution line structure comprises:
a redistribution wiring pattern electrically connecting the first semiconductor wafer to the first via; and
a dielectric layer isolating the redistribution wiring pattern.
10. The semiconductor package of claim 1, wherein the vertical connector is disposed such that a side surface of the first semiconductor die faces a side surface of the vertical connector.
11. The semiconductor package of claim 1, further comprising a layer of organic material disposed between a top surface of the first semiconductor die and a bottom surface of the second redistribution line structure.
12. The semiconductor package of claim 1, further comprising:
a second bridge wafer disposed on the second redistribution line structure, providing a level difference with the second semiconductor wafer, and having a height smaller than a height of the second semiconductor wafer, wherein the second bridge wafer includes a second via and a second pillar bump; and
a second molding layer surrounding the second bridge wafer and the second semiconductor wafer to expose a top surface of the second stud bump.
13. A semiconductor package, the semiconductor package comprising:
a first sub-package including a middle portion and a recessed edge portion having a top surface lower than a top surface of the middle portion;
a second sub-package stacked on the first sub-package such that a bottom surface of the second sub-package is in contact with a top surface of the middle portion of the first sub-package, wherein the second sub-package has a protrusion vertically spaced apart from the recessed edge portion of the first sub-package; and
a vertical connector provided on the recessed edge portion to support the protruding portion of the second sub-package,
wherein the first sub-package comprises:
a first redistribution line structure;
a first semiconductor die disposed on the first redistribution line structure;
a first bridge wafer disposed on the first redistribution line structure to provide a level difference between the first semiconductor wafer and the first bridge wafer, the first bridge wafer having a height less than a height of the first semiconductor wafer, wherein the first bridge wafer includes a first via and a first pillar bump; and
a first molding layer surrounding the first bridge wafer and the first semiconductor wafer to expose a top surface of the first pillar bump, and
wherein the vertical connector is connected to the first stud bump.
14. The semiconductor package of claim 13, wherein the level difference exists because a first height from the first redistribution line structure to a level of a top surface of the first pillar bump is less than a second height from the first redistribution line structure to a level of a top surface of the first semiconductor die.
15. The semiconductor package of claim 14, wherein the vertical connector has a third height corresponding to a difference between the first height and the second height.
16. The semiconductor package of claim 13, wherein the first redistribution line structure comprises:
a redistribution wiring pattern electrically connecting the first semiconductor wafer to the first via; and
a dielectric layer isolating the redistribution wiring pattern.
17. The semiconductor package of claim 13, wherein the vertical connector is disposed such that a side surface of the first semiconductor die faces a side surface of the vertical connector.
18. The semiconductor package of claim 13, further comprising a layer of organic material disposed between a top surface of the first sub-package and a bottom surface of the second sub-package.
19. The semiconductor package of claim 13, wherein the second sub-package comprises:
a second redistribution line structure;
a second semiconductor wafer disposed on the second redistribution line structure;
a second bridge wafer disposed on the second redistribution line structure, providing a level difference with the second semiconductor wafer, and having a height smaller than a height of the second semiconductor wafer, wherein the second bridge wafer includes a second via and a second pillar bump; and
a second molding layer surrounding the second bridge wafer and the second semiconductor wafer to expose a top surface of the second stud bump.
20. The semiconductor package of claim 13, wherein the second sub-package has substantially the same structure as the first sub-package.
CN201911219865.6A 2019-07-15 2019-12-03 Semiconductor package including bridge die Pending CN112234045A (en)

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