TW202117997A - Semiconductor packages including bridge die - Google Patents

Semiconductor packages including bridge die Download PDF

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TW202117997A
TW202117997A TW108141559A TW108141559A TW202117997A TW 202117997 A TW202117997 A TW 202117997A TW 108141559 A TW108141559 A TW 108141559A TW 108141559 A TW108141559 A TW 108141559A TW 202117997 A TW202117997 A TW 202117997A
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die
semiconductor
package
sub
bridge
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TWI844580B (en
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任尚赫
成基俊
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南韓商愛思開海力士有限公司
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135Double encapsulation or coating and encapsulation
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    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481Internal lead connections, e.g. via connections, feedthrough structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L23/00Details of semiconductor or other solid state devices
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528Geometry or layout of the interconnection structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5384Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L23/538Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386Geometry or layout of the interconnection structure
    • HELECTRICITY
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    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto

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Abstract

A semiconductor package includes first and second semiconductor dies, first and second redistributed line structures, a first bridge die, and a vertical connector. The first semiconductor die and the first bridge die are disposed on the first redistributed line structure. The first bridge die is disposed to provide a level difference between the first semiconductor die and the first bridge die, the first bridge die having a height that is less than a height of the first semiconductor die. The second redistributed line structure has a protrusion, laterally protruding from a side surface of the first semiconductor die when viewed from a plan view, and a bottom surface of the second redistributed line structure is in contact with a top surface of the first semiconductor die. The second semiconductor die is disposed on the second redistributed line structure. The vertical connector is disposed between the bridge die and the protrusion of the second redistributed line structure to support the protrusion.

Description

包括橋接晶粒的半導體封裝件Semiconductor package including bridge die

本公開的各個實施方式總體上涉及半導體封裝件技術,並且更具體地,涉及包括橋接晶粒(bridge die)的半導體封裝件。 相關申請的交叉引用Various embodiments of the present disclosure generally relate to semiconductor package technology, and more specifically, to semiconductor packages including bridge dies. Cross-references to related applications

本申請案主張2019年7月15日提交的韓國專利申請案第10-2019-0085391號的優先權。This application claims the priority of Korean Patent Application No. 10-2019-0085391 filed on July 15, 2019.

最近,已經在各種電子系統中需要具有高密度並且能夠高速操作的半導體封裝件。另外,已經開發出具有相對小的形狀因子的結構的半導體封裝件。為了實現這些半導體封裝件,已經對覆晶堆疊技術集中投入了大量努力。此外,為了實現厚度減小的半導體封裝件,已經對晶圓級封裝技術集中投入了大量努力。Recently, semiconductor packages with high density and capable of high-speed operation have been required in various electronic systems. In addition, semiconductor packages with structures with relatively small form factors have been developed. In order to realize these semiconductor packages, a lot of efforts have been concentrated on flip-chip stacking technology. In addition, in order to realize a semiconductor package with a reduced thickness, a lot of efforts have been concentrated on wafer-level packaging technology.

根據一個實施方式,一種半導體封裝件包括:第一半導體晶粒,其設置在第一重分佈線結構上;第一橋接晶粒,其設置在第一重分佈線結構上以提供第一半導體晶粒和第一橋接晶粒之間的水平差,第一橋接晶粒的高度小於第一半導體晶粒的高度;以及第二重分佈線結構,其堆疊在第一半導體晶粒上,使得第二重分佈線的底表面與第一半導體晶粒的頂表面接觸。第二重分佈線結構被設置成具有突出部,當從平面圖觀察時,突出部從第一半導體晶粒的側表面橫向突出。第二半導體晶粒設置在第二重分佈線結構上。垂直連接器設置在第一橋接晶粒與第二重分佈線結構的突出部之間以支撐突出部。第一橋接晶粒中包括第一通孔。According to one embodiment, a semiconductor package includes: a first semiconductor die disposed on a first redistribution line structure; a first bridge die disposed on the first redistribution line structure to provide a first semiconductor die The level difference between the first bridge die and the first bridge die, the height of the first bridge die is smaller than the height of the first semiconductor die; and the second redistribution line structure, which is stacked on the first semiconductor die so that the second The bottom surface of the redistribution line is in contact with the top surface of the first semiconductor die. The second redistribution line structure is provided to have a protrusion, and when viewed from a plan view, the protrusion laterally protrudes from the side surface of the first semiconductor die. The second semiconductor die is arranged on the second redistribution line structure. The vertical connector is arranged between the first bridge die and the protrusion of the second redistribution line structure to support the protrusion. The first bridge die includes a first through hole.

根據另一實施方式,一種半導體封裝件包括:第一子封裝件,其包括中間部分和凹入邊緣部分,凹入邊緣部分的頂表面低於中間部分的頂表面。第二子封裝件堆疊在第一子封裝件上,使得第二子封裝件的底表面與第一子封裝件的中間部分的頂表面接觸。第二子封裝件具有與第一子封裝件的凹入邊緣部分垂直間隔開的突出部。垂直連接器設置在凹入邊緣部分上以支撐第二子封裝件的突出部。第一子封裝件包括:第一重分佈線結構;第一半導體晶粒,其設置在第一重分佈線結構上;以及第一橋接晶粒,其設置在第一重分佈線結構上以提供第一半導體晶粒和第一橋接晶粒之間的水平差,第一橋接晶粒的高度小於第一半導體晶粒的高度。第一橋接晶粒包括第一通孔和第一柱凸塊。第一模製層圍繞第一橋接晶粒和第一半導體晶粒以露出第一柱凸塊的頂表面。垂直連接器連接到第一柱凸塊。According to another embodiment, a semiconductor package includes a first sub-package including a middle portion and a concave edge portion, the top surface of the concave edge portion being lower than the top surface of the middle portion. The second sub-package is stacked on the first sub-package such that the bottom surface of the second sub-package is in contact with the top surface of the middle portion of the first sub-package. The second sub-package has a protrusion vertically spaced from the concave edge portion of the first sub-package. The vertical connector is provided on the recessed edge portion to support the protrusion of the second sub-package. The first sub-package includes: a first redistribution line structure; a first semiconductor die disposed on the first redistribution line structure; and a first bridge die disposed on the first redistribution line structure to provide The level difference between the first semiconductor die and the first bridge die, and the height of the first bridge die is smaller than the height of the first semiconductor die. The first bridge die includes a first through hole and a first stud bump. The first mold layer surrounds the first bridge die and the first semiconductor die to expose the top surface of the first stud bump. The vertical connector is connected to the first pillar bump.

本文中使用的術語可以對應於考慮到它們在本公開的實施方式中的功能而選擇的詞語,並且術語的含義可以被解釋為根據本公開的實施方式所屬的領域中的普通技術人員是不同的。如果被詳細地定義,則術語可以根據所述定義來解釋。除非另有定義,否則本文中使用的術語(包括技術術語和科學術語)具有本公開的實施方式所屬的領域中的普通技術人員通常理解的相同的含義。The terms used herein may correspond to words selected in consideration of their functions in the embodiments of the present disclosure, and the meaning of the terms may be interpreted as being different according to those of ordinary skill in the field to which the embodiments of the present disclosure belong . If defined in detail, the terms can be interpreted according to the definition. Unless otherwise defined, the terms (including technical and scientific terms) used herein have the same meanings commonly understood by those of ordinary skill in the art to which the embodiments of the present disclosure belong.

應該理解,雖然在本文中可以使用術語“第一”、“第二”、“第三”等來描述各種元件,但是這些元件不應該受這些術語限制。這些術語僅用於將一個元件與另一個元件區分開,而不是用於僅定義元件本身或意指特定的順序。It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element, and are not used to only define the elements themselves or imply a specific order.

還應該理解,當一元件或層被稱為在另一元件或層“上”、“上方”、“下”、“下方”或“外部”時,該元件或層可以直接與另一元件或層接觸,或者可以存在中間元件或層。用於描述元件或層之間的關係的其它詞語應該以類似的樣式來解釋(例如,“在…之間”與“直接在…之間”或者“相鄰”與“直接相鄰”)。It should also be understood that when an element or layer is referred to as being “on,” “above,” “under,” “under,” or “outside” another element or layer, the element or layer can directly interact with the other element or layer. The layers are in contact, or there may be intermediate elements or layers. Other words used to describe the relationship between elements or layers should be interpreted in a similar style (for example, "between" and "directly between" or "adjacent" and "directly adjacent").

可以使用諸如“在…下方”、“在…下面”、“在…之下”、“在…上方”、“在…之上”、“頂”、“底”等這樣的空間相對術語來描述如例如圖中例示的一個元件和/或特徵與另一元件和/或特徵的關係。應該理解,空間上相對的術語旨在除了附圖中描繪的方位之外還涵蓋使用和/或操作中裝置的不同方位。例如,當將附圖中的裝置進行翻轉時,被描述為在其它元件或特徵下方或之下的元件隨後將被定向為在所述其它元件或特徵上方。裝置可以按其它方式來定向(旋轉90度或處於其它方位),並且相應解釋本文中使用的空間上相對的描述符。It can be described using spatial relative terms such as "below", "below", "below", "above", "above", "top", "bottom", etc. The relationship between one element and/or feature and another element and/or feature as exemplified in the figure, for example. It should be understood that the spatially relative terms are intended to cover different orientations of the device in use and/or operation in addition to the orientation depicted in the drawings. For example, when the device in the drawings is turned over, elements described as below or below other elements or features will then be oriented above the other elements or features. The device can be oriented in other ways (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used in this article are explained accordingly.

半導體封裝件可以包括諸如半導體晶片或半導體晶粒這樣的電子裝置。可以通過使用晶粒切割製程將諸如晶圓這樣的半導體基板分成多個件來獲得半導體晶片或半導體晶粒。半導體晶片可以對應於記憶體晶片、邏輯晶片(包括特定應用積體電路(ASIC)晶片)或系統單晶片(SoC)。記憶體晶片可以包括整合在半導體基板上的動態隨機存取記憶體(DRAM)電路、靜態隨機存取記憶體(SRAM)電路、反及型快閃記憶體電路、反或型快閃記憶體電路、磁性隨機存取記憶體(MRAM)電路、電阻式隨機存取記憶體(ReRAM)電路、鐵電隨機存取記憶體(FeRAM)電路或相變隨機存取記憶體(PcRAM)電路。邏輯晶片可以包括整合在半導體基板上的邏輯電路。可以在諸如行動電話、與生物技術或健康護理關聯的電子系統或者可穿戴電子系統這樣的通信系統中採用半導體封裝件。The semiconductor package may include electronic devices such as semiconductor wafers or semiconductor dies. A semiconductor wafer or semiconductor die can be obtained by dividing a semiconductor substrate such as a wafer into a plurality of pieces using a die cutting process. Semiconductor chips can correspond to memory chips, logic chips (including application-specific integrated circuit (ASIC) chips), or system-on-chip (SoC). The memory chip may include a dynamic random access memory (DRAM) circuit, a static random access memory (SRAM) circuit, a reverse type flash memory circuit, and a reverse NOR type flash memory circuit integrated on a semiconductor substrate , Magnetic random access memory (MRAM) circuit, resistive random access memory (ReRAM) circuit, ferroelectric random access memory (FeRAM) circuit or phase change random access memory (PcRAM) circuit. The logic chip may include a logic circuit integrated on a semiconductor substrate. Semiconductor packages can be employed in communication systems such as mobile phones, electronic systems associated with biotechnology or health care, or wearable electronic systems.

在整篇說明書中,相同的參考標號指代相同的元件。即使沒有參照一幅圖提及或描述一參考標號,也可以參照另一幅圖提及或描述該參考標號。另外,即使在一幅圖中沒有示出一參考標號,也可以參照另一幅圖提及或描述該參考標號。Throughout the specification, the same reference numerals refer to the same elements. Even if a reference number is not mentioned or described with reference to one figure, the reference number may be mentioned or described with reference to another figure. In addition, even if a reference number is not shown in one figure, the reference number may be mentioned or described with reference to another figure.

圖1、圖2和圖3是例示根據實施方式的半導體封裝件10的截面圖。圖4和圖5是例示圖1至圖3的半導體封裝件10的平面圖。圖1是沿著圖4和圖5的線X1-X1’截取的截面圖。圖2是沿著圖4和圖5的線X1-X1’的部分截取的放大截面圖。圖3是沿著圖4和圖5的線X2-X2’的部分截取的放大截面圖。圖4是在包括在圖1的半導體封裝件10中的半導體晶粒100的第一表面101的水平處截取的平面圖。為了容易和方便說明的目的,在圖4中省略了圖1中例示的介電層390和連接器600。圖5是在包括在圖1的半導體封裝件10中的半導體晶粒100的第二表面102的水平處截取的平面圖。1, 2, and 3 are cross-sectional views illustrating the semiconductor package 10 according to the embodiment. 4 and 5 are plan views illustrating the semiconductor package 10 of FIGS. 1 to 3. Fig. 1 is a cross-sectional view taken along the line X1-X1' of Figs. 4 and 5. Fig. 2 is an enlarged cross-sectional view taken along the line X1-X1' of Figs. 4 and 5. Fig. 3 is an enlarged cross-sectional view taken along the line X2-X2' of Figs. 4 and 5. 4 is a plan view taken at the level of the first surface 101 of the semiconductor die 100 included in the semiconductor package 10 of FIG. 1. For the purpose of easy and convenient description, the dielectric layer 390 and the connector 600 illustrated in FIG. 1 are omitted in FIG. 4. FIG. 5 is a plan view taken at the level of the second surface 102 of the semiconductor die 100 included in the semiconductor package 10 of FIG. 1.

參照圖1,半導體封裝件10可以被配置為包括半導體晶粒100、橋接晶粒200和重分佈線300。在平面圖中,橋接晶粒200可以與半導體晶粒100間隔開地設置。橋接晶粒200可以包括僅設置在半導體晶粒100的一側的一個晶粒,或者可以包括分別設置在半導體晶粒100的兩側的兩個晶粒。重分佈線300中的每一條可以被配置為包括將半導體晶粒100電連接到橋接晶粒200的導電圖案。半導體封裝件10還可以包括附接到橋接晶粒200的導電的柱凸塊400和模製層500。另外,半導體封裝件10還可以包括連接器600,連接器600中的每一個連接到重分佈線300中的每一條的一部分。介電層390可以被設置成覆蓋重分佈線300,以將重分佈線300彼此電絕緣。1, the semiconductor package 10 may be configured to include a semiconductor die 100, a bridge die 200 and a redistribution line 300. In a plan view, the bridge die 200 may be spaced apart from the semiconductor die 100. The bridge die 200 may include one die provided only on one side of the semiconductor die 100, or may include two die provided on both sides of the semiconductor die 100, respectively. Each of the redistribution lines 300 may be configured to include a conductive pattern that electrically connects the semiconductor die 100 to the bridge die 200. The semiconductor package 10 may further include a conductive stud bump 400 and a mold layer 500 attached to the bridge die 200. In addition, the semiconductor package 10 may further include a connector 600, and each of the connectors 600 is connected to a part of each of the redistribution lines 300. The dielectric layer 390 may be provided to cover the redistribution lines 300 to electrically insulate the redistribution lines 300 from each other.

參照圖1和圖2,半導體晶粒100可以具有其上設置有介電層390的第一表面101、位於介電層390對面的第二表面102以及從第一表面101的邊緣延伸到第二表面102的邊緣的第二側表面103。半導體晶粒100的第一表面101可以對應於其上設置有積體電路的主動表面。半導體晶粒100的第二表面102可以對應於半導體晶粒100的與主動表面相對的底表面或背面表面。第一表面101和第二表面102中的術語“第一”和“第二”僅用於將表面彼此區分開,而不是用於意指表面的特定順序。1 and 2, the semiconductor die 100 may have a first surface 101 on which a dielectric layer 390 is disposed, a second surface 102 located opposite to the dielectric layer 390, and a second surface 102 extending from the edge of the first surface 101 to the second surface. The second side surface 103 of the edge of the surface 102. The first surface 101 of the semiconductor die 100 may correspond to the active surface on which the integrated circuit is disposed. The second surface 102 of the semiconductor die 100 may correspond to the bottom surface or the back surface of the semiconductor die 100 opposite to the active surface. The terms "first" and "second" in the first surface 101 and the second surface 102 are only used to distinguish the surfaces from each other, and are not used to imply a specific order of the surfaces.

可以在半導體晶粒100的第一表面101上設置接觸墊110。接觸墊110可以是用作將半導體晶粒100電連接到外部裝置或系統的路徑的導電圖案。接觸墊110可以是佈置在半導體晶粒100的中間區域121中的中間墊,如圖4中例示的。接觸墊110可以在中間區域121的第一表面101上被佈置成兩行。半導體晶粒100可以包括中間區域121和分別位於中間區域121兩側的兩個邊緣區域123。A contact pad 110 may be provided on the first surface 101 of the semiconductor die 100. The contact pad 110 may be a conductive pattern used as a path for electrically connecting the semiconductor die 100 to an external device or system. The contact pad 110 may be an intermediate pad arranged in the intermediate region 121 of the semiconductor die 100, as illustrated in FIG. 4. The contact pads 110 may be arranged in two rows on the first surface 101 of the middle area 121. The semiconductor die 100 may include a middle region 121 and two edge regions 123 respectively located on both sides of the middle region 121.

參照圖2,橋接晶粒200可以被設置成與半導體晶粒100的第二側表面103間隔開。橋接晶粒200可以具有彼此相對的第三表面201和第四表面202以及彼此相對的第三側表面203和第四側表面204。橋接晶粒200可以被設置成使得橋接晶粒200的第三表面201面向與半導體晶粒100的第一表面101相同的方向。橋接晶粒200的第三表面201可以與半導體晶粒100的第一表面101共面。也就是說,橋接晶粒200的第三表面201可以位於與半導體晶粒100的第一表面101基本上相同的水平處。2, the bridge die 200 may be provided to be spaced apart from the second side surface 103 of the semiconductor die 100. The bridge die 200 may have a third surface 201 and a fourth surface 202 opposite to each other, and a third side surface 203 and a fourth side surface 204 opposite to each other. The bridge die 200 may be arranged such that the third surface 201 of the bridge die 200 faces the same direction as the first surface 101 of the semiconductor die 100. The third surface 201 of the bridging die 200 may be coplanar with the first surface 101 of the semiconductor die 100. That is, the third surface 201 of the bridging die 200 may be located at substantially the same level as the first surface 101 of the semiconductor die 100.

參照圖2和圖4,橋接晶粒200可以設置在半導體晶粒100旁邊,使得橋接晶粒200的第三側表面203面向半導體晶粒100的第二側表面103。橋接晶粒200可以與半導體晶粒100間隔開一定距離S。2 and 4, the bridge die 200 may be disposed beside the semiconductor die 100 such that the third side surface 203 of the bridge die 200 faces the second side surface 103 of the semiconductor die 100. The bridge die 200 may be spaced apart from the semiconductor die 100 by a certain distance S.

參照圖2,在橋接晶粒200的第四表面202和半導體晶粒100的第二表面102之間可以存在水平差H。橋接晶粒200可以設置在半導體晶粒100旁邊,使得橋接晶粒200的第四表面202和半導體晶粒100的第二表面102構成台階結構。橋接晶粒200可以比半導體晶粒100薄。與橋接晶粒200的第三表面201和第四表面202之間的距離對應的厚度T1(也被稱為第一厚度)可以小於與半導體晶粒100的第一表面101和第二表面102之間的距離對應的厚度T2(也被稱為第二厚度)。在一實施方式中,橋接晶粒200的厚度T1可以是半導體晶粒100的厚度T2的大致一半。2, there may be a level difference H between the fourth surface 202 of the bridging die 200 and the second surface 102 of the semiconductor die 100. The bridge die 200 may be disposed beside the semiconductor die 100 such that the fourth surface 202 of the bridge die 200 and the second surface 102 of the semiconductor die 100 form a step structure. The bridge die 200 may be thinner than the semiconductor die 100. The thickness T1 (also referred to as the first thickness) corresponding to the distance between the third surface 201 and the fourth surface 202 of the bridging die 200 may be smaller than the difference between the first surface 101 and the second surface 102 of the semiconductor die 100 The distance between the corresponding thickness T2 (also referred to as the second thickness). In an embodiment, the thickness T1 of the bridge die 200 may be approximately half of the thickness T2 of the semiconductor die 100.

橋接晶粒200可以包括通孔210,通孔210穿透橋接晶粒200的主體,以從第三表面201延伸到第四表面202。橋接晶粒200的主體可以包含諸如矽材料這樣的半導體材料。如果橋接晶粒200的主體包含矽材料,則可以使用矽加工技術來形成通孔210。在這種情況下,通孔210可以是具有相對細小直徑D1的直通矽穿孔(TSV)(在本說明書中也被稱為第一直徑)。通孔210可以由導電金屬材料(例如,包括銅材料的金屬材料)形成。The bridge die 200 may include a through hole 210 penetrating the body of the bridge die 200 to extend from the third surface 201 to the fourth surface 202. The body of the bridge die 200 may include a semiconductor material such as a silicon material. If the body of the bridge die 200 contains silicon material, silicon processing technology can be used to form the through hole 210. In this case, the through hole 210 may be a through silicon via (TSV) having a relatively small diameter D1 (also referred to as a first diameter in this specification). The through hole 210 may be formed of a conductive metal material (for example, a metal material including a copper material).

由於與半導體晶粒100的厚度T2相比,橋接晶粒200的厚度T1相對較小,因此通孔210的長度(對應於高度)可以相對短。例如,如果用厚度與半導體晶粒100基本上相同的厚橋接晶粒替換橋接晶粒200,則穿透厚橋接晶粒的通孔的長度可以大於通孔210的長度。然而,根據一實施方式,通孔210可以被形成為穿透比半導體晶粒100薄的橋接晶粒200。因此,通孔210可以被形成為具有相對短的長度。為了形成穿透厚橋接晶粒並具有細小直徑的通孔,可能有必要增大通孔的貫穿的通孔的寬高比。在不增加貫穿的通孔的直徑的情況下增大貫穿的通孔的寬高比可能存在限制。也就是說,如果通孔的長度增大,則通孔的直徑也可以增大。然而,根據所描述的實施方式,橋接晶粒200的厚度T1可以具有相對小的值。因此,穿透橋接晶粒200的通孔210可以被形成為具有相對短的長度,具有細小的直徑D1。因此,能夠增加設置在橋接晶粒200中的通孔210的數目,因為通孔210被形成為具有細小直徑D1。Since the thickness T1 of the bridge die 200 is relatively small compared to the thickness T2 of the semiconductor die 100, the length (corresponding to the height) of the through hole 210 may be relatively short. For example, if the bridge die 200 is replaced with a thick bridge die having substantially the same thickness as the semiconductor die 100, the length of the through hole penetrating the thick bridge die may be greater than the length of the through hole 210. However, according to an embodiment, the through hole 210 may be formed to penetrate the bridge die 200 that is thinner than the semiconductor die 100. Therefore, the through hole 210 may be formed to have a relatively short length. In order to form a through hole penetrating the thick bridging die and having a small diameter, it may be necessary to increase the aspect ratio of the through hole through which the through hole penetrates. There may be a limit to increasing the aspect ratio of the penetrating through hole without increasing the diameter of the penetrating through hole. That is, if the length of the through hole is increased, the diameter of the through hole can also be increased. However, according to the described embodiment, the thickness T1 of the bridge die 200 may have a relatively small value. Therefore, the through hole 210 penetrating the bridging die 200 may be formed to have a relatively short length with a fine diameter D1. Therefore, the number of through holes 210 provided in the bridge die 200 can be increased because the through holes 210 are formed to have a small diameter D1.

參照圖2,導電的柱凸塊400可以被設置成從橋接晶粒200的第四表面202突出。導電的柱凸塊400可以分別與通孔210電連接。在平面圖中,導電的柱凸塊400可以被設置成分別與通孔210重疊。導電的柱凸塊400可以從橋接晶粒200的第四表面202突出,使得導電的柱凸塊400中的每一個的第一側表面401的側表面面向半導體晶粒100的第二側表面103的上部。2, the conductive stud bump 400 may be provided to protrude from the fourth surface 202 of the bridge die 200. The conductive pillar bumps 400 may be electrically connected with the through holes 210, respectively. In a plan view, the conductive stud bumps 400 may be arranged to overlap with the through holes 210, respectively. The conductive stud bump 400 may protrude from the fourth surface 202 of the bridging die 200 such that the side surface of the first side surface 401 of each of the conductive stud bumps 400 faces the second side surface 103 of the semiconductor die 100 The upper part.

半導體封裝件10可以包括覆蓋橋接晶粒200的第四表面202的模製層500。模製層500可以被形成為覆蓋橋接晶粒200的第四表面202。模製層500可以被形成為包圍導電的柱凸塊400的側表面。模製層500可以被形成為直接覆蓋導電的柱凸塊400的第一側表面401。模製層500可以被形成為露出導電的柱凸塊400的頂表面402。導電的柱凸塊400的頂表面402可以與模製層500的頂表面501共面。The semiconductor package 10 may include a molding layer 500 covering the fourth surface 202 of the bridge die 200. The molding layer 500 may be formed to cover the fourth surface 202 of the bridge die 200. The mold layer 500 may be formed to surround the side surface of the conductive stud bump 400. The molding layer 500 may be formed to directly cover the first side surface 401 of the conductive stud bump 400. The mold layer 500 may be formed to expose the top surface 402 of the conductive stud bump 400. The top surface 402 of the conductive stud bump 400 may be coplanar with the top surface 501 of the mold layer 500.

其它連接器(未例示)可以附接或連接到導電的柱凸塊400的頂表面402,以將導電的柱凸塊400電連接到另一半導體封裝件或外部裝置。導電的柱凸塊400可以被模製層500包圍。導電的柱凸塊400可以基本上穿透覆蓋橋接晶粒200的第四表面202的模製層500的部分。因此,導電的柱凸塊400可以充當用於將通孔210的電路徑延伸直至模製層500的頂表面501的延伸線。Other connectors (not illustrated) may be attached or connected to the top surface 402 of the conductive stud bump 400 to electrically connect the conductive stud bump 400 to another semiconductor package or an external device. The conductive stud bump 400 may be surrounded by the mold layer 500. The conductive stud bump 400 may substantially penetrate a portion of the mold layer 500 covering the fourth surface 202 of the bridging die 200. Therefore, the conductive stud bump 400 may serve as an extension line for extending the electrical path of the through hole 210 to the top surface 501 of the molding layer 500.

儘管通孔210之間的空間被填充有諸如矽材料這樣的半導體材料,但是導電的柱凸塊400之間的空間可以被填充有諸如包含環氧樹脂模製化合物(EMC)材料的模製層500這樣的介電層。Although the space between the through holes 210 is filled with a semiconductor material such as a silicon material, the space between the conductive pillar bumps 400 may be filled with a molding layer such as an epoxy molding compound (EMC) material. 500 such a dielectric layer.

由於通孔210穿透包含半導體材料的橋接晶粒200的主體,因此與通孔210穿透絕緣基板的情況相比,通孔210中的每一個的阻抗分量可以增加。另外,如果通孔210被設置在有限的區域或有限的空間中,則通孔210之間的距離可以減小,從而造成由於雜訊信號更頻繁地出現而導致的串擾現象。當半導體封裝件在高頻下操作時,串擾現象會影響半導體封裝件的信號傳輸特性或信號完整性特性。根據所描述的實施方式,柱凸塊400之間的空間可以被填充有介電材料,例如,環氧樹脂模製化合物(EMC)材料。因此,即使通孔210被設置成穿透包含半導體材料的橋接晶粒200,由於存在填充柱凸塊400之間的空間的介電材料(即,模製層500),也能夠改善對半導體封裝件10的總體串擾現象的抑制。例如,矽材料在室溫且在1.0 kHz的頻率下可以具有約11.68的介電常數,而EMC材料在室溫且在1.0 kHz的頻率下可以具有約3.7的介電常數。橋接晶粒200和模製層500之間的這種介電常數差異會影響諸如半導體封裝件10的信號傳輸特性或信號完整性特性這樣的電特性。Since the through hole 210 penetrates the body of the bridge die 200 containing a semiconductor material, the impedance component of each of the through holes 210 may be increased compared to the case where the through hole 210 penetrates the insulating substrate. In addition, if the through holes 210 are provided in a limited area or a limited space, the distance between the through holes 210 can be reduced, thereby causing a crosstalk phenomenon due to more frequent occurrence of noise signals. When the semiconductor package is operated at a high frequency, the crosstalk phenomenon may affect the signal transmission characteristics or signal integrity characteristics of the semiconductor package. According to the described embodiment, the space between the pillar bumps 400 may be filled with a dielectric material, for example, an epoxy molding compound (EMC) material. Therefore, even if the through hole 210 is provided to penetrate the bridge die 200 containing the semiconductor material, due to the presence of the dielectric material (ie, the mold layer 500) filling the space between the pillar bumps 400, the semiconductor package can be improved Suppression of the overall crosstalk phenomenon of the device 10. For example, a silicon material may have a dielectric constant of about 11.68 at room temperature and a frequency of 1.0 kHz, and an EMC material may have a dielectric constant of about 3.7 at a frequency of 1.0 kHz at room temperature. This difference in dielectric constant between the bridge die 200 and the mold layer 500 may affect electrical characteristics such as signal transmission characteristics or signal integrity characteristics of the semiconductor package 10.

柱凸塊400中的每一個可以具有比通孔210中的每一個的第一直徑D1大的第二直徑D2。由於通孔210中的每一個的第一直徑D1小於連接到通孔210的柱凸塊400中的每一個的第二直徑D2,因此通孔210之間的距離可以相對大於柱凸塊400之間的距離。也就是說,柱凸塊400可以被設置成使得柱凸塊400之間的距離小於通孔210之間的距離。例如,相鄰的柱凸塊之間的距離可以小於對應的相鄰通孔之間的距離。另外,柱凸塊400之間的空間可以被填充有介電材料,並且通孔210之間的空間可以被填充有半導體材料。由於通孔210之間的距離可以相對大於柱凸塊400之間的距離,因此能夠減少由於通過相鄰的通孔210傳輸的信號之間的干擾而產生的雜訊。Each of the pillar bumps 400 may have a second diameter D2 that is larger than the first diameter D1 of each of the through holes 210. Since the first diameter D1 of each of the through holes 210 is smaller than the second diameter D2 of each of the pillar bumps 400 connected to the through holes 210, the distance between the through holes 210 may be relatively larger than that of the pillar bumps 400. The distance between. That is, the pillar bumps 400 may be arranged such that the distance between the pillar bumps 400 is smaller than the distance between the through holes 210. For example, the distance between adjacent stud bumps may be smaller than the distance between corresponding adjacent through holes. In addition, the space between the stud bumps 400 may be filled with a dielectric material, and the space between the through holes 210 may be filled with a semiconductor material. Since the distance between the through holes 210 may be relatively larger than the distance between the stud bumps 400, the noise generated due to interference between signals transmitted through the adjacent through holes 210 can be reduced.

如上所述,為了減少由於通過相鄰的通孔210傳輸的信號之間的干擾而產生的雜訊,可能有必要增大通孔210之間的距離。為了在不改變通孔210的節距大小的情況下增大通孔210之間的距離,可能需要減小第一直徑D1。為了形成具有與比穿透橋接晶粒200的第二直徑D2小的細小直徑對應的第一直徑D1的通孔210,可能需要減小橋接晶粒200的厚度T1。根據一實施方式,橋接晶粒200可以被設置成具有比半導體晶粒100的厚度T2小的厚度T1。因此,通孔210中的每一個可以被形成為具有直通矽穿孔(TSV)形狀。結果,可以增大通孔210之間的距離,以抑制由於通過相鄰的通孔210傳輸的信號之間的干擾而產生的雜訊。As described above, in order to reduce noise generated due to interference between signals transmitted through adjacent through holes 210, it may be necessary to increase the distance between the through holes 210. In order to increase the distance between the through holes 210 without changing the pitch size of the through holes 210, the first diameter D1 may need to be reduced. In order to form the through hole 210 having the first diameter D1 corresponding to the fine diameter smaller than the second diameter D2 of the penetrating bridge die 200, the thickness T1 of the bridge die 200 may need to be reduced. According to an embodiment, the bridge die 200 may be provided to have a thickness T1 smaller than the thickness T2 of the semiconductor die 100. Therefore, each of the through holes 210 may be formed to have a through silicon via (TSV) shape. As a result, the distance between the through holes 210 can be increased to suppress noise generated due to interference between signals transmitted through the adjacent through holes 210.

柱凸塊400中的每一個可以具有包含銅材料的金屬柱的形狀。柱凸塊400的長度L(即,高度)可以小於柱凸塊400的第二直徑D2。例如,柱凸塊400中的每一個的長度L可以為約60微米。柱凸塊400的長度L可以與橋接晶粒200的第一厚度T1大致相同。例如,橋接晶粒200的第一厚度T1可以為約50微米。柱凸塊400中的每一個可以具有約100微米的第二直徑D2。相比之下,通孔210中的每一個的第一直徑D1可以為約0.5微米。由於柱凸塊400被形成為具有與通孔210相比相對大的直徑(即,第二直徑D2),因此諸如焊料凸塊這樣的連接器(未例示)可以直接連接到柱凸塊400的各個頂表面402。因此,不需要用於增加連接器(未例示)和柱凸塊400的頂表面402之間的接觸區域的額外導電墊。Each of the pillar bumps 400 may have the shape of a metal pillar including a copper material. The length L (ie, height) of the stud bump 400 may be smaller than the second diameter D2 of the stud bump 400. For example, the length L of each of the stud bumps 400 may be about 60 microns. The length L of the stud bump 400 may be approximately the same as the first thickness T1 of the bridge die 200. For example, the first thickness T1 of the bridge die 200 may be about 50 microns. Each of the stud bumps 400 may have a second diameter D2 of about 100 microns. In contrast, the first diameter D1 of each of the through holes 210 may be about 0.5 micrometers. Since the stud bump 400 is formed to have a relatively large diameter (ie, the second diameter D2) compared to the through hole 210, a connector (not illustrated) such as a solder bump can be directly connected to the stud bump 400 Each top surface 402. Therefore, an additional conductive pad for increasing the contact area between the connector (not illustrated) and the top surface 402 of the stud bump 400 is not required.

模製層500可以延伸以填充半導體晶粒100的第二側表面103和柱凸塊400的第一側表面401之間的空間。模製層500可以延伸以基本上覆蓋半導體晶粒100的第二側表面103的整個部分。模製層500還可以延伸以覆蓋橋接晶粒200的面向半導體晶粒100的第二側表面103的第三側表面203。模製層500還可以延伸以填充半導體晶粒100的第二側表面103和橋接晶粒200的第三側表面203之間的空間。The molding layer 500 may extend to fill the space between the second side surface 103 of the semiconductor die 100 and the first side surface 401 of the stud bump 400. The molding layer 500 may extend to substantially cover the entire portion of the second side surface 103 of the semiconductor die 100. The molding layer 500 may also extend to cover the third side surface 203 of the bridge die 200 facing the second side surface 103 of the semiconductor die 100. The molding layer 500 may also extend to fill the space between the second side surface 103 of the semiconductor die 100 and the third side surface 203 of the bridging die 200.

參照圖2和圖5,模製層500可以被形成為露出半導體晶粒100的第二表面102。半導體晶粒100的第二表面102可以與模製層500的頂表面501共面。也就是說,模製層500的頂表面501可以位於與半導體晶粒100的第二表面102基本上相同的水平處。柱凸塊400的頂表面402可以與半導體晶粒100的第二表面102共面。由於模製層500被形成為露出半導體晶粒100的第二表面102,因此與模製層500被形成為覆蓋半導體晶粒100的整個部分的情況相比,半導體封裝件10的總厚度可以具有減小的厚度。2 and 5, the mold layer 500 may be formed to expose the second surface 102 of the semiconductor die 100. The second surface 102 of the semiconductor die 100 may be coplanar with the top surface 501 of the mold layer 500. That is, the top surface 501 of the mold layer 500 may be located at substantially the same level as the second surface 102 of the semiconductor die 100. The top surface 402 of the stud bump 400 may be coplanar with the second surface 102 of the semiconductor die 100. Since the molding layer 500 is formed to expose the second surface 102 of the semiconductor die 100, the total thickness of the semiconductor package 10 may have Reduced thickness.

模製層500可以被形成為露出橋接晶粒200的與半導體晶粒100相對的第四側表面204。可以通過將模製層500形成為露出橋接晶粒200的第四側表面204來提高半導體封裝件10的熱輻射效率。被模製層500露出的橋接晶粒200的第四側表面204和半導體晶粒100的第二表面102可以充當半導體封裝件10的熱輻射路徑。The mold layer 500 may be formed to expose the fourth side surface 204 of the bridge die 200 opposite to the semiconductor die 100. The heat radiation efficiency of the semiconductor package 10 can be improved by forming the mold layer 500 to expose the fourth side surface 204 of the bridge die 200. The fourth side surface 204 of the bridge die 200 and the second surface 102 of the semiconductor die 100 exposed by the molding layer 500 may serve as a heat radiation path of the semiconductor package 10.

模製層500可以覆蓋橋接晶粒200的第三側表面203和半導體晶粒100的第二側表面103,並且可以延伸以覆蓋橋接晶粒200的第四表面202和柱凸塊400的第一側表面401。因此,能夠提高模製層500與橋接晶粒200的接合力,因為柱凸塊400與通孔210結合並且模製層500延伸以包圍柱凸塊400的第一側表面401。The mold layer 500 may cover the third side surface 203 of the bridge die 200 and the second side surface 103 of the semiconductor die 100, and may extend to cover the fourth surface 202 of the bridge die 200 and the first surface 202 of the pillar bump 400.边面401。 Side surface 401. Therefore, the bonding force of the mold layer 500 and the bridge die 200 can be improved because the stud bump 400 is combined with the through hole 210 and the mold layer 500 extends to surround the first side surface 401 of the stud bump 400.

再次參照圖2和圖4,半導體封裝件10還可以包括重分佈線300。重分佈線300可以被設置成將半導體晶粒100電連接到通孔210。重分佈線300中的每一條可以包括將半導體晶粒100的接觸墊110中的一個電連接到通孔210中的任一個的導電圖案。重分佈線300可以被形成為包含諸如鋁(Al)材料、銅(Cu)材料、金(Au)材料等這樣的金屬材料。Referring again to FIGS. 2 and 4, the semiconductor package 10 may further include a redistribution line 300. The redistribution line 300 may be provided to electrically connect the semiconductor die 100 to the through hole 210. Each of the redistribution lines 300 may include a conductive pattern that electrically connects one of the contact pads 110 of the semiconductor die 100 to any one of the through holes 210. The redistribution line 300 may be formed to include a metal material such as aluminum (Al) material, copper (Cu) material, gold (Au) material, and the like.

重分佈線300中的每一條可以包括墊重疊部分310、延伸線320或330+340以及通孔墊370。延伸線320和330+340可以包括第一延伸線320、第二延伸線330和第三延伸線340。墊重疊部分310可以接合到半導體晶粒100的接觸墊110中的任一個。墊重疊部分310可以與半導體晶粒100的接觸墊110中的一個接觸,以將接觸墊110中的一個電連接到延伸線320、330和340中的任一條。墊重疊部分310可以與半導體晶粒100的接觸墊110中的任一個重疊,以具有墊形狀。重分佈線300的通孔墊370可以被佈置成具有比接觸墊110的節距大小大的節距大小。Each of the redistribution lines 300 may include a pad overlap portion 310, an extension line 320 or 330+340, and a via pad 370. The extension lines 320 and 330+340 may include a first extension line 320, a second extension line 330, and a third extension line 340. The pad overlapping portion 310 may be bonded to any one of the contact pads 110 of the semiconductor die 100. The pad overlap portion 310 may be in contact with one of the contact pads 110 of the semiconductor die 100 to electrically connect one of the contact pads 110 to any one of the extension lines 320, 330, and 340. The pad overlapping portion 310 may overlap with any one of the contact pads 110 of the semiconductor die 100 to have a pad shape. The via pad 370 of the redistribution line 300 may be arranged to have a pitch size larger than that of the contact pad 110.

通孔墊370可以是與橋接晶粒200的通孔210中的任一個連接的導電圖案。通孔210的第一端可以分別連接到柱凸塊400,並且通孔210的第二端可以分別連接到重分佈線300的通孔墊370。重分佈線300的通孔墊370可以設置在橋接晶粒200的與柱凸塊400相對的第三表面201上,並且柱凸塊400可以設置在橋接晶粒200的與通孔墊370相對的第四表面202上。通孔210可以對應於將通孔墊370電連接到相應的柱凸塊400的導電圖案。通孔墊370可以被設置成在平面圖中與相應的通孔210重疊,並且柱凸塊400可以被設置成在平面圖中與相應的通孔210重疊。因此,當從平面圖觀看時,通孔墊370也可以被設置成分別與柱凸塊400重疊。通孔墊370可以是具有與柱凸塊400的第二直徑D2基本上相等或大致相同的第三直徑D3的導電圖案。通孔墊370可以具有比通孔210的第一直徑D1大的第三直徑D3。The via pad 370 may be a conductive pattern connected to any one of the via holes 210 of the bridge die 200. The first ends of the through holes 210 may be respectively connected to the stud bump 400, and the second ends of the through holes 210 may be respectively connected to the through hole pads 370 of the redistribution line 300. The via pad 370 of the redistribution line 300 may be disposed on the third surface 201 of the bridge die 200 opposite to the stud bump 400, and the stud bump 400 may be disposed on the bridge die 200 opposite to the via pad 370. On the fourth surface 202. The via 210 may correspond to a conductive pattern that electrically connects the via pad 370 to the corresponding stud bump 400. The through hole pad 370 may be arranged to overlap the corresponding through hole 210 in a plan view, and the pillar bump 400 may be arranged to overlap the corresponding through hole 210 in a plan view. Therefore, when viewed from a plan view, the via pads 370 may also be arranged to overlap the pillar bumps 400, respectively. The via pad 370 may be a conductive pattern having a third diameter D3 that is substantially equal to or substantially the same as the second diameter D2 of the stud bump 400. The via pad 370 may have a third diameter D3 larger than the first diameter D1 of the via 210.

重分佈線300的通孔墊370可以在橋接晶粒200的第三表面201上被佈置成多行。如圖4的平面圖中例示的,通孔墊370可以包括佈置在第一行的通孔墊371、佈置在第二行的通孔墊372、佈置在第三行的通孔墊373、佈置在第四行的通孔墊375和佈置在第五行的通孔墊377。可以將第一行至第五行順序定位成逐漸遠離半導體晶粒100。如圖4中例示的,通孔墊370可以被佈置成棋盤形狀(即,矩陣形式)。然而,圖4中例示的實施方式可以僅僅是本公開的各個實施方式中的一個。例如,在一些其它實施方式中,當從平面圖觀看時,每行中的通孔墊370可以沿著行方向以Z字形(zigzag)方式佈置。The via pads 370 of the redistribution line 300 may be arranged in multiple rows on the third surface 201 of the bridging die 200. As illustrated in the plan view of FIG. 4, the via pads 370 may include via pads 371 arranged in the first row, via pads 372 arranged in the second row, via pads 373 arranged in the third row, and The via pads 375 in the fourth row and the via pads 377 are arranged in the fifth row. The first row to the fifth row may be sequentially positioned gradually away from the semiconductor die 100. As illustrated in FIG. 4, the via pads 370 may be arranged in a checkerboard shape (ie, a matrix form). However, the embodiment illustrated in FIG. 4 may be only one of the various embodiments of the present disclosure. For example, in some other embodiments, when viewed from a plan view, the via pads 370 in each row may be arranged in a zigzag manner along the row direction.

重分佈線300的第一延伸線320可以對應於將佈置在第一行的通孔墊371電連接到第一組墊重疊部分310的延伸線。也就是說,第一延伸線320可以將佈置在第一行的通孔墊371電連接到第一組接觸墊110。通孔210中的一些可以通過佈置在第一行的通孔墊371、第一延伸線320和第一組墊重疊部分310電連接到半導體晶粒100的接觸墊110中的一些。第一延伸線320可以是從半導體晶粒100的第一表面101跨越模製層500延伸到橋接晶粒200的第三表面201上的導電圖案。The first extension line 320 of the redistribution line 300 may correspond to an extension line that electrically connects the via pads 371 arranged in the first row to the first group of pad overlap portions 310. That is, the first extension line 320 may electrically connect the via pads 371 arranged in the first row to the first group of contact pads 110. Some of the vias 210 may be electrically connected to some of the contact pads 110 of the semiconductor die 100 through the via pads 371, the first extension line 320, and the first set of pad overlapping portions 310 arranged in the first row. The first extension line 320 may be a conductive pattern extending from the first surface 101 of the semiconductor die 100 across the mold layer 500 to the third surface 201 of the bridging die 200.

參照圖3和圖4,重分佈線300的第二延伸線330可以對應於將佈置在第二行的通孔墊372電連接到第二組墊重疊部分310的延伸線。也就是說,第二延伸線330可以將佈置在第二行的通孔墊372電連接到第二組接觸墊110。通孔210中的一些可以通過佈置在第二行的通孔墊372、第二延伸線330和第二組墊重疊部分310電連接到半導體晶粒100的接觸墊110中的一些。第二延伸線330可以是從半導體晶粒100的第一表面101跨越模製層500延伸到橋接晶粒200的第三表面201上的導電圖案。如圖4中例示的,第一延伸線320和第二延伸線330可以交替地設置。Referring to FIGS. 3 and 4, the second extension line 330 of the redistribution line 300 may correspond to an extension line that electrically connects the via pads 372 arranged in the second row to the second group of pad overlap portions 310. That is, the second extension line 330 may electrically connect the via pads 372 arranged in the second row to the second group of contact pads 110. Some of the through holes 210 may be electrically connected to some of the contact pads 110 of the semiconductor die 100 through the through hole pads 372, the second extension line 330, and the second set of pad overlapping portions 310 arranged in the second row. The second extension line 330 may be a conductive pattern extending from the first surface 101 of the semiconductor die 100 across the mold layer 500 to the third surface 201 of the bridging die 200. As illustrated in FIG. 4, the first extension line 320 and the second extension line 330 may be alternately arranged.

重分佈線300的第三延伸線340可以對應於將佈置在第二行的通孔墊372電連接到佈置在第三行的通孔墊373的延伸線。由於第三延伸線340將佈置在第二行的通孔墊372電連接到佈置在第三行的通孔墊373,因此通孔210當中的與第二行的通孔墊372耦合的第一通孔212可以電連接到通孔210當中的與第三行的通孔墊373耦合的第二通孔213。第三延伸線340可以將第一通孔212電連接到與第一通孔212相鄰的第二通孔213。第三延伸線340可以設置在橋接晶粒200的第三表面201上。The third extension line 340 of the redistribution line 300 may correspond to an extension line that electrically connects the via pads 372 arranged in the second row to the via pads 373 arranged in the third row. Since the third extension line 340 electrically connects the via pads 372 arranged in the second row to the via pads 373 arranged in the third row, the first of the vias 210 coupled with the via pads 372 in the second row The through hole 212 may be electrically connected to the second through hole 213 coupled with the through hole pad 373 of the third row among the through holes 210. The third extension line 340 may electrically connect the first through hole 212 to the second through hole 213 adjacent to the first through hole 212. The third extension line 340 may be disposed on the third surface 201 of the bridge die 200.

第一通孔212中的一個和第二通孔213中的一個可以通過第三延伸線340中的任一條電連接到第二延伸線330中的任一條。即使通過第一通孔212異常地傳輸信號,信號也可以通過第二通孔213正常地傳輸到第二延伸線330。因此,能夠實現半導體封裝件10中包括的半導體晶粒100的可靠信號路徑。儘管第二延伸線330提供了資料信號路徑,但是第一延伸線320可以被用作包括電力電壓線和接地電壓線的電源線。One of the first through holes 212 and one of the second through holes 213 may be electrically connected to any one of the second extension lines 330 through any one of the third extension lines 340. Even if a signal is abnormally transmitted through the first through hole 212, the signal may be normally transmitted to the second extension line 330 through the second through hole 213. Therefore, a reliable signal path of the semiconductor die 100 included in the semiconductor package 10 can be realized. Although the second extension line 330 provides a data signal path, the first extension line 320 may be used as a power supply line including a power voltage line and a ground voltage line.

佈置在第四行的通孔墊375和佈置在第五行的通孔墊377可以設置在橋接晶粒200的第三表面201上,以充當第一虛設墊。也就是說,第四行中的通孔墊375和第五行中的通孔墊377可以與第一延伸線320、第二延伸線330和第三延伸線340電斷開和隔離。由於第四行中的通孔墊375和第五行中的通孔墊377對應於第一虛設墊,因此與第四行中的通孔墊375和第五行中的通孔墊377連接的通孔210也可以對應於電絕緣的第一虛設通孔215。連接到第一虛設通孔215的柱凸塊400也可以對應於電絕緣的第一虛設柱凸塊413。第一虛設墊375和377、第一虛設通孔215和第一虛設柱凸塊413可以被提供作為冗餘預備構件。The via pads 375 arranged in the fourth row and the via pads 377 arranged in the fifth row may be disposed on the third surface 201 of the bridging die 200 to serve as the first dummy pad. That is, the via pads 375 in the fourth row and the via pads 377 in the fifth row may be electrically disconnected and isolated from the first extension line 320, the second extension line 330, and the third extension line 340. Since the via pads 375 in the fourth row and the via pads 377 in the fifth row correspond to the first dummy pads, the vias connected to the via pads 375 in the fourth row and the via pads 377 in the fifth row 210 may also correspond to the first dummy via 215 that is electrically insulated. The stud bump 400 connected to the first dummy via 215 may also correspond to the first dummy stud bump 413 that is electrically insulated. The first dummy pads 375 and 377, the first dummy through hole 215, and the first dummy pillar bump 413 may be provided as redundant preparation members.

再次參照圖2,半導體封裝件10可以包括介電層390,介電層390露出通孔墊370而覆蓋第一延伸線320、第二延伸線330和第三延伸線340以及墊重疊部分310,以將延伸線320、330和340彼此電絕緣。介電層390可以被形成為覆蓋半導體晶粒100的第一表面101、橋接晶粒200的第三表面201以及半導體晶粒100和橋接晶粒200之間的模製層500。介電層390可以包括露出通孔墊370的阻焊層。2 again, the semiconductor package 10 may include a dielectric layer 390 that exposes the via pad 370 to cover the first extension line 320, the second extension line 330, the third extension line 340, and the pad overlap portion 310, The extension wires 320, 330, and 340 are electrically insulated from each other. The dielectric layer 390 may be formed to cover the first surface 101 of the semiconductor die 100, the third surface 201 of the bridge die 200, and the mold layer 500 between the semiconductor die 100 and the bridge die 200. The dielectric layer 390 may include a solder resist layer exposing the via pad 370.

連接器600可以附接到露出的通孔墊370,以將半導體封裝件10電連接到外部裝置或另一半導體封裝件。可以使用焊料凸塊或焊料球來實現連接器600。The connector 600 may be attached to the exposed via pad 370 to electrically connect the semiconductor package 10 to an external device or another semiconductor package. The connector 600 may be implemented using solder bumps or solder balls.

圖6是例示根據實施方式的半導體封裝件11的截面圖。在圖6中,具有與圖1至圖5中例示相同的形狀的構件表示基本上相同的元件。在圖6中,與圖1至圖5中使用的相同的參考標號表示基本上相同的元件。FIG. 6 is a cross-sectional view illustrating the semiconductor package 11 according to the embodiment. In Fig. 6, members having the same shapes as exemplified in Figs. 1 to 5 represent substantially the same elements. In FIG. 6, the same reference numerals as used in FIGS. 1 to 5 denote substantially the same elements.

參照圖6,半導體封裝件11可以包括模製層500-1,模製層500-1具有包括在圖2的半導體封裝件10中的模製層500的擴展形狀。模製層500-1可以包圍柱凸塊400-1的第一側表面401-1,並且可以露出柱凸塊400-1的頂表面402-1。柱凸塊400-1可以穿透模製層500-1,以具有與圖2中例示的柱凸塊400相同的功能。模製層500-1可以覆蓋橋接晶粒200的第四表面202,並且可以延伸以覆蓋橋接晶粒200的與半導體晶粒100相對的第四側表面204。由於模製層500-1覆蓋橋接晶粒200的第四表面202以保護橋接晶粒200,因此橋接晶粒200不會暴露於外部環境。因此,模製層500-1可以抑制因外部環境造成的橋接晶粒200的損壞或者在橋接晶粒200中形成裂縫。另外,模製層500-1可以延伸以覆蓋半導體晶粒100的與接觸墊110相對的第二表面102。Referring to FIG. 6, the semiconductor package 11 may include a mold layer 500-1 having an expanded shape of the mold layer 500 included in the semiconductor package 10 of FIG. 2. The molding layer 500-1 may surround the first side surface 401-1 of the stud bump 400-1, and may expose the top surface 402-1 of the stud bump 400-1. The stud bump 400-1 may penetrate the mold layer 500-1 to have the same function as the stud bump 400 illustrated in FIG. 2. The molding layer 500-1 may cover the fourth surface 202 of the bridge die 200 and may extend to cover the fourth side surface 204 of the bridge die 200 opposite to the semiconductor die 100. Since the molding layer 500-1 covers the fourth surface 202 of the bridge die 200 to protect the bridge die 200, the bridge die 200 will not be exposed to the external environment. Therefore, the molding layer 500-1 can suppress damage to the bridge die 200 or the formation of cracks in the bridge die 200 caused by the external environment. In addition, the molding layer 500-1 may extend to cover the second surface 102 of the semiconductor die 100 opposite to the contact pad 110.

圖7是例示根據實施方式的半導體封裝件12的截面圖。圖8是例示根據實施方式的半導體封裝件12-S的截面圖。圖8中例示的半導體封裝件12-S可以對應於包括垂直堆疊的一對半導體封裝件12的堆疊封裝。在圖7和圖8中,具有與圖1至圖5中例示相同的形狀的構件表示基本上相同的元件。在圖7和圖8中,與圖1至圖5中使用的相同的參考標號表示基本上相同的元件。FIG. 7 is a cross-sectional view illustrating the semiconductor package 12 according to the embodiment. FIG. 8 is a cross-sectional view illustrating a semiconductor package 12-S according to an embodiment. The semiconductor package 12 -S illustrated in FIG. 8 may correspond to a stack package including a pair of semiconductor packages 12 stacked vertically. In FIGS. 7 and 8, members having the same shapes as exemplified in FIGS. 1 to 5 represent substantially the same elements. In FIGS. 7 and 8, the same reference numerals as those used in FIGS. 1 to 5 denote substantially the same elements.

參照圖7,半導體封裝件12可以包括位於半導體晶粒100一側的橋接晶粒200-2。半導體封裝件12還可以包括將橋接晶粒200-2的通孔210電連接到半導體晶粒100的接觸墊110的重分佈線300-2。虛設晶粒250可以位於半導體晶粒100的與橋接晶粒200-2相對的另一側。Referring to FIG. 7, the semiconductor package 12 may include a bridge die 200-2 located on one side of the semiconductor die 100. The semiconductor package 12 may further include a redistribution line 300-2 that electrically connects the through hole 210 of the bridge die 200-2 to the contact pad 110 of the semiconductor die 100. The dummy die 250 may be located on the other side of the semiconductor die 100 opposite to the bridge die 200-2.

與橋接晶粒200-2不同,虛設晶粒250可以沒有通孔。但是,可以在虛設晶粒250上設置第二虛設墊370-5。當連接器600-2附接到與穿透橋接晶粒200-2的主體的通孔210連接的通孔墊370-2時,虛設連接器600-5可以附接到第二虛設墊370-5。第二虛設墊370-5可以與半導體晶粒100電絕緣。設置在虛設晶粒250上的第二虛設柱凸塊400-5也可以與半導體晶粒100電絕緣。Unlike the bridge die 200-2, the dummy die 250 may not have through holes. However, a second dummy pad 370-5 may be provided on the dummy die 250. When the connector 600-2 is attached to the via pad 370-2 connected with the via 210 penetrating the body of the bridge die 200-2, the dummy connector 600-5 may be attached to the second dummy pad 370- 5. The second dummy pad 370-5 may be electrically insulated from the semiconductor die 100. The second dummy stud bump 400-5 provided on the dummy die 250 may also be electrically insulated from the semiconductor die 100.

虛設晶粒250可以對應於具有小於橋接晶粒200-2的寬度W1的寬度W2的半導體晶粒。因此,與虛設晶粒250具有與橋接晶粒200-2相同的寬度的情況相比,能夠減小半導體封裝件12的總寬度W3。在平面圖中,虛設晶粒250和橋接晶粒200-2可以在垂直於寬度方向的方向上具有基本上相同的長度。在其它實施方式中,虛設晶粒250可以具有與橋接晶粒200-2基本上相同的大小。另選地,虛設晶粒250的大小可以是與橋接晶粒200-2大致相同的大小。The dummy die 250 may correspond to a semiconductor die having a width W2 smaller than the width W1 of the bridge die 200-2. Therefore, compared with the case where the dummy die 250 has the same width as the bridge die 200-2, the total width W3 of the semiconductor package 12 can be reduced. In a plan view, the dummy die 250 and the bridge die 200-2 may have substantially the same length in a direction perpendicular to the width direction. In other embodiments, the dummy die 250 may have substantially the same size as the bridge die 200-2. Alternatively, the size of the dummy die 250 may be approximately the same size as the bridge die 200-2.

參照圖7和圖8,由於虛設晶粒250和橋接晶粒200-2分別位於半導體晶粒100的兩側,因此半導體封裝件12可以由於虛設晶粒250的凸塊連接結構而具有穩定的結構。因此,當具有與半導體封裝件12相同配置的第一子封裝件12-1和具有與半導體封裝件12相同配置的第二子封裝件12-2垂直地堆疊以提供半導體封裝件12-S時,半導體封裝件12-S可以被很好地平衡。7 and 8, since the dummy die 250 and the bridge die 200-2 are respectively located on both sides of the semiconductor die 100, the semiconductor package 12 may have a stable structure due to the bump connection structure of the dummy die 250 . Therefore, when the first sub-package 12-1 having the same configuration as the semiconductor package 12 and the second sub-package 12-2 having the same configuration as the semiconductor package 12 are vertically stacked to provide the semiconductor package 12-S , The semiconductor package 12-S can be well balanced.

第一子封裝件12-1和第二子封裝件12-2可以彼此物理地接合,並且可以通過連接器600-2彼此電連接。在這種情況下,設置在第一子封裝件12-1的虛設晶粒250-1上的第二虛設柱凸塊400-5可以使用虛設連接器600-5接合到設置在第二子封裝件12-2的虛設晶粒250-2上的第二虛設墊370-5。虛設連接器600-5、第二虛設柱凸塊400-5、第二虛設墊370-5以及虛設晶粒250-1和250-2可以充當用於防止第二子封裝件12-2傾斜的平衡件。也就是說,可以引入虛設連接器600-5、第二虛設柱凸塊400-5、第二虛設墊370-5以及虛設晶粒250-1和250-2,以在第二子封裝件12-2堆疊在第一子封裝件12-1上時保持平衡。因此,虛設連接器600-5、第二虛設柱凸塊400-5、第二虛設墊370-5以及虛設晶粒250-1和250-2可以提供半導體封裝件12-S的對稱結構,以防止由於半導體封裝件12-S的不對稱結構而產生半導體封裝件12-S的物理缺陷。The first sub-package 12-1 and the second sub-package 12-2 may be physically bonded to each other, and may be electrically connected to each other through the connector 600-2. In this case, the second dummy stud bump 400-5 provided on the dummy die 250-1 of the first sub-package 12-1 may be bonded to the second sub-package using the dummy connector 600-5. The second dummy pad 370-5 on the dummy die 250-2 of the part 12-2. The dummy connector 600-5, the second dummy pillar bump 400-5, the second dummy pad 370-5, and the dummy dies 250-1 and 250-2 may serve as a device for preventing the second sub-package 12-2 from tilting. Balance pieces. That is to say, the dummy connector 600-5, the second dummy pillar bump 400-5, the second dummy pad 370-5, and the dummy dies 250-1 and 250-2 can be introduced to install the second sub-package 12 -2 keeps balance when stacked on the first sub-package 12-1. Therefore, the dummy connector 600-5, the second dummy pillar bump 400-5, the second dummy pad 370-5, and the dummy dies 250-1 and 250-2 can provide a symmetrical structure of the semiconductor package 12-S, Prevent the occurrence of physical defects of the semiconductor package 12-S due to the asymmetric structure of the semiconductor package 12-S.

圖9是例示根據實施方式的半導體封裝件13的截面圖。在圖9中,具有與圖1至圖5中例示相同的形狀的構件表示基本上相同的元件。在圖9中,與圖1至圖5中使用的相同的參考標號表示基本上相同的元件。FIG. 9 is a cross-sectional view illustrating the semiconductor package 13 according to the embodiment. In FIG. 9, members having the same shapes as exemplified in FIGS. 1 to 5 represent substantially the same elements. In FIG. 9, the same reference numerals as those used in FIGS. 1 to 5 denote substantially the same elements.

參照圖9,半導體封裝件13可以被配置為包括垂直堆疊在封裝基板700上的多個子封裝件(即,第一子封裝件10-1、第二子封裝件10-2、第三子封裝件10-3和第四子封裝件10-4)。封裝基板700可以包括具有電路互連線的互連結構層,例如,印刷電路板(PCB)或中介層。雖然圖9例示了半導體封裝件13包括第一子封裝件10-1、第二子封裝件10-2、第三子封裝件10-3和第四子封裝件10-4的示例,但是可以根據各個實施方式將子封裝件的數目設置成不同。外部連接器750可以附接到封裝基板700,以將半導體封裝件13電連接到另一電子系統。9, the semiconductor package 13 may be configured to include a plurality of sub-packages (ie, a first sub-package 10-1, a second sub-package 10-2, a third sub-package 10-3 and the fourth sub-package 10-4). The package substrate 700 may include an interconnection structure layer having circuit interconnection lines, for example, a printed circuit board (PCB) or an interposer. Although FIG. 9 illustrates an example in which the semiconductor package 13 includes the first sub-package 10-1, the second sub-package 10-2, the third sub-package 10-3, and the fourth sub-package 10-4, it may The number of sub-packages is set to be different according to various embodiments. The external connector 750 may be attached to the package substrate 700 to electrically connect the semiconductor package 13 to another electronic system.

第一子封裝件10-1、第二子封裝件10-2、第三子封裝件10-3和第四子封裝件10-4中的每一個可以具有與參照圖1至圖5描述的半導體封裝件10基本上相同的配置。第一子封裝件10-1、第二子封裝件10-2、第三子封裝件10-3和第四子封裝件10-4中的每一個可以被配置為包括半導體晶粒100、分別設置在半導體晶粒100兩側的一對橋接晶粒200、柱凸塊400、模製層500(下文中,被稱為第一模製層)和重分佈線300。第一子封裝件10-1、第二子封裝件10-2、第三子封裝件10-3和第四子封裝件10-4可以通過連接器600彼此電連接。連接器600可以將上子封裝件(例如,第二子封裝件10-2)的通孔墊370電連接到下子封裝件(例如,第一子封裝件10-1)的柱凸塊400。連接器600可以直接接合到下子封裝件(例如,第一子封裝件10-1)的柱凸塊400。柱凸塊400中的每一個的頂表面402可以具有足以與連接器600中的任一個接觸的面積。因此,在柱凸塊400上可以不需要額外的導電墊。Each of the first sub-package 10-1, the second sub-package 10-2, the third sub-package 10-3, and the fourth sub-package 10-4 may have the same as those described with reference to FIGS. 1 to 5 The semiconductor package 10 has basically the same configuration. Each of the first sub-package 10-1, the second sub-package 10-2, the third sub-package 10-3, and the fourth sub-package 10-4 may be configured to include the semiconductor die 100, respectively A pair of bridge dies 200, stud bumps 400, a molding layer 500 (hereinafter, referred to as a first molding layer), and redistribution lines 300 are provided on both sides of the semiconductor die 100. The first sub package 10-1, the second sub package 10-2, the third sub package 10-3 and the fourth sub package 10-4 may be electrically connected to each other through the connector 600. The connector 600 may electrically connect the via pad 370 of the upper sub-package (for example, the second sub-package 10-2) to the stud bump 400 of the lower sub-package (for example, the first sub-package 10-1). The connector 600 may be directly bonded to the pillar bump 400 of the lower sub-package (for example, the first sub-package 10-1). The top surface 402 of each of the pillar bumps 400 may have an area sufficient to contact any of the connectors 600. Therefore, no additional conductive pads may be needed on the stud bump 400.

半導體封裝件13還可以包括覆蓋並保護第一子封裝件10-1、第二子封裝件10-2、第三子封裝件10-3和第四子封裝件10-4的堆疊結構的第二模製層500-3。第二模製層500-3可以延伸以填充第一子封裝件10-1、第二子封裝件10-2、第三子封裝件10-3和第四子封裝件10-4之間的空間。第二模製層500-3可以包含諸如環氧樹脂模製化合物(EMC)材料這樣的包封材料。The semiconductor package 13 may further include a second sub-package that covers and protects the stack structure of the first sub-package 10-1, the second sub-package 10-2, the third sub-package 10-3, and the fourth sub-package 10-4. Two molded layers 500-3. The second molding layer 500-3 may extend to fill the gap between the first sub-package 10-1, the second sub-package 10-2, the third sub-package 10-3, and the fourth sub-package 10-4 space. The second molding layer 500-3 may include an encapsulating material such as an epoxy molding compound (EMC) material.

圖9中的半導體封裝件13例示了圖1的半導體封裝件10被用在模組封裝中或者用作堆疊封裝中的能夠堆疊的子封裝件的示例。半導體封裝件(圖1中的10)的橋接晶粒(圖1中的200)可以提供用於將垂直堆疊的第一子封裝件10-1、第二子封裝件10-2、第三子封裝件10-3和第四子封裝件10-4彼此電連接的垂直互連結構。圖6或圖7中例示的半導體封裝件11或12也可以被用作構成諸如圖9中的半導體封裝件13這樣的堆疊封裝的子封裝件。The semiconductor package 13 in FIG. 9 illustrates an example in which the semiconductor package 10 of FIG. 1 is used in a module package or as a stackable sub-package in a stacked package. The bridge die (200 in FIG. 1) of the semiconductor package (10 in FIG. 1) can provide a first sub-package 10-1, a second sub-package 10-2, and a third sub-package that are vertically stacked. A vertical interconnection structure in which the package 10-3 and the fourth sub package 10-4 are electrically connected to each other. The semiconductor package 11 or 12 illustrated in FIG. 6 or FIG. 7 may also be used as a sub-package constituting a stacked package such as the semiconductor package 13 in FIG. 9.

如上所述,圖9中的半導體封裝件13可以採用圖1的半導體封裝件10作為垂直堆疊以構成半導體封裝件13的子封裝件中的每一個。因此,半導體封裝件13可以提供具有大容量的緊湊封裝。As described above, the semiconductor package 13 in FIG. 9 may adopt the semiconductor package 10 of FIG. 1 as a vertical stack to constitute each of the sub-packages of the semiconductor package 13. Therefore, the semiconductor package 13 can provide a compact package with a large capacity.

根據各個實施方式,半導體封裝件10可以被設置成包括半導體晶粒100和與半導體晶粒100間隔開的橋接晶粒200。另外,包括半導體晶粒100和與半導體晶粒100間隔開的橋接晶粒200的半導體封裝件10可以被用作垂直堆疊的多個子封裝件中的每一個,以提供與堆疊封裝對應的半導體封裝件13。According to various embodiments, the semiconductor package 10 may be provided to include a semiconductor die 100 and a bridge die 200 spaced apart from the semiconductor die 100. In addition, the semiconductor package 10 including the semiconductor die 100 and the bridge die 200 spaced apart from the semiconductor die 100 may be used as each of a plurality of sub-packages stacked vertically to provide a semiconductor package corresponding to the stacked package Piece 13.

圖10是例示根據實施方式的半導體封裝件的第一子封裝件1010的截面圖。FIG. 10 is a cross-sectional view illustrating the first sub-package 1010 of the semiconductor package according to the embodiment.

參照圖10,根據實施方式,第一子封裝件1010可以是半導體封裝件的單元組件。單元組件(例如第一子封裝件1010)可以重複並且垂直地堆疊以形成半導體封裝件。第一子封裝件1010可以被配置為包括第一重分佈線結構1100、第一半導體晶粒1200、第一橋接晶粒1300和第一模製層1400。在以下描述中,術語“第一”、“第二”等僅用於區分一個元件與另一元件,而不用於表示元件的特定順序。10, according to an embodiment, the first sub-package 1010 may be a unit component of a semiconductor package. The unit components (for example, the first sub-package 1010) may be repeatedly and vertically stacked to form a semiconductor package. The first sub-package 1010 may be configured to include a first redistribution line structure 1100, a first semiconductor die 1200, a first bridge die 1300 and a first mold layer 1400. In the following description, the terms “first”, “second”, etc. are only used to distinguish one element from another element, and not used to indicate a specific order of the elements.

第一半導體晶粒1200可以設置在第一重分佈線結構1100上。第一重分佈線結構1100可以包括頂表面1102和底表面1101,這兩個表面彼此相對。第一半導體晶粒1200也可以包括彼此相對的底表面1201和頂表面1202。第一半導體晶粒1200可以安裝在第一重分佈線結構1100上,使得第一半導體晶粒1200的底表面1201面對第一重分佈線結構1100的頂表面1102。第一半導體晶粒1200可以電連接到第一重分佈線結構1100。The first semiconductor die 1200 may be disposed on the first redistribution line structure 1100. The first redistribution line structure 1100 may include a top surface 1102 and a bottom surface 1101, and the two surfaces are opposite to each other. The first semiconductor die 1200 may also include a bottom surface 1201 and a top surface 1202 opposite to each other. The first semiconductor die 1200 may be mounted on the first redistribution line structure 1100 such that the bottom surface 1201 of the first semiconductor die 1200 faces the top surface 1102 of the first redistribution line structure 1100. The first semiconductor die 1200 may be electrically connected to the first redistribution line structure 1100.

第一橋接晶粒1300可以設置在第一重分佈線結構1100上。第一橋接晶粒1300可以設置成與第一半導體晶粒1200橫向間隔開。在這種情況下,第一橋接晶粒1300可以分別設置在第一半導體晶粒1200的兩側。當從平面圖觀察時,第一重分佈線結構1100可以延伸為具有從第一半導體晶粒1200的側表面橫向突出的延伸部。第一橋接晶粒1300可設置在第一重分佈線結構1100的延伸部上。The first bridge die 1300 may be disposed on the first redistribution line structure 1100. The first bridge die 1300 may be disposed to be laterally spaced apart from the first semiconductor die 1200. In this case, the first bridge die 1300 may be provided on both sides of the first semiconductor die 1200, respectively. When viewed from a plan view, the first redistribution line structure 1100 may extend to have an extension part protruding laterally from the side surface of the first semiconductor die 1200. The first bridge die 1300 may be disposed on the extension portion of the first redistribution line structure 1100.

可以形成第一模製層1400以覆蓋第一重分佈線結構1100的頂表面1102的部分。第一模製層1400可以延伸以與第一重分佈線結構1100的頂表面1102接觸。第一模製層1400可以固定第一半導體晶粒1200和第一橋接晶粒1300。第一模製層1400可以延伸以部分地覆蓋第一半導體晶粒1200的側表面1203。第一模製層1400可以圍繞第一半導體晶粒1200的側表面1203。The first molding layer 1400 may be formed to cover a portion of the top surface 1102 of the first redistribution line structure 1100. The first molding layer 1400 may extend to contact the top surface 1102 of the first redistribution line structure 1100. The first molding layer 1400 may fix the first semiconductor die 1200 and the first bridge die 1300. The first molding layer 1400 may extend to partially cover the side surface 1203 of the first semiconductor die 1200. The first molding layer 1400 may surround the side surface 1203 of the first semiconductor die 1200.

第一模製層1400可以被設置成露出第一半導體晶粒1200的側表面1203的上部1203U。第一模製層1400可以被設置為露出第一半導體晶粒1200的頂表面1202。因為第一模製層1400被設置成露出第一半導體晶粒1200的側表面1203的上部1203U和第一半導體晶粒1200的頂表面1202的整個部分,所以由第一半導體晶粒1200的工作產生的熱量可以更容易地從第一半導體晶粒1200朝向第一半導體晶粒1200的外部區域散發。因此,可以抑制或防止由於被局限在第一半導體晶粒1200中的熱量所引起的第一半導體晶粒1200的性能劣化。The first molding layer 1400 may be disposed to expose the upper portion 1203U of the side surface 1203 of the first semiconductor die 1200. The first molding layer 1400 may be disposed to expose the top surface 1202 of the first semiconductor die 1200. Because the first mold layer 1400 is provided to expose the upper portion 1203U of the side surface 1203 of the first semiconductor die 1200 and the entire portion of the top surface 1202 of the first semiconductor die 1200, it is generated by the work of the first semiconductor die 1200 The heat of this can be more easily dissipated from the first semiconductor die 1200 toward the outer area of the first semiconductor die 1200. Therefore, it is possible to suppress or prevent the performance degradation of the first semiconductor die 1200 due to the heat confined in the first semiconductor die 1200.

第一模製層1400可以延伸以填充第一半導體晶粒1200與第一橋接晶粒1300之間的空間。第一模製層1400可以延伸為部分地圍繞第一橋接晶粒1300的側表面。The first molding layer 1400 may extend to fill the space between the first semiconductor die 1200 and the first bridge die 1300. The first molding layer 1400 may extend to partially surround the side surface of the first bridging die 1300.

第一模製層1400可以被形成為包括各種類型的囊封材料中的一種或者各種類型的介電材料中的任一種。例如,第一模製層1400可以使用模製製程利用環氧樹脂模製化合物(EMC)材料形成。在形成EMC層以覆蓋第一半導體晶粒1200和第一橋接晶粒1300之後,可以使EMC層凹入(recessed)以露出第一半導體晶粒1200的頂表面1202。The first molding layer 1400 may be formed to include one of various types of encapsulation materials or any one of various types of dielectric materials. For example, the first molding layer 1400 may be formed using an epoxy molding compound (EMC) material using a molding process. After the EMC layer is formed to cover the first semiconductor die 1200 and the first bridge die 1300, the EMC layer may be recessed to expose the top surface 1202 of the first semiconductor die 1200.

可以通過部分地蝕刻覆蓋第一半導體晶粒1200和第一橋接晶粒1300的EMC層而使EMC層凹入,從而露出第一半導體晶粒1200的側表面1203的上部1203U。第一模製層1400可以凹入以露出被包括在每一個第一橋接晶粒1300中的第一柱凸塊1340的頂表面1340U。The EMC layer may be recessed by partially etching the EMC layer covering the first semiconductor die 1200 and the first bridge die 1300, thereby exposing the upper portion 1203U of the side surface 1203 of the first semiconductor die 1200. The first molding layer 1400 may be recessed to expose the top surface 1340U of the first stud bump 1340 included in each first bridge die 1300.

與印刷電路板(PCB)或矽中介層(interposer)不同,第一重分佈線結構1100可以直接接觸第一半導體晶粒1200、第一橋接晶粒1300和第一模製層1400。第一重分佈線結構1100可以具有多層結構,該多層結構包括第一介電層1110、第二介電層1120和設置在第一介電層1110和第二介電層1120之間的第一重分佈線圖案1130。Unlike a printed circuit board (PCB) or a silicon interposer, the first redistribution line structure 1100 can directly contact the first semiconductor die 1200, the first bridge die 1300, and the first molding layer 1400. The first redistribution line structure 1100 may have a multilayer structure including a first dielectric layer 1110, a second dielectric layer 1120, and a first dielectric layer 1110 and a second dielectric layer 1120. Redistribute the line pattern 1130.

整合有第一介電層1110、第一重分佈線圖案1130和第二介電層1120的結構(即,第一重分佈線結構1100)可以與包括第一半導體晶粒1200、第一橋接晶粒1300和第一模製層1400的結構的底表面直接接觸。這樣,由於第一重分佈線結構1100具有堆疊結構,所以與第一重分佈線結構1100由PCB或中介層代替的情況相比,第一子封裝件1010可以具有相對較薄的結構。The structure that integrates the first dielectric layer 1110, the first redistribution line pattern 1130, and the second dielectric layer 1120 (ie, the first redistribution line structure 1100) may be integrated with the first semiconductor die 1200 and the first bridge die. The particles 1300 are in direct contact with the bottom surface of the structure of the first molding layer 1400. In this way, since the first redistribution line structure 1100 has a stacked structure, the first sub-package 1010 may have a relatively thin structure compared to the case where the first redistribution line structure 1100 is replaced by a PCB or an interposer.

第一重分佈線結構1100可以用作將第一半導體晶粒1200電連接到第一橋接晶粒1300的互連結構。第一重分佈線結構1100的第一重分佈線圖案1130可以是用於將第一半導體晶粒1200的第一連接墊1210電連接到第一橋接晶粒1300的第一通孔墊1320的導電圖案。第一半導體晶粒1200的第一連接墊1210可以是設置在第一半導體晶粒1200的底表面1201上的電連接端子。第一橋接晶粒1300的第一通孔墊1320可以是設置在第一橋接晶粒1300的底表面(即,第一橋接晶粒1300的第一主體1310的底表面1311)上的電連接端子。The first redistribution line structure 1100 may be used as an interconnect structure that electrically connects the first semiconductor die 1200 to the first bridge die 1300. The first redistribution line pattern 1130 of the first redistribution line structure 1100 may be a conductive material for electrically connecting the first connection pad 1210 of the first semiconductor die 1200 to the first via pad 1320 of the first bridge die 1300 pattern. The first connection pad 1210 of the first semiconductor die 1200 may be an electrical connection terminal disposed on the bottom surface 1201 of the first semiconductor die 1200. The first via pad 1320 of the first bridge die 1300 may be an electrical connection terminal provided on the bottom surface of the first bridge die 1300 (ie, the bottom surface 1311 of the first body 1310 of the first bridge die 1300) .

第一重分佈線圖案1130的第一端可以接合到第一連接墊1210,並且第一重分佈線圖案1130的第二端可以接合到第一通孔墊1320。可以通過在第一介電層1110上沉積導電材料並且通過利用蝕刻製程圖案化導電材料來形成第一重分佈線圖案1130。另選地,可以通過電鍍製程來形成第一重分佈線圖案1130。第一重分佈線圖案1130可以被形成為包括諸如銅層的金屬層。The first end of the first redistribution line pattern 1130 may be bonded to the first connection pad 1210, and the second end of the first redistribution line pattern 1130 may be bonded to the first via pad 1320. The first redistribution line pattern 1130 may be formed by depositing a conductive material on the first dielectric layer 1110 and patterning the conductive material by using an etching process. Alternatively, the first redistribution line pattern 1130 may be formed through an electroplating process. The first redistribution line pattern 1130 may be formed to include a metal layer such as a copper layer.

第一重分佈線結構1100還可以用作用於將第一半導體晶粒1200電連接到外部裝置、外部基板或外部模組的互連結構。外部連接器1500可以電連接到第一重分佈線結構1100的第一重分佈線圖案1130。外部連接器1500可以是焊料球。The first redistribution line structure 1100 may also be used as an interconnection structure for electrically connecting the first semiconductor die 1200 to an external device, an external substrate, or an external module. The external connector 1500 may be electrically connected to the first redistribution line pattern 1130 of the first redistribution line structure 1100. The external connector 1500 may be a solder ball.

圖11是例示圖1的第一子封裝件1010的平面圖。圖10是沿圖11的線X-X'截取的截面圖。圖11對應於第一半導體晶粒1200、第一橋接晶粒1300和第一模製層1400的仰視圖。FIG. 11 is a plan view illustrating the first sub-package 1010 of FIG. 1. Fig. 10 is a cross-sectional view taken along line XX' of Fig. 11. FIG. 11 corresponds to a bottom view of the first semiconductor die 1200, the first bridge die 1300, and the first molding layer 1400.

參照圖10和圖11,附加的第一半導體晶粒1200-1可以設置成與第一半導體晶粒1200間隔開。在這種情況下,還可以分別在附加的第一半導體晶粒1200-1的兩側設置兩個附加的第一橋接晶粒1300。每一個第一橋接晶粒1300可以包括多個第一通孔1330,並且第一通孔墊1320可以連接到相應的第一通孔1330。10 and 11, the additional first semiconductor die 1200-1 may be provided to be spaced apart from the first semiconductor die 1200. In this case, two additional first bridge dies 1300 may also be provided on both sides of the additional first semiconductor die 1200-1, respectively. Each first bridge die 1300 may include a plurality of first via holes 1330, and the first via pad 1320 may be connected to the corresponding first via hole 1330.

圖12是例示被包括在根據實施方式的半導體封裝件中的第一橋接晶粒1300的截面圖。FIG. 12 is a cross-sectional view illustrating the first bridge die 1300 included in the semiconductor package according to the embodiment.

參照圖10和圖12,第一橋接晶粒1300可以被配置為包括第一主體1310、第一通孔墊1320、第一通孔1330和第一柱凸塊1340。第一主體1310可以是具有彼此相對的底表面1311和頂表面1312的基板。第一主體1310可以是例如矽基板的半導體基板。在一些其它實施方式中,第一主體1310可以是介電基板。當第一主體1310是矽基板時,使用半導體製程形成第一通孔1330可能是有利的。10 and 12, the first bridge die 1300 may be configured to include a first body 1310, a first via pad 1320, a first via hole 1330, and a first pillar bump 1340. The first body 1310 may be a substrate having a bottom surface 1311 and a top surface 1312 opposite to each other. The first body 1310 may be a semiconductor substrate such as a silicon substrate. In some other embodiments, the first body 1310 may be a dielectric substrate. When the first body 1310 is a silicon substrate, it may be advantageous to use a semiconductor process to form the first through hole 1330.

第一通孔1330可以垂直穿透第一主體1310。也就是說,第一通孔1330可以從第一主體1310的底表面1311延伸到第一主體1310的頂表面1312。在形成第一通孔1330時,可以使用一些半導體製程(包括應用於矽晶圓的光微影製程)。The first through hole 1330 may penetrate the first body 1310 vertically. That is, the first through hole 1330 may extend from the bottom surface 1311 of the first body 1310 to the top surface 1312 of the first body 1310. When forming the first through hole 1330, some semiconductor processes (including photolithography processes applied to silicon wafers) can be used.

因此,第一通孔1330可以是具有細小直徑D11的直通矽穿孔(TSV)。第一通孔1330可以包括銅層。與模塑通孔(TMV)相比,TSV可以具有相對較小的直徑。因此,可以增加在有限區域中形成的第一通孔1330的數量。因為TMV的直徑大於TSV的直徑,所以與TSV相反,可能難以在有限區域內密集地形成TMV。Therefore, the first through hole 1330 may be a through silicon via (TSV) with a small diameter D11. The first via 1330 may include a copper layer. Compared to molded through holes (TMV), TSVs can have a relatively small diameter. Therefore, the number of first through holes 1330 formed in a limited area can be increased. Because the diameter of the TMV is larger than the diameter of the TSV, in contrast to the TSV, it may be difficult to densely form the TMV in a limited area.

如上所述,可以使用TSV技術形成第一通孔1330。因此,可以在第一主體1310的有限區域中形成第一通孔1330,使得第一通孔1330對應於第一橋接晶粒1300的許多輸入/輸出(I/O)端子和電源/接地端子。As described above, the TSV technology may be used to form the first through hole 1330. Therefore, the first through holes 1330 may be formed in a limited area of the first body 1310 such that the first through holes 1330 correspond to many input/output (I/O) terminals and power/ground terminals of the first bridge die 1300.

如果第一通孔1330的直徑D11減小,則第一通孔1330的長度L也可能減小。第一主體1310可以被配置為包括第一通孔1330基本穿透的芯部1315和覆蓋芯部1315的第三介電層1316。第三介電層1316可以是使第一通孔墊1320彼此電隔離和絕緣的介電層。芯部1315可以是矽基板。第一通孔墊1320可以是將第一通孔1330連接到第一重分佈線結構(圖10的1100)的第一重分佈線圖案(圖10的1130)的連接元件。If the diameter D11 of the first through hole 1330 is reduced, the length L of the first through hole 1330 may also be reduced. The first body 1310 may be configured to include a core 1315 through which the first through hole 1330 substantially penetrates and a third dielectric layer 1316 covering the core 1315. The third dielectric layer 1316 may be a dielectric layer that electrically isolates and insulates the first via pads 1320 from each other. The core 1315 may be a silicon substrate. The first via pad 1320 may be a connection element that connects the first via 1330 to the first redistribution line pattern (1130 of FIG. 10) of the first redistribution line structure (1100 of FIG. 10).

第一通孔1330可以被形成為具有對應於芯部1315的厚度T12-1的長度L,並且芯部1315的厚度T12-1可以小於第一主體1310的厚度T12。在這種情況下,由於其中形成每一個第一通孔1330的通孔的寬高比的限制,在減小第一橋接晶粒1300中的第一通孔1330的直徑D11方面可能存在限制。為了減小第一橋接晶粒1300中的第一通孔1330的直徑D11,可能需要減小第一主體1310的厚度T12或芯部1315的厚度T12-1以克服形成每一個第一通孔1330的通孔的寬高比的限制。如果第一主體1310的厚度T12變得小於第一半導體晶粒1200的厚度(圖10的T11),則也可以減小第一通孔1330的直徑D11。因此,可以增加形成在第一主體1310中的第一通孔1330的數量。The first through hole 1330 may be formed to have a length L corresponding to the thickness T12-1 of the core 1315, and the thickness T12-1 of the core 1315 may be smaller than the thickness T12 of the first body 1310. In this case, due to the limitation of the aspect ratio of the through hole in which each first through hole 1330 is formed, there may be a limitation in reducing the diameter D11 of the first through hole 1330 in the first bridge die 1300. In order to reduce the diameter D11 of the first through hole 1330 in the first bridge die 1300, it may be necessary to reduce the thickness T12 of the first body 1310 or the thickness T12-1 of the core 1315 to overcome the formation of each first through hole 1330. The aspect ratio of the through hole is limited. If the thickness T12 of the first body 1310 becomes smaller than the thickness of the first semiconductor die 1200 (T11 in FIG. 10), the diameter D11 of the first through hole 1330 may also be reduced. Therefore, the number of first through holes 1330 formed in the first body 1310 may be increased.

第一橋接晶粒1300的第一通孔墊1320可以設置在第一橋接晶粒1300的底表面(即,第一主體1310的底表面1311)上,以連接到第一通孔1330。第一通孔墊1320可以是被設置成與第一通孔1330重疊的電連接端子。The first via pad 1320 of the first bridging die 1300 may be disposed on the bottom surface of the first bridging die 1300 (ie, the bottom surface 1311 of the first body 1310) to be connected to the first via 1330. The first via pad 1320 may be an electrical connection terminal arranged to overlap the first via 1330.

第一柱凸塊1340可以連接到第一通孔1330。第一柱凸塊1340可以設置在第一通孔1330的與第一通孔墊1320相對的頂表面上。第一柱凸塊1340可以被設置成從第一主體1310的頂表面1312突出。第一柱凸塊1340可以具有直徑D12,直徑D12大於第一通孔1330的直徑D11。第一柱凸塊1340可以具有對應於距第一主體1310的頂表面1312的厚度T13的垂直高度,以補償第一主體1310的厚度T12。The first pillar bump 1340 may be connected to the first through hole 1330. The first pillar bump 1340 may be disposed on the top surface of the first through hole 1330 opposite to the first through hole pad 1320. The first pillar bump 1340 may be provided to protrude from the top surface 1312 of the first body 1310. The first pillar bump 1340 may have a diameter D12, which is larger than the diameter D11 of the first through hole 1330. The first pillar bump 1340 may have a vertical height corresponding to the thickness T13 from the top surface 1312 of the first body 1310 to compensate for the thickness T12 of the first body 1310.

結果,第一橋接晶粒1300可以具有對應於第一主體1310的厚度T12和第一柱凸塊1340的厚度T13之和的第一高度H11。由於第一柱凸塊1340的存在,可以相對減小第一主體1310的厚度T12而不減小第一橋接晶粒1300的第一高度H11。因此,可以進一步減小第一通孔1330的直徑D11,以增加形成在第一主體1310的有限區域中的第一通孔1330的數量。As a result, the first bridge die 1300 may have a first height H11 corresponding to the sum of the thickness T12 of the first body 1310 and the thickness T13 of the first stud bump 1340. Due to the existence of the first pillar bump 1340, the thickness T12 of the first body 1310 can be relatively reduced without reducing the first height H11 of the first bridge die 1300. Therefore, the diameter D11 of the first through hole 1330 may be further reduced to increase the number of the first through hole 1330 formed in the limited area of the first body 1310.

再次參照圖10,第一橋接晶粒1300可以具有第一高度H11,並且可以設置在第一重分佈線結構1100上。第一高度H11可以對應於第一重分佈線結構1100的頂表面1102的水平與第一柱凸塊1340的頂表面1340U的水平之間的距離。第一半導體晶粒1200可以具有第二高度H12,並且可以被設置在第一橋接晶粒1300之間。第二高度H12可以對應於第一重分佈線結構1100的頂表面1102的水平與第一半導體晶粒1200的頂表面1202的水平之間的距離。第一橋接晶粒1300的第一高度H11可以小於第一半導體晶粒1200的第二高度H12。因此,在第一橋接晶粒1300和第一半導體晶粒1200之間可以存在水平差H13。因為第一橋接晶粒1300的第一高度H11小於第一半導體晶粒1200的第二高度H12,所以可以存在水平差H13。第一柱凸塊1340的頂表面1340U可以位於比第一半導體晶粒1200的頂表面1202的水平低水平差H13的水平處。Referring again to FIG. 10, the first bridge die 1300 may have a first height H11 and may be disposed on the first redistribution line structure 1100. The first height H11 may correspond to the distance between the level of the top surface 1102 of the first redistribution line structure 1100 and the level of the top surface 1340U of the first pillar bump 1340. The first semiconductor die 1200 may have a second height H12, and may be disposed between the first bridge dies 1300. The second height H12 may correspond to the distance between the level of the top surface 1102 of the first redistribution line structure 1100 and the level of the top surface 1202 of the first semiconductor die 1200. The first height H11 of the first bridge die 1300 may be smaller than the second height H12 of the first semiconductor die 1200. Therefore, there may be a level difference H13 between the first bridge die 1300 and the first semiconductor die 1200. Since the first height H11 of the first bridge die 1300 is smaller than the second height H12 of the first semiconductor die 1200, there may be a level difference H13. The top surface 1340U of the first stud bump 1340 may be located at a level lower than the level of the top surface 1202 of the first semiconductor die 1200 by a level difference H13.

因為在第一橋接晶粒1300和第一半導體晶粒1200之間存在水平差H13,所以第一子封裝件1010可以具有中間部分1010H和凹入邊緣部分1010R,凹入邊緣部分1010R的頂表面低於中間部分1010H的頂表面。因此,由於水平差H13,第一子封裝件1010的中間部分1010H和凹入邊緣部分1010R可以提供台階結構。Because there is a level difference H13 between the first bridge die 1300 and the first semiconductor die 1200, the first sub-package 1010 may have a middle portion 1010H and a concave edge portion 1010R, and the top surface of the concave edge portion 1010R is low. On the top surface of the middle portion 1010H. Therefore, due to the level difference H13, the middle portion 1010H and the recessed edge portion 1010R of the first sub-package 1010 may provide a stepped structure.

第一子封裝件1010的中間部分1010H可以是設置有第一半導體晶粒1200的區域。第一子封裝件1010的頂表面可以對應於第一半導體晶粒1200的頂表面1202。第一子封裝件1010的凹入邊緣部分1010R可以是設置有第一橋接晶粒1300的區域。第一子封裝件1010的凹入邊緣部分1010R的頂表面可以包括第一柱凸塊1340的頂表面1340U和第一模製層1400的頂表面。第一柱凸塊1340的頂表面1340U可以在第一模製層1400的頂表面處露出。第一模製層1400可以被設置成圍繞第一柱凸塊1340的側表面並且覆蓋第一主體1310。The middle portion 1010H of the first sub-package 1010 may be a region where the first semiconductor die 1200 is provided. The top surface of the first sub-package 1010 may correspond to the top surface 1202 of the first semiconductor die 1200. The recessed edge portion 1010R of the first sub-package 1010 may be a region where the first bridge die 1300 is provided. The top surface of the concave edge portion 1010R of the first sub-package 1010 may include the top surface 1340U of the first stud bump 1340 and the top surface of the first mold layer 1400. The top surface 1340U of the first stud bump 1340 may be exposed at the top surface of the first molding layer 1400. The first molding layer 1400 may be provided to surround the side surface of the first stud bump 1340 and cover the first body 1310.

圖13是例示根據實施方式的半導體封裝件的第二子封裝件1020的截面圖。FIG. 13 is a cross-sectional view illustrating the second sub-package 1020 of the semiconductor package according to the embodiment.

參照圖13,第二子封裝件1020可以被配置成與圖10所示的第一子封裝件1010具有基本相同的形狀。第二子封裝件1020可以被配置為與圖10所示的第一子封裝件1010包括基本相同的元件。第二子封裝件1020可以與圖10所示的第一子封裝件1010具有基本相同的結構。第二子封裝件1020可以被配置為包括第二重分佈線結構S1100、第二半導體晶粒S1200、第二橋接晶粒S1300和第二模製層S1400。Referring to FIG. 13, the second sub-package 1020 may be configured to have substantially the same shape as the first sub-package 1010 shown in FIG. 10. The second sub-package 1020 may be configured to include substantially the same elements as the first sub-package 1010 shown in FIG. 10. The second sub-package 1020 may have substantially the same structure as the first sub-package 1010 shown in FIG. 10. The second sub-package 1020 may be configured to include a second redistribution line structure S1100, a second semiconductor die S1200, a second bridge die S1300, and a second molding layer S1400.

第二橋接晶粒S1300可以具有第四高度H14並且可以設置在第二重分佈線結構S1100上。第四高度H14可以對應於第二重分佈線結構S1100的頂表面S1102的水平與第二橋接晶粒S1300中的第二柱凸塊S1340的頂表面S1340U的水平之間的距離。第二半導體晶粒S1200可以具有第五高度H15,並且可以設置在第二橋接晶粒S1300之間。第五高度H15可以對應於第二重分佈線結構S1100的頂表面S1102的水平與第二半導體晶粒S1200的頂表面S1202的水平之間的距離。第一橋接晶粒S1300的第四高度H14可以小於第二半導體晶粒S1200的第五高度H15。因此,在第二橋接晶粒S1300和第二半導體晶粒S1200之間可以存在水平差H16。因為第二橋接晶粒S1300的第四高度H14小於第二半導體晶粒S1200的第五高度H15,所以可以存在水平差H16。The second bridge die S1300 may have a fourth height H14 and may be disposed on the second redistribution line structure S1100. The fourth height H14 may correspond to the distance between the level of the top surface S1102 of the second redistribution line structure S1100 and the level of the top surface S1340U of the second pillar bump S1340 in the second bridge die S1300. The second semiconductor die S1200 may have a fifth height H15, and may be disposed between the second bridge dies S1300. The fifth height H15 may correspond to the distance between the level of the top surface S1102 of the second redistribution line structure S1100 and the level of the top surface S1202 of the second semiconductor die S1200. The fourth height H14 of the first bridge die S1300 may be smaller than the fifth height H15 of the second semiconductor die S1200. Therefore, there may be a level difference H16 between the second bridge die S1300 and the second semiconductor die S1200. Because the fourth height H14 of the second bridge die S1300 is smaller than the fifth height H15 of the second semiconductor die S1200, there may be a level difference H16.

因為在第二橋接晶粒S1300與第二半導體晶粒S1200之間存在水平差H16,所以第二子封裝件1020可具有中間部分1020H和凹入邊緣部分1020R,凹入邊緣部分1020R的頂表面低於中間部分1020H的頂表面。因此,由於水平差H16,第二子封裝件1020的中間部分1020H和凹入邊緣部分1020R可以提供台階結構。Because there is a level difference H16 between the second bridge die S1300 and the second semiconductor die S1200, the second sub-package 1020 may have a middle portion 1020H and a concave edge portion 1020R, and the top surface of the concave edge portion 1020R is low. On the top surface of the middle portion 1020H. Therefore, due to the level difference H16, the middle portion 1020H and the concave edge portion 1020R of the second sub-package 1020 may provide a stepped structure.

每一個第二橋接晶粒S1300可以被配置為包括第二主體S1310、第二通孔墊S1320、第二通孔S1330和第二柱凸塊S1340。第二模製層S1400可以圍繞第二橋接晶粒S1300的側表面和第二半導體晶粒S1200的側表面以露出第二柱凸塊S1340的頂表面S1340U。第二重分佈線結構S1100可以包括第二重分佈線圖案S1130、第三介電層S1110和第四介電層S1120。第三介電層S1110和第四介電層S1120可以被設置為使第二重分佈線圖案S1130彼此電隔離和絕緣。Each second bridge die S1300 may be configured to include a second body S1310, a second via pad S1320, a second via hole S1330, and a second pillar bump S1340. The second molding layer S1400 may surround the side surface of the second bridge die S1300 and the side surface of the second semiconductor die S1200 to expose the top surface S1340U of the second stud bump S1340. The second redistribution line structure S1100 may include a second redistribution line pattern S1130, a third dielectric layer S1110, and a fourth dielectric layer S1120. The third dielectric layer S1110 and the fourth dielectric layer S1120 may be provided to electrically isolate and insulate the second redistribution line patterns S1130 from each other.

第二重分佈線結構S1100可以用作將第二半導體晶粒S1200電連接到第一半導體晶粒(圖10的1200)、第一橋接晶粒(圖10的1300)或外部裝置的互連結構。垂直連接器S1500可以電連接到第二重分佈線結構S1100的第二重分佈線圖案S1130。垂直連接器S1500可用作將上部元件連接到位於上部元件下方的下部元件的連接構件。垂直連接器S1500可以是焊料球或導電凸塊。The second redistribution line structure S1100 can be used as an interconnection structure for electrically connecting the second semiconductor die S1200 to the first semiconductor die (1200 in FIG. 10), the first bridge die (1300 in FIG. 10), or an external device . The vertical connector S1500 may be electrically connected to the second redistribution line pattern S1130 of the second redistribution line structure S1100. The vertical connector S1500 can be used as a connecting member that connects the upper element to the lower element located below the upper element. The vertical connector S1500 may be solder balls or conductive bumps.

圖14是例示根據實施方式的半導體封裝件1030的截面圖。圖15是被包括在圖14的半導體封裝件1030中的第一橋接晶粒1300和第二橋接晶粒S1300的放大圖。FIG. 14 is a cross-sectional view illustrating a semiconductor package 1030 according to an embodiment. FIG. 15 is an enlarged view of the first bridge die 1300 and the second bridge die S1300 included in the semiconductor package 1030 of FIG. 14.

參照圖14,半導體封裝件1030可以被配置為包括依次堆疊的第一子封裝件1010和第二子封裝件1020。第二子封裝件1020可以垂直堆疊在第一子封裝件1010上。第二子封裝件1020的底表面可以與第一子封裝件1010的頂表面直接接觸。第二子封裝件1020的底表面可以對應於第二重分佈線結構S1100的底表面S1121。第一子封裝件1010的頂表面可以對應於第一半導體晶粒1200的頂表面1202。因此,第二重分佈線結構S1100的底表面S1121可以與第一半導體晶粒1200的頂表面1202直接接觸。第一子封裝件1010的中間部分1010H的頂表面可以與第二子封裝件1020的對應於第二重分佈線結構S1100的底表面S1121的底表面直接接觸。14, the semiconductor package 1030 may be configured to include a first sub package 1010 and a second sub package 1020 that are sequentially stacked. The second sub-package 1020 may be vertically stacked on the first sub-package 1010. The bottom surface of the second sub-package 1020 may directly contact the top surface of the first sub-package 1010. The bottom surface of the second sub-package 1020 may correspond to the bottom surface S1121 of the second redistribution line structure S1100. The top surface of the first sub-package 1010 may correspond to the top surface 1202 of the first semiconductor die 1200. Therefore, the bottom surface S1121 of the second redistribution line structure S1100 may directly contact the top surface 1202 of the first semiconductor die 1200. The top surface of the middle portion 1010H of the first sub-package 1010 may directly contact the bottom surface of the second sub-package 1020 corresponding to the bottom surface S1121 of the second redistribution line structure S1100.

因為第二子封裝件1020的底表面與第一子封裝件1010的頂表面1202直接接觸,所以可以最小化第一子封裝件1010和第二子封裝件1020的總厚度(即,半導體封裝件1030的厚度T14)。也就是說,與其中第一子封裝件和第二子封裝件堆疊成彼此垂直間隔開的比較例相比,包括彼此垂直接觸的第一子封裝件1010和第二子封裝件1020的半導體封裝件1030的厚度T14可以減小。Because the bottom surface of the second sub package 1020 is in direct contact with the top surface 1202 of the first sub package 1010, the total thickness of the first sub package 1010 and the second sub package 1020 (ie, the semiconductor package 1030 thickness T14). That is, compared with the comparative example in which the first sub-package and the second sub-package are stacked to be vertically spaced apart from each other, the semiconductor package including the first sub-package 1010 and the second sub-package 1020 that are in vertical contact with each other The thickness T14 of the piece 1030 can be reduced.

參照圖14和圖15,在半導體封裝件1030中,第二子封裝件1020的凹入部分1020R可以對應於從第二半導體晶粒S1200橫向突出以與第一子封裝件1010的凹入邊緣部分1010R垂直重疊的部分。在下文中,第二子封裝件1020的凹入部分1020R可以被稱為第二子封裝件1020的突出部。第二子封裝件1020的突出部1020R可以突出為位於第一子封裝件1010的凹入邊緣部分1010R上方。第二子封裝件1020的突出部1020R可以包括第二重分佈線結構S1100的突出部。第二重分佈線結構S1100的突出部可以不突出為與第一半導體晶粒1200垂直重疊。14 and 15, in the semiconductor package 1030, the recessed portion 1020R of the second sub-package 1020 may correspond to laterally protruding from the second semiconductor die S1200 to be aligned with the recessed edge portion of the first sub-package 1010 1010R The part that overlaps vertically. Hereinafter, the concave portion 1020R of the second sub-package 1020 may be referred to as a protrusion of the second sub-package 1020. The protrusion 1020R of the second sub-package 1020 may protrude to be located above the concave edge portion 1010R of the first sub-package 1010. The protrusion 1020R of the second sub-package 1020 may include the protrusion of the second redistribution line structure S1100. The protrusion of the second redistribution line structure S1100 may not protrude to vertically overlap the first semiconductor die 1200.

第二子封裝件1020的突出部1020R可以與第一子封裝件1010的凹入邊緣部分1010R垂直地間隔開。第一子封裝件1010可以具有中間部分1010H和低於中間部分1010H的凹入邊緣部分1010R,從而提供台階結構。因此,與第一子封裝件1010接觸的對應於第二子封裝件1020的邊緣部分的突出部1020R可以從第二半導體晶粒S1200橫向突出以作為懸垂部。The protrusion 1020R of the second sub-package 1020 may be vertically spaced from the concave edge portion 1010R of the first sub-package 1010. The first sub-package 1010 may have a middle portion 1010H and a concave edge portion 1010R lower than the middle portion 1010H, thereby providing a stepped structure. Therefore, the protrusion 1020R corresponding to the edge portion of the second sub-package 1020 in contact with the first sub-package 1010 may laterally protrude from the second semiconductor die S1200 as an overhang.

垂直連接器S1500可以設置在第二子封裝件1020的突出部1020R和第一子封裝件1010的凹入邊緣部分1010R之間。垂直連接器S1500可以設置在第一子封裝件1010的凹入邊緣部分1010R上以支撐第二子封裝件1020的突出部1020R。The vertical connector S1500 may be disposed between the protrusion 1020R of the second sub-package 1020 and the concave edge portion 1010R of the first sub-package 1010. The vertical connector S1500 may be disposed on the concave edge portion 1010R of the first sub-package 1010 to support the protrusion 1020R of the second sub-package 1020.

垂直連接器S1500可以具有第三高度CH。第三高度CH可以對應於第一子封裝件1010的凹入邊緣部分1010R的頂表面的水平與第二重分佈線結構S1100的底表面S1121(即,第二子封裝件1020的底表面)的水平之間的距離。垂直連接器S1500的第三高度CH可以具有用於補償與第二子封裝件1020的突出部1020R與第一子封裝件1010的凹入邊緣部分1010R之間的距離相對應的水平差H13的適當值。因為垂直連接器S1500補償水平差H13,所以垂直連接器S1500的第三高度CH可以對應於第一橋接晶粒1300的第一高度H11與第一半導體晶粒1200的第二高度H12之差。The vertical connector S1500 may have a third height CH. The third height CH may correspond to the level of the top surface of the concave edge portion 1010R of the first sub-package 1010 and the bottom surface S1121 of the second redistribution line structure S1100 (ie, the bottom surface of the second sub-package 1020). The distance between levels. The third height CH of the vertical connector S1500 may have an appropriate level for compensating for the level difference H13 corresponding to the distance between the protrusion 1020R of the second sub-package 1020 and the concave edge portion 1010R of the first sub-package 1010. value. Because the vertical connector S1500 compensates for the level difference H13, the third height CH of the vertical connector S1500 may correspond to the difference between the first height H11 of the first bridge die 1300 and the second height H12 of the first semiconductor die 1200.

垂直連接器S1500可以將第一子封裝件1010的第一橋接晶粒1300的第一柱凸塊1340電連接到第二子封裝件1020的第二重分佈線結構S1100的第二重分佈線圖案S1130。結果,垂直連接器S1500可以提供將第一子封裝件1010電連接到第二子封裝件1020的垂直路徑。垂直連接器S1500可以將第一半導體晶粒1200和第二半導體晶粒S1200彼此電連接。垂直連接器S1500可以位於第一子封裝件1010的凹入邊緣部分1010R上。因此,第一半導體晶粒1200的側表面1203的上部1203U可以面對垂直連接器S1500的側表面S1503。The vertical connector S1500 may electrically connect the first pillar bump 1340 of the first bridge die 1300 of the first sub-package 1010 to the second redistribution line pattern of the second redistribution line structure S1100 of the second sub-package 1020 S1130. As a result, the vertical connector S1500 may provide a vertical path to electrically connect the first sub-package 1010 to the second sub-package 1020. The vertical connector S1500 may electrically connect the first semiconductor die 1200 and the second semiconductor die S1200 to each other. The vertical connector S1500 may be located on the concave edge portion 1010R of the first sub-package 1010. Therefore, the upper portion 1203U of the side surface 1203 of the first semiconductor die 1200 may face the side surface S1503 of the vertical connector S1500.

再次參照圖14和圖15,因為第一子封裝件1010包括中間部分1010H和比中間部分1010H低的凹入邊緣部分1010R以提供台階結構,所以凹入邊緣部分1010R上的垂直連接器S1500可以從第一子封裝件1010的頂表面1202的水平沿向下方向延伸。因此,第二子封裝件1020的底表面可以與第一子封裝件1010的頂表面1202接觸。在比較例中,如果對應於第一子封裝件1010的第一子封裝件具有平坦頂表面而沒有任何台階結構,則對應於垂直連接器S1500的垂直連接器可能被設置成從第一子封裝件的平坦頂表面突出。在這種情況下,對應於第二子封裝件1020的第二子封裝件可能以垂直連接器的高度而與第一子封裝件垂直地間隔開。因此,根據比較例的包括通過垂直連接器彼此垂直地間隔開的第一子封裝件和第二子封裝件的半導體封裝件可能具有大於圖14所示的半導體封裝件1030的厚度T14的厚度。也就是說,圖14所示的半導體封裝件1030的厚度T14可以小於根據比較例的半導體封裝件的厚度。因此,本實施方式可以提供薄而且緊湊的半導體封裝件。14 and 15 again, because the first sub-package 1010 includes a middle portion 1010H and a concave edge portion 1010R lower than the middle portion 1010H to provide a step structure, the vertical connector S1500 on the concave edge portion 1010R can be changed from The level of the top surface 1202 of the first sub-package 1010 extends in the downward direction. Therefore, the bottom surface of the second sub-package 1020 may be in contact with the top surface 1202 of the first sub-package 1010. In the comparative example, if the first sub-package corresponding to the first sub-package 1010 has a flat top surface without any stepped structure, the vertical connector corresponding to the vertical connector S1500 may be set from the first sub-package The flat top surface of the piece protrudes. In this case, the second sub-package corresponding to the second sub-package 1020 may be vertically spaced from the first sub-package by the height of the vertical connector. Therefore, the semiconductor package including the first subpackage and the second subpackage vertically spaced apart from each other by the vertical connector according to the comparative example may have a thickness greater than the thickness T14 of the semiconductor package 1030 shown in FIG. 14. That is, the thickness T14 of the semiconductor package 1030 shown in FIG. 14 may be smaller than the thickness of the semiconductor package according to the comparative example. Therefore, the present embodiment can provide a thin and compact semiconductor package.

圖16是例示根據實施方式的半導體封裝件1040的截面圖。FIG. 16 is a cross-sectional view illustrating a semiconductor package 1040 according to an embodiment.

參照圖16,半導體封裝件1040還可以包括有機材料層1600,其設置在第一子封裝件1010的頂表面1202和第二子封裝件1020的底表面(即,與半導體封裝件1030相比的,第二重分佈線結構S1100的底表面S1121)之間。有機材料層1600可以是膜狀層。有機材料層1600可以是將第二子封裝件1020附接到第一子封裝件1010的黏合劑層。充當黏合劑層的有機材料層1600可以將第二子封裝件1020固定到第一子封裝件1010,以防止或抑制第二子封裝件1020的任何不期望的位置變化。16, the semiconductor package 1040 may further include an organic material layer 1600 disposed on the top surface 1202 of the first sub package 1010 and the bottom surface of the second sub package 1020 (ie, compared with the semiconductor package 1030 , Between the bottom surface S1121) of the second redistribution line structure S1100. The organic material layer 1600 may be a film-like layer. The organic material layer 1600 may be an adhesive layer that attaches the second sub-package 1020 to the first sub-package 1010. The organic material layer 1600 serving as an adhesive layer may fix the second sub-package 1020 to the first sub-package 1010 to prevent or suppress any undesired positional change of the second sub-package 1020.

圖17是例示包括採用至少一個根據本公開的實施方式的半導體封裝件的記憶卡7800的電子系統的方塊圖。記憶卡7800可以包括諸如非揮發性記憶體裝置這樣的記憶體7810和記憶體控制器7820。記憶體7810和記憶體控制器7820可以存儲資料或者讀出已存儲的資料。記憶體7810和記憶體控制器7820中的至少一個可以包括至少一個根據本公開的實施方式的半導體封裝件。FIG. 17 is a block diagram illustrating an electronic system including a memory card 7800 employing at least one semiconductor package according to an embodiment of the present disclosure. The memory card 7800 may include a memory 7810 such as a non-volatile memory device and a memory controller 7820. The memory 7810 and the memory controller 7820 can store data or read out stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one semiconductor package according to an embodiment of the present disclosure.

記憶體7810可以包括根據本公開的實施方式製造的非揮發性存儲裝置。記憶體控制器7820可以控制記憶體7810,使得響應於來自主機7830的讀/寫請求而讀出已存儲的資料或者存儲資料。The memory 7810 may include a non-volatile storage device manufactured according to an embodiment of the present disclosure. The memory controller 7820 can control the memory 7810 so as to read out stored data or stored data in response to a read/write request from the host 7830.

圖18是例示包括根據本公開的實施方式的至少一個半導體封裝件的電子系統8710的方塊圖。電子系統8710可以包括控制器8711、輸入/輸出裝置8712和記憶體8713。控制器8711、輸入/輸出裝置8712和記憶體8713可以通過提供資料移動的路徑的匯流排8715彼此耦合。FIG. 18 is a block diagram illustrating an electronic system 8710 including at least one semiconductor package according to an embodiment of the present disclosure. The electronic system 8710 may include a controller 8711, an input/output device 8712, and a memory 8713. The controller 8711, the input/output device 8712, and the memory 8713 may be coupled to each other through a bus 8715 that provides a path for data movement.

在一實施方式中,控制器8711可以包括一個或更多個微處理器、數位信號處理器、微控制器和/或能夠執行與這些組件相同的功能的邏輯器件。控制器8711或記憶體8713可以包括根據本公開的實施方式的一個或更多個半導體封裝件。輸入/輸出裝置8712可以包括從小鍵盤、鍵盤、顯示裝置、觸摸面板等當中選擇的至少一個。記憶體8713是用於存儲資料的裝置。記憶體8713可以存儲將由控制器8711執行的資料和/或命令等。In an embodiment, the controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and/or logic devices capable of performing the same functions as these components. The controller 8711 or the memory 8713 may include one or more semiconductor packages according to embodiments of the present disclosure. The input/output device 8712 may include at least one selected from a keypad, a keyboard, a display device, a touch panel, and the like. The memory 8713 is a device for storing data. The memory 8713 can store data and/or commands to be executed by the controller 8711.

記憶體8713可以包括諸如DRAM這樣的揮發性存儲裝置和/或諸如快閃記憶體這樣的非揮發性存儲裝置。例如,可以將快閃記憶體安裝到諸如移動終端或桌上型電腦這樣的信息處理系統。快閃記憶體可以構成固態硬碟(SSD)。在這種情況下,電子系統8710可以將大量資料穩定地存儲在快閃記憶體系統中。The memory 8713 may include a volatile storage device such as DRAM and/or a non-volatile storage device such as flash memory. For example, the flash memory can be installed in an information processing system such as a mobile terminal or a desktop computer. Flash memory can form a solid state drive (SSD). In this case, the electronic system 8710 can stably store a large amount of data in the flash memory system.

電子系統8710還可以包括介面8714,介面8714被配置為向通信網絡發送資料和從通信網絡接收資料。介面8714可以是有線或無線類型。例如,介面8714可以包括天線或者有線或無線收發器。The electronic system 8710 may also include an interface 8714, which is configured to send data to and receive data from the communication network. The interface 8714 can be wired or wireless. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

電子系統8710可以被實現為移動系統、個人電腦、工業電腦或執行各種功能的邏輯系統。例如,移動系統可以是個人數位助理(PDA)、便攜式電腦、平板電腦、行動電話、智慧型手機、無線電話、膝上型電腦、記憶卡、數位音樂系統和信息發送/接收系統中的任一個。The electronic system 8710 can be implemented as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system can be any of a personal digital assistant (PDA), laptop, tablet, mobile phone, smart phone, wireless phone, laptop, memory card, digital music system, and information sending/receiving system .

如果電子系統8710是能夠執行無線通信的設備,則電子系統8710可以用於使用分碼多工存取(CDMA)、全球移動通信系統(GSM)、北美數位行動電話(NADC)、強化分時多工存取(E-TDMA)、寬頻分碼多工存取(WCDMA)、CDMA2000、長期演進技術(LTE)或無線寬頻網際網路(WiBro)的技術的通信系統。If the electronic system 8710 is a device capable of performing wireless communication, the electronic system 8710 can be used to use code division multiple access (CDMA), global system for mobile communications (GSM), North American digital mobile phone (NADC), and enhanced time sharing. E-TDMA, Wideband Code Division Multiple Access (WCDMA), CDMA2000, Long Term Evolution (LTE) or Wireless Broadband Internet (WiBro) technology communication systems.

已經出於例示目的公開了本公開的實施方式。本領域的技術人員將領會的是,能夠在不脫離本公開和所附的請求項的範圍和精神的情況下進行各種修改、添加和替換。The embodiments of the present disclosure have been disclosed for illustrative purposes. Those skilled in the art will appreciate that various modifications, additions and substitutions can be made without departing from the scope and spirit of the present disclosure and the appended claims.

CH:高度 D1:直徑 D2:直徑 D3:直徑 D11:直徑 D12:直徑 L:長度 H:水平差 H11:高度 H12:高度 H13:水平差 H14:高度 H15:高度 H16:水平差 S:距離 S1100:重分佈線結構 S1102:頂表面 S1110:介電層 S1120:介電層 S1121:底表面 S1130:重分佈線圖案 S1200:半導體晶粒 S1202:頂表面 S1300:橋接晶粒 S1310:主體 S1320:通孔 S1330:通孔 S1340:柱凸塊 S1340U:頂表面 S1400:模製層 S1500:垂直連接器 S1503:側表面 T1:厚度 T11:厚度 T12:厚度 T12-1:厚度 T14:厚度 T2:厚度 W1:寬度 W2:寬度 W3:總寬度 X-X’:截面圖的截取線 X1-X1’:截面圖的截取線 X2-X2’:截面圖的截取線 10:半導體封裝件 10-1:子封裝件 10-2:子封裝件 10-3:子封裝件 10-4:子封裝件 11:半導體封裝件 12:半導體封裝件 12-1:子封裝件 12-2:子封裝件 12-S:半導體封裝件 13:半導體封裝件 100:半導體晶粒 101:子封裝件 102:表面 103:側表面 110:接觸墊 121:連接墊 123:邊緣區域 200:橋接晶粒 200-2:橋接晶粒 201:表面 202:表面 203:側表面 204:側表面 210:通孔 212:通孔 213:通孔 215:虛設通孔 250:虛設晶粒 250-1:虛設晶粒 250-2:虛設晶粒 300:重分佈線 300-2:重分佈線 310:墊重疊部分 320:延伸線 330:延伸線 340:延伸線 370:通孔墊 370-2:通孔墊 370-5:虛設墊 371:通孔墊 372:通孔墊 373:通孔墊 375:通孔墊 377:通孔墊 390:介電層 400:柱凸塊 400-1:柱凸塊 400-5:柱凸塊 401:側表面 401-1:側表面 402:頂表面 402-1:頂表面 413:虛設柱凸塊 500:模製層 500-1:模製層 500-3:模製層 501:頂表面 600:連接器 600-2:連接器 600-5:虛設連接器 700:封裝基板 750:外部連接器 1010:子封裝件 1010H:中間部分 1010R:凹入邊緣部分 1020:子封裝件 1020H:中間部分 1020R:凹入部分 1030:半導體封裝件 1040:半導體封裝件 1100:重分佈線結構 1101:底表面 1102:頂表面 1100:重分佈線結構 1110:介電層 1120:介電層 1130:重分佈線圖案 1200:半導體晶粒 1200-1:半導體晶粒 1201:底表面 1202:頂表面 1203:側表面 1203U:上部 1210:連接墊 1300:橋接晶粒 1310:主體 1311:底表面 1312:頂表面 1315:芯部 1316:介電層 1320:通孔墊 1330:通孔 1340:柱凸塊 1340U:頂表面 1400:模製層 1500:外部連接器 1600:有機材料層 7800:記憶卡 7810:記憶體 7820:記憶體控制器 7830:主機 8710:電子系統 8711:介面 8712:輸入/輸出裝置 8713:記憶體 8714:介面 8715:匯流排CH: height D1: diameter D2: Diameter D3: Diameter D11: Diameter D12: Diameter L: length H: Level difference H11: height H12: height H13: Level difference H14: height H15: height H16: Level difference S: distance S1100: Redistribution line structure S1102: Top surface S1110: Dielectric layer S1120: Dielectric layer S1121: bottom surface S1130: Redistribution line pattern S1200: Semiconductor die S1202: Top surface S1300: Bridge Die S1310: main body S1320: Through hole S1330: Through hole S1340: Pillar bump S1340U: Top surface S1400: Molded layer S1500: vertical connector S1503: Side surface T1: thickness T11: thickness T12: Thickness T12-1: Thickness T14: Thickness T2: thickness W1: width W2: width W3: total width X-X’: Intersection line of the cross-sectional view X1-X1’: the cut line of the cross-sectional view X2-X2’: the cut line of the cross-sectional view 10: Semiconductor package 10-1: Sub-package 10-2: Sub-package 10-3: Sub-package 10-4: Sub-package 11: Semiconductor package 12: Semiconductor package 12-1: Sub-package 12-2: Sub-package 12-S: Semiconductor package 13: Semiconductor package 100: semiconductor die 101: Sub-package 102: Surface 103: side surface 110: contact pad 121: connection pad 123: edge area 200: Bridge Die 200-2: Bridge Die 201: Surface 202: Surface 203: side surface 204: side surface 210: Through hole 212: Through hole 213: Through hole 215: dummy via 250: dummy die 250-1: dummy die 250-2: dummy die 300: Redistribution line 300-2: Redistribution line 310: Pad overlapping part 320: extension line 330: Extension line 340: Extension line 370: Through Hole Pad 370-2: Through hole pad 370-5: dummy pad 371: Through Hole Pad 372: Through Hole Pad 373: Through Hole Pad 375: Through Hole Pad 377: Through Hole Pad 390: Dielectric layer 400: column bump 400-1: Pillar bump 400-5: Pillar bump 401: side surface 401-1: side surface 402: top surface 402-1: top surface 413: Dummy column bump 500: Molded layer 500-1: Molded layer 500-3: Molded layer 501: top surface 600: Connector 600-2: Connector 600-5: Dummy connector 700: Package substrate 750: External connector 1010: Sub-package 1010H: middle part 1010R: recessed edge part 1020: Sub-package 1020H: middle part 1020R: Recessed part 1030: Semiconductor package 1040: Semiconductor package 1100: Redistribution line structure 1101: bottom surface 1102: top surface 1100: Redistribution line structure 1110: Dielectric layer 1120: Dielectric layer 1130: Redistribution line pattern 1200: semiconductor die 1200-1: semiconductor die 1201: bottom surface 1202: top surface 1203: side surface 1203U: upper part 1210: connection pad 1300: Bridge Die 1310: main body 1311: bottom surface 1312: top surface 1315: core 1316: Dielectric layer 1320: Through hole pad 1330: Through hole 1340: column bump 1340U: Top surface 1400: Molded layer 1500: External connector 1600: organic material layer 7800: Memory card 7810: memory 7820: Memory Controller 7830: host 8710: electronic system 8711: Interface 8712: input/output device 8713: memory 8714: Interface 8715: bus

圖1、圖2和圖3是例示根據實施方式的半導體封裝件的截面圖。1, 2, and 3 are cross-sectional views illustrating semiconductor packages according to embodiments.

圖4和圖5是例示根據實施方式的半導體封裝件的平面圖。4 and 5 are plan views illustrating a semiconductor package according to an embodiment.

圖6是例示根據實施方式的半導體封裝件的截面圖。FIG. 6 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

圖7是例示根據實施方式的半導體封裝件的截面圖。FIG. 7 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

圖8是例示根據實施方式的半導體封裝件的截面圖。FIG. 8 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

圖9是例示根據實施方式的半導體封裝件的截面圖。FIG. 9 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

圖10是例示根據實施方式的半導體封裝件的子封裝件的截面圖。FIG. 10 is a cross-sectional view illustrating a sub-package of the semiconductor package according to the embodiment.

圖11是例示根據實施方式的半導體封裝件的子封裝件的平面圖。FIG. 11 is a plan view illustrating a sub-package of the semiconductor package according to the embodiment.

圖12是例示根據實施方式的半導體封裝件的橋接晶粒的截面圖。FIG. 12 is a cross-sectional view illustrating a bridge die of a semiconductor package according to an embodiment.

圖13是例示根據實施方式的半導體封裝件的子封裝件的截面圖。FIG. 13 is a cross-sectional view illustrating a sub-package of the semiconductor package according to the embodiment.

圖14是例示根據實施方式的半導體封裝件的截面圖。FIG. 14 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

圖15是被包括在圖14的半導體封裝件中的橋接晶粒的放大圖。FIG. 15 is an enlarged view of the bridge die included in the semiconductor package of FIG. 14.

圖16是例示根據實施方式的半導體封裝件的截面圖。FIG. 16 is a cross-sectional view illustrating a semiconductor package according to an embodiment.

圖17是例示採用包括至少一個根據各個實施方式的半導體封裝件的記憶卡的電子系統的方塊圖。FIG. 17 is a block diagram illustrating an electronic system employing a memory card including at least one semiconductor package according to various embodiments.

圖18是例示包括至少一個根據各個實施方式的半導體封裝件的另一電子系統的方塊圖。FIG. 18 is a block diagram illustrating another electronic system including at least one semiconductor package according to various embodiments.

CH:高度 CH: height

H12:高度 H12: height

T14:厚度 T14: Thickness

S1100:重分佈線結構 S1100: Redistribution line structure

S1121:底表面 S1121: bottom surface

S1130:重分佈線圖案 S1130: Redistribution line pattern

S1200:半導體晶粒 S1200: Semiconductor die

S1300:橋接晶粒 S1300: Bridge Die

S1500:垂直連接器 S1500: vertical connector

S1503:側表面 S1503: Side surface

1010:子封裝件 1010: Sub-package

1010H:中間部分 1010H: middle part

1010R:凹入邊緣部分 1010R: recessed edge part

1020:子封裝件 1020: Sub-package

1020R:凹入部分 1020R: Recessed part

1030:半導體封裝件 1030: Semiconductor package

1100:重分佈線結構 1100: Redistribution line structure

1200:半導體晶粒 1200: semiconductor die

1202:頂表面 1202: top surface

1203:側表面 1203: side surface

1203U:上部 1203U: upper part

1300:橋接晶粒 1300: Bridge Die

1340:柱凸塊 1340: column bump

Claims (20)

一種半導體封裝件,所述半導體封裝件包括:  第一半導體晶粒,所述第一半導體晶粒設置在第一重分佈線結構上; 第一橋接晶粒,所述第一橋接晶粒設置在所述第一重分佈線結構上以提供所述第一半導體晶粒和所述第一橋接晶粒之間的水平差,所述第一橋接晶粒的高度小於所述第一半導體晶粒的高度; 第二重分佈線結構,所述第二重分佈線結構堆疊在所述第一半導體晶粒上,使得所述第二重分佈線結構的底表面與所述第一半導體晶粒的頂表面接觸,其中,所述第二重分佈線結構被設置成具有突出部,當從平面圖觀察時,所述突出部從所述第一半導體晶粒的側表面橫向突出; 第二半導體晶粒,所述第二半導體晶粒設置在所述第二重分佈線結構上;以及 垂直連接器,所述垂直連接器設置在所述第一橋接晶粒與所述第二重分佈線結構的所述突出部之間以支撐所述突出部, 其中,所述第一橋接晶粒包括第一通孔。A semiconductor package comprising: a first semiconductor die, the first semiconductor die being arranged on a first redistribution line structure; A first bridge die, the first bridge die is disposed on the first redistribution line structure to provide a level difference between the first semiconductor die and the first bridge die, the first The height of a bridge die is smaller than the height of the first semiconductor die; A second redistribution line structure, the second redistribution line structure being stacked on the first semiconductor die, such that the bottom surface of the second redistribution line structure is in contact with the top surface of the first semiconductor die , Wherein the second redistribution line structure is configured to have a protrusion, and when viewed from a plan view, the protrusion laterally protrudes from the side surface of the first semiconductor die; A second semiconductor die, the second semiconductor die being disposed on the second redistribution line structure; and A vertical connector provided between the first bridging die and the protrusion of the second redistribution line structure to support the protrusion, Wherein, the first bridge die includes a first through hole. 根據請求項1所述的半導體封裝件,其中,所述第一橋接晶粒包括: 第一主體,所述第一通孔垂直穿過所述第一主體;以及 第一柱凸塊,所述第一柱凸塊設置在所述第一主體上以從所述第一主體向上突出,並且所述第一柱凸塊電連接到所述第一通孔; 其中,所述垂直連接器將所述第一柱凸塊電連接到所述第二重分佈線結構的所述突出部。The semiconductor package according to claim 1, wherein the first bridge die includes: A first body, the first through hole vertically passing through the first body; A first stud bump, the first stud bump is disposed on the first body to protrude upward from the first body, and the first stud bump is electrically connected to the first through hole; Wherein, the vertical connector electrically connects the first pillar bump to the protrusion of the second redistribution line structure. 根據請求項2所述的半導體封裝件,其中,由於從所述第一重分佈線結構到所述第一柱凸塊的頂表面的水平的第一高度小於從所述第一重分佈線結構到所述第一半導體晶粒的所述頂表面的水平的第二高度,所以存在所述水平差。The semiconductor package according to claim 2, wherein the first height from the first redistribution line structure to the top surface of the first pillar bump is smaller than that from the first redistribution line structure The second height to the level of the top surface of the first semiconductor die, so there is the level difference. 根據請求項3所述的半導體封裝件,其中,所述垂直連接器具有與所述第一高度和所述第二高度之差相對應的第三高度。The semiconductor package according to claim 3, wherein the vertical connector has a third height corresponding to a difference between the first height and the second height. 根據請求項4所述的半導體封裝件,其中,所述垂直連接器包括焊料球。The semiconductor package according to claim 4, wherein the vertical connector includes a solder ball. 根據請求項2所述的半導體封裝件,所述半導體封裝件還包括圍繞所述第一橋接晶粒和所述第一半導體晶粒的第一模製層, 其中,所述第一模製層圍繞所述第一柱凸塊並且覆蓋所述第一橋接晶粒的所述第一主體。The semiconductor package according to claim 2, further comprising a first molding layer surrounding the first bridge die and the first semiconductor die, Wherein, the first molding layer surrounds the first pillar bumps and covers the first body of the first bridge die. 根據請求項6所述的半導體封裝件,其中,所述第一模製層被設置成露出所述第一半導體晶粒的側表面的上部和所述第一半導體晶粒的所述頂表面。The semiconductor package according to claim 6, wherein the first mold layer is provided to expose an upper portion of a side surface of the first semiconductor die and the top surface of the first semiconductor die. 根據請求項2所述的半導體封裝件,其中,所述第一柱凸塊具有大於所述第一通孔的第一直徑的第二直徑。The semiconductor package according to claim 2, wherein the first stud bump has a second diameter larger than the first diameter of the first through hole. 根據請求項1所述的半導體封裝件,其中,所述第一重分佈線結構包括: 重分佈線圖案,所述重分佈線圖案將所述第一半導體晶粒電連接到所述第一通孔;以及 介電層,所述介電層隔離所述重分佈線圖案。The semiconductor package according to claim 1, wherein the first redistribution line structure includes: A redistribution line pattern that electrically connects the first semiconductor die to the first through hole; and The dielectric layer isolates the redistribution line pattern. 根據請求項1所述的半導體封裝件,其中,所述垂直連接器被設置為使得所述第一半導體晶粒的側表面面向所述垂直連接器的側表面。The semiconductor package according to claim 1, wherein the vertical connector is arranged such that the side surface of the first semiconductor die faces the side surface of the vertical connector. 根據請求項1所述的半導體封裝件,所述半導體封裝件還包括有機材料層,所述有機材料層設置在所述第一半導體晶粒的所述頂表面與所述第二重分佈線結構的所述底表面之間。The semiconductor package according to claim 1, further comprising an organic material layer provided on the top surface of the first semiconductor die and the second redistribution line structure Between the bottom surface. 根據請求項1所述的半導體封裝件,所述半導體封裝件還包括: 第二橋接晶粒,所述第二橋接晶粒設置在所述第二重分佈線結構上,提供與所述第二半導體晶粒之間的水平差,並且所述第二橋接晶粒的高度小於所述第二半導體晶粒的高度,其中,所述第二橋接晶粒包括第二通孔和第二柱凸塊;以及 第二模製層,所述第二模製層圍繞所述第二橋接晶粒和所述第二半導體晶粒以露出所述第二柱凸塊的頂表面。The semiconductor package according to claim 1, wherein the semiconductor package further includes: Second bridge dies, the second bridge dies are arranged on the second redistribution line structure to provide a level difference with the second semiconductor dies, and the height of the second bridge dies Less than the height of the second semiconductor die, wherein the second bridge die includes a second through hole and a second pillar bump; and The second molding layer surrounds the second bridge die and the second semiconductor die to expose the top surface of the second stud bump. 一種半導體封裝件,所述半導體封裝件包括: 第一子封裝件,所述第一子封裝件包括中間部分和凹入邊緣部分,所述凹入邊緣部分的頂表面低於所述中間部分的頂表面; 第二子封裝件,所述第二子封裝件堆疊在所述第一子封裝件上以使得所述第二子封裝件的底表面與所述第一子封裝件的所述中間部分的頂表面接觸,其中,所述第二子封裝件具有與所述第一子封裝件的所述凹入邊緣部分垂直間隔開的突出部;以及 垂直連接器,所述垂直連接器設置在所述凹入邊緣部分上以支撐所述第二子封裝件的所述突出部, 其中,所述第一子封裝件包括: 第一重分佈線結構; 第一半導體晶粒,所述第一半導體晶粒設置在所述第一重分佈線結構上; 第一橋接晶粒,所述第一橋接晶粒設置在所述第一重分佈線結構上以提供所述第一半導體晶粒和所述第一橋接晶粒之間的水平差,所述第一橋接晶粒的高度小於所述第一半導體晶粒的高度,其中,所述第一橋接晶粒包括第一通孔和第一柱凸塊;以及 第一模製層,所述第一模製層圍繞所述第一橋接晶粒和所述第一半導體晶粒以露出所述第一柱凸塊的頂表面,並且 其中,所述垂直連接器連接到所述第一柱凸塊。A semiconductor package, the semiconductor package includes: A first sub-package, the first sub-package includes a middle portion and a concave edge portion, the top surface of the concave edge portion is lower than the top surface of the middle portion; A second sub-package, the second sub-package being stacked on the first sub-package such that the bottom surface of the second sub-package is aligned with the top of the middle portion of the first sub-package Surface contact, wherein the second sub-package has a protrusion vertically spaced from the concave edge portion of the first sub-package; and A vertical connector provided on the recessed edge portion to support the protrusion of the second sub-package, Wherein, the first sub-package includes: The first redistribution line structure; A first semiconductor die, the first semiconductor die being disposed on the first redistribution line structure; A first bridge die, the first bridge die is disposed on the first redistribution line structure to provide a level difference between the first semiconductor die and the first bridge die, the first The height of a bridge die is smaller than the height of the first semiconductor die, wherein the first bridge die includes a first through hole and a first pillar bump; and A first molding layer that surrounds the first bridge die and the first semiconductor die to expose the top surface of the first stud bump, and Wherein, the vertical connector is connected to the first pillar bump. 根據請求項13所述的半導體封裝件,其中,由於從所述第一重分佈線結構到所述第一柱凸塊的頂表面的水平的第一高度小於從所述第一重分佈線結構到所述第一半導體晶粒的所述頂表面的水平的第二高度,所以存在所述水平差。The semiconductor package according to claim 13, wherein the first height from the first redistribution line structure to the top surface of the first pillar bump is smaller than that from the first redistribution line structure The second height to the level of the top surface of the first semiconductor die, so there is the level difference. 根據請求項14所述的半導體封裝件,其中,所述垂直連接器具有與所述第一高度和所述第二高度之差相對應的第三高度。The semiconductor package according to claim 14, wherein the vertical connector has a third height corresponding to a difference between the first height and the second height. 根據請求項13所述的半導體封裝件,其中,所述第一重分佈線結構包括: 重分佈線圖案,所述重分佈線圖案將所述第一半導體晶粒電連接到所述第一通孔;以及 介電層,所述介電層隔離所述重分佈線圖案。The semiconductor package according to claim 13, wherein the first redistribution line structure includes: A redistribution line pattern that electrically connects the first semiconductor die to the first through hole; and The dielectric layer isolates the redistribution line pattern. 根據請求項13所述的半導體封裝件,其中,所述垂直連接器設置成使所述第一半導體晶粒的側表面面向所述垂直連接器的側表面。The semiconductor package according to claim 13, wherein the vertical connector is provided such that the side surface of the first semiconductor die faces the side surface of the vertical connector. 根據請求項13所述的半導體封裝件,所述半導體封裝件還包括有機材料層,所述有機材料層設置在所述第一子封裝件的所述頂表面與所述第二子封裝件的所述底表面之間。The semiconductor package according to claim 13, wherein the semiconductor package further includes an organic material layer disposed on the top surface of the first sub-package and the second sub-package. Between the bottom surface. 根據請求項13所述的半導體封裝件,其中,所述第二子封裝件包括: 第二重分佈線結構; 第二半導體晶粒,所述第二半導體晶粒設置在所述第二重分佈線結構上; 第二橋接晶粒,所述第二橋接晶粒設置在所述第二重分佈線結構上,提供與所述第二半導體晶粒之間的水平差,並且所述第二橋接晶粒的高度小於所述第二半導體晶粒的高度,其中,所述第二橋接晶粒包括第二通孔和第二柱凸塊;以及 第二模製層,所述第二模製層圍繞所述第二橋接晶粒和所述第二半導體晶粒以露出所述第二柱凸塊的頂表面。The semiconductor package according to claim 13, wherein the second sub-package includes: The second redistribution line structure; A second semiconductor die, the second semiconductor die is disposed on the second redistribution line structure; Second bridge dies, the second bridge dies are arranged on the second redistribution line structure to provide a level difference with the second semiconductor dies, and the height of the second bridge dies Less than the height of the second semiconductor die, wherein the second bridge die includes a second through hole and a second pillar bump; and The second molding layer surrounds the second bridge die and the second semiconductor die to expose the top surface of the second stud bump. 根據請求項13所述的半導體封裝件,其中,所述第二子封裝件與所述第一子封裝件具有基本相同的結構。The semiconductor package according to claim 13, wherein the second sub package and the first sub package have substantially the same structure.
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