CN112151614A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN112151614A
CN112151614A CN202010572172.1A CN202010572172A CN112151614A CN 112151614 A CN112151614 A CN 112151614A CN 202010572172 A CN202010572172 A CN 202010572172A CN 112151614 A CN112151614 A CN 112151614A
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嘉屋旨哲
永久克己
下村彰宏
柳川洋
森和久
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Renesas Electronics Corp
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Abstract

本申请涉及半导体器件。为了减小导通电阻同时抑制具有超级结结构的垂直MOSFET的特性变化的增加，垂直MOSFET包括具有n型漂移区的半导体衬底、在n型漂移区的表面上形成的p型基极区、以预定间隔布置在p型基极区下部的n型漂移区中的多个p型列区、底表面到达比p型基极区更深的位置并且布置在相邻p型列区之间的多个沟槽、在多个沟槽中形成的多个栅极电极、和在栅极电极的侧面上的p型基极区中形成的n型源极区。

Description

半导体器件
相关申请的交叉引用
于2019年6月28日提交的日本专利申请号2019-120692的公开内容，包括说明书、附图和摘要，其整体通过引用并入本文。
技术领域
本发明涉及一种半导体器件，包括具有沟槽栅极的垂直MOSFET(垂直型金属氧化物场效应晶体管)，具体涉及一种用于半导体器件的有效技术，该半导体器件包括所谓的超级结结构(下文中，称为SJ结构)，该超级结结构具有p型列区，p型列区被形成为使得从p型基极区的底部向n型漂移区突出。
背景技术
具有SJ结构的半导体器件包括例如：包括n型漂移区的半导体衬底、在n型漂移区的表面上形成的p型基极区、耦合到p型基极区并且以预定间隔布置在n型漂移区中的多个p型列区、布置在相邻的p型列区之间并且在到达p型基极区的底表面的沟槽中形成的栅极电极、和在栅极电极的侧面上的p型基极区中形成的n型源极区。
在日本未审查专利申请公开号2017-168501(专利文献1)中描述了具有这种SJ结构的半导体器件的示例。在同一文献中，公开了一种垂直MOSFET，该MOSFET具有形成为条形的多个p型列区，和在平面图中沿p型列区布置在相邻的p型列区之间的条形栅极电极。
发明内容
本申请的发明人在试图进一步减小包括SJ结构的垂直MOSFET的导通电阻时发现以下问题。
当进一步减小专利文献1中所述的具有所谓的SJ结构的垂直MOSFET的导通电阻时，周期性p型列区的间距的减小和n型漂移区或p型列区的浓度的增大是有效的。然而，垂直MOSFET的击穿电压和标准导通电阻随p型列区和n型漂移区的尺寸变化的灵敏度增加，因此存在垂直MOSFET的特性变化增大的问题。
其他问题和新颖特征从说明书和附图的描述中将变得明显。
根据本公开的实施例的半导体器件包括：包括n型漂移区的半导体衬底、在n型漂移区的表面上形成的p型基极区、以预定间隔布置在基极区下部处的n型漂移区中的多个p型列区、底表面到达比p型基极区更深的位置并且布置在相邻p型列区之间的多个沟槽、在多个沟槽中通过栅极绝缘膜形成的多个栅极电极、和在栅极电极的侧面上的p型基极区中形成的n型源极区。
通过根据实施例的半导体器件，在抑制包括SJ结构的垂直MOSFET的特性变化增大的同时，可以减小导通电阻。
附图说明
图1是根据实施例的具有垂直MOSFET结构的半导体器件的平面图。
图2是由图1中的虚线所示的单元区域的放大平面图。
图3是图2中的单位单元UC的主要部分的截面图。
图4是示出了根据实施例的具有垂直MOSFET结构的半导体器件的比较示例的单元区域的放大平面图。
图5是图4中的单位单元UC的主要部分的截面图。
图6是示出了根据实施例和比较示例的垂直MOSFET的击穿电压BVdss和标准导通电阻Rsp之间的关系的图。
图7是示出了根据实施例的具有垂直MOSFET结构的半导体器件的第一修改示例的单元区域的放大平面图。
图8是图7中的单位单元UC的主要部分的截面图。
图9是示出了根据实施例的具有垂直MOSFET结构的半导体器件的第二修改示例的单元区域的放大平面图。
图10是图9中的单位单元UC的主要部分的截面图。
图11是示出了根据实施例的具有垂直MOSFET结构的半导体器件的第三修改示例的单元区域的放大平面图。
图12是图11中的单位单元UC的主要部分的截面图。
图13是示出了根据实施例的具有垂直MOSFET结构的半导体器件的制造工艺的主要部分的截面图。
图14是示出了图13之后的具有垂直MOSFET结构的半导体器件的制造工艺的主要部分的截面图。
图15是示出了图14之后的具有垂直MOSFET结构的半导体器件的制造工艺的主要部分的截面图。
图16是示出了图15之后的具有垂直MOSFET结构的半导体器件的制造工艺的主要部分的截面图。
图17是示出了图16之后的具有垂直MOSFET结构的半导体器件的制造工艺的主要部分的截面图。
图18是示出了图17之后的具有垂直MOSFET结构的半导体器件的制造工艺的主要部分的截面图。
图19是示出了图18之后的具有垂直MOSFET结构的半导体器件的制造工艺的主要部分的截面图。
图20是示出了图19之后的具有垂直MOSFET结构的半导体器件的制造工艺的主要部分的截面图。
图21是示出了图20之后的具有垂直MOSFET结构的半导体器件的制造工艺的主要部分的截面图。
图22是示出了图21之后的具有垂直MOSFET结构的半导体器件的制造工艺的主要部分的截面图。
图23是示出了根据实施例的具有垂直MOSFET结构的半导体器件的第四修改示例的单元区域的放大平面图。
图24是示出了根据实施例的具有垂直MOSFET结构的半导体器件的第五修改示例的单元区域的放大平面图。
图25是示出了根据实施例的具有垂直MOSFET结构的半导体器件的第六修改示例的单元区域的放大平面图。
图26是示出了根据实施例的具有垂直MOSFET结构的半导体器件的第七修改示例的单元区域的放大平面图。
图27是示出了根据实施例的具有垂直MOSFET结构的半导体器件的第八修改示例的单元区域的放大平面图。
具体实施方式
参考附图，将详细描述根据实施例的半导体器件。在说明书和附图中，相同或对应的结构元件用相同的参考标号表示，并且省略其重复描述。此外，至少一部分实施例和每个修改彼此可以任意地组合。此外，在每个截面图中，指示空间不是空腔的斜线可以被省略，以使附图更容易看懂。如果指示空腔，则应在说明书中单独指明其为空腔。
符号“-”和“+”表示n或p型杂质的相对密度，例如，在n型杂质的情况下，杂质密度的高低按最低的“n--”、“n-”、“n”、“n+”和最高的“n++”的顺序。
(第一实施例)将参考图1至图3来描述根据本实施例的半导体设备。如图1所示，具有垂直MOSFET的半导体器件在半导体衬底100的主表面上具有栅极焊盘101和源极焊盘102。参考标号103示意性地示出了位于源极焊盘102下侧的垂直MOSFET的单元区域。
图2是由图1中的虚线所示的单元区域103中的放大平面图，沿Y方向的多个p型列区104和多个沟槽栅极(即，栅极电极)105并联布置。在本实施例中，p型列区104的间隔Pcol和沟槽栅极105的间隔Ptr分别以一定间隔设置，并且作为优选值，间隔Pcol是间隔Ptr的两倍。此外，假设沟槽栅极105在X方向上的宽度为Wtr，单位单元UC被设计为使得当沿连接相邻p型列区104的线路时，始终存在与沟槽栅极105的两倍以上宽度Wtr的重叠。
如图3所示，p型基极区106和p+型基极接触区107在距离Ptr处，沿X方向彼此平行地在相邻沟槽栅极105之间重复形成。
图3是图2的A-A截面图。垂直型MOSFET的每个单位单元UC包括：由半导体衬底100中的n型外延层形成的n型漂移区108、在n型漂移区108的底部处由高杂质浓度的n+型半导体层形成的n+型漏极区109，和电耦合到n+型漏极区109的底部的漏极电极110。
在p型基极区106中，形成了由高杂质浓度的n+型半导体层形成的n+型源极区111。在作为半导体衬底100的厚度方向的Z方向上，n+源极区111形成得比p型基极区106浅，并且p型列区104形成得比p型基极区106深。在相邻的p型列区104之间，形成沟槽栅极105以填充通过蚀刻n-漂移区108的表面而形成的两个沟槽。栅极绝缘膜112在n-漂移区108和沟槽栅极105之间的界面处形成。绝缘膜113在n型漂移区108的上表面上形成以覆盖沟槽栅极105和n+型源极区111，并且源极电极114在绝缘膜113的上表面上形成。
源极电极114通过在绝缘膜113中形成的条形接触孔CH1而形成在比n+型源极区111深且比p型基极区106浅的相邻沟槽栅极105之间，并且耦合到p+型基极接触区107。此外，源极电极114通过在绝缘膜113中形成的条形接触孔CH2而耦合到在p型列区104上形成的p+型基极接触区107。
为了比较上述根据第一实施例的垂直MOSFET的配置，图4和图5示出了与图2和图3中所示的垂直MOSFET的比较示例。顺便提及，图5是图4中的B-B截面图。图4和图5中所示的垂直MOSFET被配置为将p型列区104始终布置在相邻的沟槽栅极105之间。即，在相邻的p型列区104之间，在该配置中在平面图中仅布置了一个条形沟槽栅极105。
另一方面，根据第一实施例的垂直MOSFET与图4和图5的比较示例相比，可以通过减小平面图中每单位单元UC的p型列区104的占用率来确保更宽的电流路径。此外，即使当减小沟槽栅极105的重复间隔Ptr以提高栅极密度时，由于p型列区和漂移区(也称为n型列区)的重复间隔Pcol可以确保两倍于间隔Ptr的距离，因此也可以减小导通电阻，而不需要p型列区和漂移区的过高的杂质浓度。
图6示出了当p型列区和n型列区的电荷量相等时，电荷不平衡率(p型列区和n型列区的电荷量的平衡)与击穿电压BVdss和标准导通电阻Rsp之间的关系，从而获得垂直MOSFET的最大击穿电压。
在图4和图5中所示的比较示例的垂直MOSFET中，需要减小Pcol/Ptr，并且p型列区和n型列区需要高度集中，以减小标准导通电阻Rsp，同时保持电荷不平衡裕度满足一定的击穿电压或在该击穿电压以上。因此，出现了击穿电压和标准导通电阻Rsp对电荷不平衡率的灵敏度变高的问题。
另一方面，第一实施例的垂直MOSFET结构可以在不增加击穿电压BVdss和标准导通电阻Rsp对电荷不平衡率的灵敏度的情况下显著减小标准导通电阻Rsp。因此，垂直MOSFET结构不仅可以提高基本性能，而且能够更好地抵抗制造差异，从而提高产品的产量。
(第一修改示例)图7和图8中示出了第一实施例的第一修改示例。与第一实施例相比，第一修改示例的改变之处在于，沟槽栅极105的重复间隔具有两种类型的间隔Ptr1和Ptr2，并且如果p型列区104和沟槽栅极105的重复间隔是Pcol，那么间隔Pcol具有间隔Ptr1和间隔Ptr2的加和关系。顺便提及，图8是图中的C-C截面图。
由于第一修改示例的半导体器件具有这种关系，因此单位单元的设计灵活性高于第一实施例中的设计灵活性，并且可以增加p型列区104和沟槽栅极105之间的距离，使得p型列区104对沟道电阻的影响可以被抑制。此外，由于p型列区和n型列区(即，n型漂移区108)的PN结与沟槽栅极105之间的距离可以增加，因此通过在PN结和沟槽栅极105各自的下部增加的电场幅度的耦合可以缓解，使得击穿电压得到改善。
(第二修改示例)图9和图10中示出了第一实施例的第二修改示例。与第一实施例相比，第二修改示例的改变之处在于，在平面图中用蜂窝结构形成具有最小沟槽宽度Wtr的沟槽栅极105以提高栅极密度，并且在平面图中交错布置p型列区104。沟槽栅极105与p型列区104之间的关系即使在该配置中，当假设沿连接相邻p型列区104的线路时，单位单元UC也被设计为使得始终存在与沟槽栅极105的两倍以上宽度Wtr的重叠。顺便说，图10是图9中的D-D截面图。
在图10中，形成了在相邻的p型列区之间的X方向上具有宽度W并且在Y方向上具有宽度Wtr的沟槽栅极105，沟槽栅极105被设计为使得宽度W是宽度Wtr的两倍以上。
与第一实施例相比，第二修改示例的结构具有沟槽栅极105在单位单元UC中的更高的密度。因此，由于沟道密度可以提高，因此可以减小垂直MOSFET的导通电阻。此外，即使设计成使得沟槽栅极密度高，由于在平面图中单位单元的p型列区的占用率可以减小，因此可以确保宽的电流路径。因此，可以在无需过度增加p型列区和n型漂移区的杂质浓度的情况下减小导通电阻。
(第三修改示例)图11和图12中示出了第一实施例的第三修改示例。与第一实施例相比，第三修改示例的改变之处在于，在平面图中以栅格结构形成具有最小沟槽宽度Wtr的沟槽栅极105以提高栅极密度，并且在平面图中交错布置p型列区104。沟槽栅极105与p型列区104之间的关系即使在该配置中，当假设沿连接相邻p型列区104的线路时，单位单元UC也被设计成使得始终存在与沟槽栅极105的两倍以上宽度Wtr的重叠。图12是图11中的E-E截面图。
在图12中，形成了在相邻的p型列区之间的X方向上具有宽度W并且在Y方向上具有宽度Wtr的沟槽栅极105，沟槽栅极105被设计成使得宽度W是宽度Wtr的两倍以上。
在第三修改示例的配置中，单位单元UC中的沟槽栅极105的密度高于第一实施例的密度。因此，由于沟槽密度可以提高，可以减小垂直MOSFET的导通电阻。此外，即使设计成使得沟槽栅极密度高，由于在平面图中单位单元的p型列区的占用率可以减小，因此可以确保宽的电流路径。因此，可以在无需过度增加p型列区和n型漂移区的杂质浓度的情况下减小导通电阻。
下面，将描述根据本发明实施例的包括垂直MOSFET的半导体器件的制造方法。
如图13所示，例如，制备具有外延层EP的半导体衬底100，该外延层形成在包括n型高浓度半导体层的晶面(100)的硅衬底SB上。
接着，如图14所示，在外延层EP的上表面上形成由光致抗蚀剂膜11和绝缘膜10形成的硬掩模HM1。
接着，如图15所示，蚀刻从硬掩模HM1中暴露的外延层EP的上表面，以形成用于沟槽栅极的沟槽12。
接着，在移除硬掩模HM1之后，如图16所示，在沟槽12被填充有绝缘膜13之后，在外延层EP的上表面上依次形成绝缘膜14、绝缘膜15和绝缘膜16。例如，作为绝缘膜14和绝缘膜16，使用由CVD方法形成的氧化硅膜。作为绝缘膜15，使用由CVD方法形成的氮化硅膜。
接着，如图17所示，通过传统的光刻和蚀刻技术形成由光致抗蚀剂膜17和绝缘膜16形成的硬掩模HM2。接着，将硬掩模HM2用作引入杂质的掩模，例如，将诸如硼的p型杂质离子注入到外延层EP中以形成p型列区104。
接着，在移除硬掩模HM2、绝缘膜15和绝缘膜14之后，如图18所示，例如通过热氧化工艺，在包括沟槽12的表面的外延层EP的表面上形成栅极绝缘膜112。
接着，如图19所示，形成沟槽栅极105以嵌入沟槽12。沟槽栅极105例如由掺杂有n型杂质的多晶硅膜形成，并且通过在半导体衬底100的整个表面上沉积多晶硅膜，然后通过化学-机械抛光(即CMP)进行回蚀刻而在沟槽12中选择性地形成。
接着，如图20所示，将诸如硼的p型杂质选择性地离子注入外延层EP中以形成p型基极区106。p型基极区106在相邻的沟槽栅极105之间形成，并且形成为耦合到p型列区104，并且还在比沟槽栅极105的底表面浅的位置形成。
接着，如图21所示，将诸如砷的n型杂质选择性地离子注入到外延层EP以形成n+型源极区111。n+源极区111在p型基极区106的表面上形成，并且位于沟槽栅极105的末端。
接着，在半导体衬底100的整个表面上形成绝缘膜113，然后使用光致抗蚀剂膜18通过普通光刻和蚀刻技术对绝缘膜113进行图案化，以在绝缘膜113中形成接触孔CH1和CH2。接触孔CH1和CH2分别在相邻的沟槽栅极105之间和p型列区104上形成。此外，通过部分地刻蚀外延层EP的表面，形成接触孔CH1和CH2的底表面以到达p型基极区106。
接着，通过使用光致抗蚀剂膜18和绝缘膜113作为掩膜的p型杂质的离子注入，在从接触孔CH1和CH2暴露的p型基极区106中形成p+型基极接触区107。接着，在移除光致抗蚀剂膜18之后，如图22所示，形成包含例如铝作为主要成分的源极电极114，并且在半导体衬底100的下表面上形成具有由例如Au/Cu/Ni制成的多层结构的漏极电极110，从而完成垂直MOSFET。
尽管已经基于实施例对本发明人制造的本发明进行了具体描述，但是本发明不限于上述实施例，并且可以在不偏离其要点的情况下进行各种修改。
例如，虽然本发明已经示出n沟槽的垂直MOSFET，但是本发明还可以应用于p沟槽的垂直MOSFET。在这种情况下，构成漂移区的半导体层的源极区、漏极区、基极区(也称为沟道形成区)和导电类型可以反向配置。
此外，图2和图7中所示的条形p型列区104可以在如图23至图26中所示的在平面图中以交错或网格形状布置的n型漂移区中布置。图23至图26是示出了第四修改示例至第八修改示例中的半导体器件的平面图。
在这种情况下，如图23至图26所示，平面图中的p型列区104的占用率在图23和图25中所示的交错布置中是最低的，由于电流路径的宽度变宽，对导通电阻减小的影响较高。此外，即使在图24和图26中所示的方形网格布置的情况下，由于电流路径的宽度大于图2和图7中所示的条形布置，因此对导通电阻减小的影响也较高。
另一方面，由于获得高击穿电压所需的耗尽的缓解更优选p型列区之间的短距离，以及由p型列区和n型列区(n型漂移区)形成的PN结的均匀关系，因此它变得与导通电阻减小的缓解相反，并且按条形布置、方形网格布置和交错布置的顺序适用于高击穿电压。
如图27所示，p型列区104不可以直接耦合到p型基极区106的底表面。在这种情况下，尽管p型列区104变为p型列区104被n型漂移区108包围并且随后电势浮动的状态，但是p型基极区106和p型列区104之间的n型区的厚度T1可以被设置为足以抑制从p型基极区106到p型列区104的孔的支撑势垒的厚度，在垂直MOSFET的实际操作期间，作为优选值，p型基极区106和p型列区104之间的n型区的厚度T1可以被设置为例如约0.5μm。
通过这种配置，可以有助于垂直MOSFET的击穿电压的改善，因为可以比图3所示的结构更优化耗尽层的分布。

Claims (13)

1.一种包括垂直MOSFET的半导体器件，所述垂直MOSFET包括：
半导体衬底，所述半导体衬底具有第一导电类型的半导体层的漂移区；
与所述第一导电类型相反的第二导电类型的半导体层的基极区，所述基极区在所述漂移区的表面上形成；
与所述第一导电类型相反的第二导电类型的半导体层的多个列区，所述多个列区以预定间隔布置在所述漂移区中，并且形成为与所述基极区接触；
多个沟槽，在所述漂移区中形成，并且布置在相邻的多个列区之间，所述多个沟槽均具有比所述基极区更深的底表面；
多个栅极电极，被形成为使得通过在所述多个沟槽的每个表面上形成的栅极绝缘层而嵌入在所述多个沟槽中；和
第一导电类型的半导体层的多个源极区，形成在所述基极区中，所述多个源极区在所述多个栅极电极的每一侧上形成。
2.根据权利要求1所述的半导体器件，其中所述多个列区和所述多个栅极电极在平面图中沿第一方向以条形形成。
3.根据权利要求2所述的半导体器件，其中所述多个列区的底表面位于所述漂移区中比所述多个沟槽的所述底表面更深的位置。
4.根据权利要求2所述的半导体器件，其中所述多个列区在平面图中不布置在所述多个栅极电极中的相邻的栅极电极之间。
5.根据权利要求2所述的半导体器件，其中所述相邻的多个列区的间隔被设置为所述相邻的多个栅极电极的间隔的两倍以上。
6.根据权利要求2所述的半导体器件，其中所述多个列区被布置为耦合到所述基极区的底表面。
7.根据权利要求2所述的半导体器件，其中所述多个列区沿所述半导体衬底的厚度方向、以预定距离与所述基极区的所述底表面分离地布置。
8.一种半导体器件，包括：
半导体衬底，所述半导体衬底具有第一导电类型的半导体层的漂移区；
与所述第一导电类型相反的第二导电类型的半导体层的基极区，所述基极区在所述漂移区的表面上形成；
与所述第一导电类型相反的第二导电类型的半导体层的多个列区，所述多个列区以预定间隔布置在所述漂移区中，并且形成为与所述基极区接触；
多个沟槽，所述多个沟槽的底表面到达比所述基极区更深的位置，并且布置在所述相邻的多个列区之间；
多个栅极电极，被形成为使得通过在所述多个沟槽的每个表面上形成的栅极绝缘层而嵌入在所述多个沟槽中；和
第一导电类型的半导体层的多个源极区，在所述基极区中形成，所述多个源极区在所述多个栅极电极的每一侧上形成，
其中所述多个栅极电极在平面图中沿第一方向以条形形成，并且
其中所述多个列区在平面图中沿所述第一方向以交错形状布置。
9.根据权利要求8所述的半导体器件，其中以所述交错形状布置的所述多个列区的底表面位于所述漂移区中比所述多个沟槽的所述底表面更深的位置。
10.根据权利要求9所述的半导体器件，其中所述多个列区在平面图中不布置在所述多个栅极电极中的相邻的栅极电极之间。
11.一种半导体器件，包括：
半导体衬底，所述半导体衬底具有第一导电类型的半导体层的漂移区；
与所述第一导电类型相反的第二导电类型的半导体层的基极区，所述基极区在所述漂移区的表面上形成；
与所述第一导电类型相反的第二导电类型的半导体层的多个列区，所述多个列区以预定间隔布置在所述漂移区中，并且形成为与所述基极区接触；
多个沟槽，所述多个沟槽的底表面到达比所述基极区更深的位置，并且布置在所述相邻的多个列区之间；
多个栅极电极，被形成为使得通过在所述多个沟槽的每个表面上形成的栅极绝缘层嵌入所述多个沟槽；和
第一导电类型的半导体层的多个源极区，在所述基极区中形成，所述多个源极区在所述多个栅极电极的每一侧上形成，
其中所述多个栅极电极在平面图中沿第一方向以条形布置，并且
其中所述多个列区在平面图中沿所述第一方向以网格形状布置。
12.根据权利要求11所述的半导体器件，其中以所述网格形状布置的所述多个列区的底表面位于所述漂移区中比所述多个沟槽的所述底表面更深的位置。
13.根据权利要求11所述的半导体器件，其中所述多个列区在平面图中不布置在所述多个栅极电极中的相邻的栅极电极之间。
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