CN112151476A - 半导体器件组件 - Google Patents

半导体器件组件 Download PDF

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Publication number
CN112151476A
CN112151476A CN202010535742.XA CN202010535742A CN112151476A CN 112151476 A CN112151476 A CN 112151476A CN 202010535742 A CN202010535742 A CN 202010535742A CN 112151476 A CN112151476 A CN 112151476A
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China
Prior art keywords
semiconductor die
leadframe
disposed
heat slug
conductive
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Pending
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CN202010535742.XA
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English (en)
Inventor
J·蒂萨艾尔
吴宗麟
B·多斯多斯
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Publication of CN112151476A publication Critical patent/CN112151476A/zh
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Abstract

本发明题为“半导体器件组件”。在一般方面,一种半导体器件装置可包括引线框,该引线框包括多个引线,该多个引线被配置成为该装置提供电气连接。该装置还可包括设置在引线框上的半导体管芯以及将半导体管芯与引线框电耦接的导电夹。该装置还可包括设置在导电夹上的散热块。该散热块可包括导热并且电绝缘的材料。

Description

半导体器件组件
技术领域
本说明书整体涉及半导体器件组件,诸如具有双面冷却的半导体器件封装件或模块。
背景技术
一般来讲,金属(例如,铜)散热块可包括在半导体器件组件(例如,封装件或模块)中,以将由包括在半导体组件中的一个或多个半导体管芯(或其他电子部件)产生的热量(在操作期间)传导至组件的周围(外部)环境,诸如传导至可与组件耦接的散热器、冷却夹套等。然而,此类金属(铜)散热块可能具有某些缺点。例如,金属散热块可诸如通过上面可设置有散热块的导电夹电连接(例如,电短路)到半导体管芯(例如,到半导体器件组件的电气节点)。散热块与半导体管芯之间的此类电气连接可导致半导体管芯与相关电气系统中的其他部件之间的电短路,这是不期望的。另外,可限制金属散热块的面积(例如,外部暴露面积)以防止在半导体器件组件内发生不期望的电气连接(例如,电短路)(例如,由于对导线接合部等的干扰而引起),这继而可限制组件的热耗散能力。
发明内容
在一个一般方面,一种装置可包括引线框,该引线框包括多个引线,该多个引线被配置成为装置提供电气连接。该装置还可包括设置在引线框上的半导体管芯以及将半导体管芯与引线框电耦接的导电夹。该装置还可包括设置在导电夹上的散热块。该散热块可包括导热并且电绝缘的材料。
在另一个一般方面,一种装置可包括引线框,该引线框包括多个引线,该多个引线被配置成为装置提供电气连接。该装置还可包括设置在引线框上的半导体管芯、将半导体管芯与引线框电耦接的第一导电夹,以及将半导体管芯与引线框电耦接的第二导电夹。该装置还可包括导线接合部,该导线接合部将半导体管芯与引线框的多个引线中的一个引线电耦接。该装置还可包括设置在第一导电夹和第二导电夹上的散热块。该散热块可包括导热并且电绝缘的材料。该半导体管芯可被布置在平面中,并且与平面正交的线可与引线框、半导体管芯、导线接合部和散热块相交。
在另一个一般方面,一种装置可包括引线框,该引线框包括多个引线,该多个引线被配置成为装置提供电气连接。该装置还可包括设置在引线框上的第一半导体管芯、设置在引线框上的第二半导体管芯以及将第一半导体管芯与第二半导体管芯和引线框电耦接的导电夹。该装置还可包括设置在导电夹上的散热块。该散热块可包括导热并且电绝缘的材料。
一个或多个实施方式的细节在附随附图和以下描述中阐明。其他特征将从说明书和附图中以及从权利要求书中显而易见。
附图说明
图1是示意性地示出半导体器件组件的图。
图2A至图2E是示出半导体器件组件的各种视图的图。
图3A至图3F是示出另一个半导体器件组件的各种视图的图。
图4A至图4E是示出另一个半导体器件组件的各种视图的图。
图5A至图5E是示出另一个半导体器件组件的各种视图的图。
图6A是示出一种用于制造半导体器件组件(诸如本文所述的那些)的方法的流程图。
图6B和图6C是示出图6A的方法的散热块附着操作的实施方式的流程图。
具体实施方式
半导体器件组件(例如,半导体器件封装件、模块组件、组件、多芯片模块(MCM)等),诸如本文所述的那些,可包括引线框、一个或多个半导体管芯、半导体管芯和/或引线框之间的导线接合部、一个或多个导电夹以及导热电绝缘散热块。在一些实施方式中,散热块可包括陶瓷材料。在一些实施方式中,散热块可设置在多个导电夹上,并且该组件可允许例如经由该组件的第一侧上的引线框以及经由该组件的与该组件的第一侧相对的第二侧上的散热块进行双面冷却。
本文所述的示例性实施方式可克服上面讨论的缺点中的至少一些。例如,使用电绝缘散热块可防止在半导体器件组件的半导体管芯与相关电气系统中的其他部件之间发生电短路。另外,可增大电绝缘散热块的面积(例如,暴露面积),例如以桥接多个导电夹,这可改善对应半导体器件组件的热耗散能力。
图1是示意性地示出半导体器件组件100的图。图1的示例性实施方式示出了半导体器件组件(组件)100的示意性侧视图。应当指出,组件100的各方面以举例的方式给出,并且这些方面也可应用于图2A至图5E所示的半导体器件组件的示例性实施方式。
如图1所示,组件100可包括引线框(基架等)110、半导体管芯120、导电夹130、导线接合部140、导热且电绝缘的散热块150、粘合剂层160和模塑料170。虽然图1中未具体示出,但组件100可包括其他元件,诸如相应的焊料或粘合剂层,这些焊料或粘合剂层可用于将半导体管芯120耦接到引线框110(例如,耦接到引线框110的管芯附着焊盘)并且将导电夹130耦接(例如,电耦接)到引线框110和半导体管芯120。
在一些实施方式中,诸如本文所述的那些,引线框110可包括多个引线框部分,诸如一个或多个管芯附着焊盘和多个引线(信号引线、功率端子等)。引线可被配置成为装置提供电气连接。例如,引线可被配置成与例如印刷电路板耦接以提供从印刷电路板到组件100(例如,到半导体管芯120和/或组件100的其他元件)的电气连接。然后,导电夹130和导线接合部140可在半导体管芯120与引线框110之间提供电气连接。在一些实施方式中,组件100中可包括附加的半导体管芯120、导电夹130和/或导线接合部140,诸如在本文所述的各种实施方式中。例如,可包括不同半导体管芯120之间的导线接合部140,导电夹130可与不同半导体管芯120和/或引线框110耦接并且可在它们之间提供电气连接,等等。
如图1所示,半导体管芯120可设置在引线框110上,导电夹130可设置在引线框110和半导体管芯120上,并且散热块150可设置在导电夹130上。在一些实施方式诸如组件100中,散热块150可从导电夹130在半导体管芯120和导线接合部140之上延伸(横向延伸)。与例如使用不延伸超过导电夹130的金属散热块的当前实施方式相比,这可允许增大通过模塑料170暴露的散热块150的面积。这种增大的暴露面积可改善组件100的热耗散性能。例如,在一些实施方式中,可实现给定半导体器件组件的热阻(例如,结到壳的热阻)减小10%、20%或更大。
在组件100(和其他组件)中,可使用低回路导线接合部形成一个或多个导线接合部140,使得散热块150不接触(干扰、损坏等)一个或多个导线接合部140。此外,在一些实施方式中,可例如使用背面研磨工艺来减薄半导体管芯120,以在一个或多个导线接合部140与散热块150之间提供间隙。
如图1所示,粘合剂层160可将散热块150与导电夹130耦接。在一些实施方式中,粘合剂层160可为粘合剂膜(例如,非导电的线上膜(film-on-wire)粘合剂膜)。如图1所示,在此类实施方式中,导线接合部140的至少一部分可由于固化(烘烤)工艺而嵌入粘合剂层160中。
如图1所示,模塑料170可至少部分地包封装置100。例如,引线框(诸如引线框110的引线)和散热块150的部分(表面)可通过模塑料暴露。这些暴露表面可提供装置100的双面冷却,其中在组件100的电气操作期间产生的热量可通过组件100的第一侧(例如,底侧)上的引线框110并且通过组件100的第二侧(例如,顶侧)上的散热块150耗散。在一些实施方式中,可使用研磨工艺通过模塑料170暴露散热块150以从散热块150的上表面去除模塑料,诸如下文相对于图6A进一步描述。
如图1所示,半导体管芯120(其可为半导体器件组件的多个半导体管芯中的一个)可被布置在平面P中(在平面P中对准、限定平面P等)。也如图1所示。与平面P正交的第一线L1可与引线框110、半导体管芯120、导线接合部140和散热块150相交(例如,与包括它们的竖直叠堆相交)。换句话讲,散热块150可从导电夹130在半导体管芯120和导线接合部140之上延伸(横向延伸),如上面所指出的。如图1中进一步所示,也与平面P正交的第二线L2可与引线框110、半导体管芯120、导电夹130和散热块150相交(例如,与包括它们的竖直叠堆相交)。图2A至图5E的示例性半导体器件组件也可在它们的引线框、半导体管芯、导电夹、导线接合部和散热块之间具有类似的关系。
如上面所指出的,图2A至图5E示出了可包括图1的组件100的各方面的半导体器件组件的示例性实施方式。然而,为了简洁起见,可能不会相对于图2A至图5E的示例性实施方式来具体讨论这些方面。另外,在图2A至图5E中,对于那些元件中的每一个,可能未示出相同或类似元件的参考标号。另外,来自给定实施方式的一个视图的参考标号在相关视图中可以不重复。此外,在一些情况下,出于比较不同视图的目的,来自给定实施方式的一个视图的参考标号可以在其他视图中重复,但是可以不相对于每个视图进行具体讨论。
图2A至图2E是示出半导体器件组件200的各种视图的图。图2A是无散热块的组件200的等轴视图,以示出组件400的(设置在散热块下方的)元件的布置。图2B是包括散热块的组件200的等轴视图。在图2A和图2B中,模塑料由轮廓指示(例如,被显示为透明的),使得设置在模塑料内的组件200的其他元件在那些视图中可见。图2C是与图2B的视图相对应的组件200的等轴视图,将模塑料显示为不透明的。图2D是示出图2C所示的组件200的底侧的等轴视图。图2E是沿图2B所示的剖面线2E-2E的组件200的剖视图,其中模塑料再次由轮廓示出。
参见图2A,组件200包括引线框210、半导体管芯220、导电夹230和235、导线接合部240和模塑料270。如上面所指出的,图2A中未示出散热块。引线框210可包括多个部分,该多个部分包括多个引线212,该多个引线被配置成与印刷电路板耦接(电耦接)。如图2A所示,半导体管芯220(其可为分立的功率晶体管)可设置在引线框210上。导电夹230和235可设置在引线框210和半导体管芯220上(并且与它们电耦接)。导电夹230和235可在引线框210与半导体管芯220之间提供相应的电气连接(例如,到功率晶体管的源极和漏极)。也如图2A所示,导线接合部240还可在半导体管芯220与引线框210之间提供电气连接(例如,到功率晶体管的栅极)。如图2A进一步所示,模塑料270(以轮廓示出)可包封(部分地包封)装置200。例如,引线框210(诸如引线212)的部分(表面)可通过模塑料270暴露以提供对与半导体管芯220的电气连接的建立。
参见图2B,示出了具有导热且电绝缘的散热块250的组件200。在一些实施方式中,散热块250(以及本文所述的其他示例性实施方式的散热块)可包括陶瓷材料。例如,在一些实施方式中,散热块250可包括氧化铝(Al2O3)、氮化铝(AlN)和氧化铍(BeO)中的至少一种。在一些实施方式中,散热块250可包括其他导热且电绝缘的材料,诸如金刚石、硅、碳化硅等。
如图2B所示,散热块250可设置在导电夹230和235上,并且可以诸如以上关于图1所讨论的布置(竖直布置)在半导体管芯220和导线接合部240中的一个或多个导线接合部之上(上方、竖直上方等)延伸(横向延伸)超过导电夹230和235。在组件200中,散热块250的表面(上表面)可通过模塑料270暴露。在一些实施方式中,散热器(或其他热耗散装置)可设置在散热块250以及对应电气系统中所包括的其他组件的散热块的暴露表面上。由于散热块250是电绝缘的,因此散热块250不电连接到导电夹230和235,从而防止通过散热块250电连接(电短路)到半导体管芯220的风险。图2B中还示出了剖面线2E-2E,其中剖面线2E-2E与图2E所示的组件200的剖视图相对应。
参见图2C,示出了组件200,其中模塑料270被显示为不透明的,相比之下,模塑料270在图2A和图2B中被显示为透明的。如图2C所示,散热块250的表面(上表面)通过模塑料270暴露。此外,引线框的部分(诸如引线212的表面)也通过模塑料270暴露。图2D示出了组件200的底侧的视图(与图2C的视图相比)。如图2D所示,引线框的部分(诸如引线212的表面)通过模塑料270暴露。如本文所述,组件200可通过组件200的第一侧上的引线框并且通过组件200的第二侧上的散热块250来提供双面冷却(热耗散)。
如上面所指出的,图2E示出了沿图2B中的剖面线2E-2E的装置200的剖视图。如图2E所示,半导体管芯220设置在引线框210上,导电夹230和235设置在半导体管芯220和引线框210上(例如,设置在引线212上),并且散热块250设置在导电夹230和235上,其中粘合剂层260(例如,环氧树脂、粘合剂膜等)设置在散热块250与导电夹230和235之间。如本文所讨论的,由于散热块250是电绝缘的,因此散热块250可设置在这两个导电夹230和235上(桥接这两个导电夹),其中导电夹230和235保持彼此电绝缘隔离。图2E还进一步示出了模塑料270对装置200的包封,其中散热块250的表面和引线框210的表面通过模塑料270暴露。
图3A至图3F是示出半导体器件组件300的各种视图的图。图3A是无散热块的组件300的等轴视图,以示出组件400的(设置在散热块下方的)元件的布置。图3B是包括散热块的组件300的等轴视图。与图2A和图2B一样,在图3A和图3B中,模塑料由轮廓(例如,透明的)指示,使得设置在模塑料内的组件300的其他元件在那些视图中是可见的。图3C是与图3B的视图相对应的组件300的等轴视图,将模塑料显示为不透明的。图3D是示出图3C所示的组件300的底侧的等轴视图。图3E是沿图3B所示的方向3E的组件300的侧视图,其中模塑料再次以轮廓示出。图3F是沿图3B所示的剖面线3F-3F的组件300的剖视图,其中模塑料由轮廓示出。
参见图3A,组件300包括引线框310、半导体管芯320、322和324、导电夹330、导线接合部340和模塑料370。如上面所指出的,图3A中未示出散热块。引线框310可包括多个部分,该多个部分包括多个引线312,该多个引线被配置成与印刷电路板耦接(电耦接)。如图3A所示,半导体管芯320、322和324(其可实现功率晶体管对和相关联的控制电路)可设置在引线框310上。导电夹330可设置在引线框310以及半导体管芯320和322(而不是半导体管芯324)上(并且与它们电耦接)。导电夹330可在引线框310与半导体管芯320和322之间提供电气连接(例如,到功率晶体管对的开关节点)。也如图3A所示,导线接合部340还可在半导体管芯320、322和324与引线框310之间提供电气连接。即,导线接合部340可提供半导体管芯到半导体管芯的电气连接,以及半导体管芯到引线框的电气连接。
如图3A进一步所示,模塑料370(以轮廓示出)可包封(部分地包封)装置300。例如,引线框310(诸如引线312)的部分(表面)可通过模塑料370暴露以提供对与半导体管芯320、322和324的电气连接的建立。
参见图3B,示出了具有导热且电绝缘的散热块350的组件300。在一些实施方式中,如上面所指出的,散热块350可包括陶瓷材料。例如,在一些实施方式中,散热块350可包括Al2O3、AlN和BeO中的至少一种。在一些实施方式中,散热块350可包括其他导热且电绝缘的材料。
如图3B所示,散热块350可设置在导电夹330上,并且可在半导体管芯320、322和324以及导线接合部340中的一个或多个导线接合部之上(上方、竖直上方等)延伸(横向延伸)超过导电夹330,如在诸如上文相对于图1所讨论的布置(竖直布置)中那样。在组件300中,散热块350的表面(上表面)可通过模塑料370暴露。在一些实施方式中,散热器(或其他热耗散装置)可设置在散热块350以及对应电气系统中所包括的其他组件的散热块的暴露表面上。由于散热块350是电绝缘的,因此散热块350不电连接到导电夹330,从而防止通过散热块350电连接(电短路)到半导体管芯320和322的风险。
图3B中示出方向线3E,其中方向线3E与图3E所示的组件300的侧视图相对应。图3B中还示出剖面线3F-3F,其中剖面线3F-3F与图3F所示的组件300的剖视图相对应。
参见图3C,示出了组件300,其中模塑料370被显示为不透明的,相比之下,模塑料370在图3A和图3B中被显示为透明的。如图3C所示,散热块350的表面(上表面)通过模塑料370暴露。此外,引线框的部分(诸如引线312的表面)也通过模塑料370暴露。图3D示出了组件300的底侧的视图(与图3C的视图相比)。如图3D所示,引线框的部分(诸如引线312的表面)通过模塑料370暴露。如本文所述,组件300可通过组件300的第一侧上的引线框并且通过组件300的第二侧上的散热块350来提供双面冷却(热耗散)。
如上面所指出的,图3E示出了沿图3B中的方向线3E的装置300的侧视图。如图3E所示,半导体管芯320、322和324设置在引线框310上,导电夹330设置在半导体管芯320和322以及引线框310上(例如,设置在引线312上),并且散热块350设置在导电夹330上,其中粘合剂层360(例如,环氧树脂、粘合剂膜等)设置在散热块350与导电夹330之间。图3E还进一步示出了模塑料370对装置300的包封,其中散热块350的表面和引线框310的表面通过模塑料370暴露。
如上面所指出的,图3F示出了沿图3B中的剖面线3F-3F的装置300的剖视图。如图3F所示,与图3E类似,半导体管芯320、322和324设置在引线框310上,导电夹330设置在半导体管芯320和322以及引线框310上(例如,设置在引线312上),并且散热块350设置在导电夹330上,其中粘合剂层360设置在散热块350与导电夹330之间。与图3E类似,图3F还进一步示出了模塑料370对装置300的包封,其中散热块350的表面和引线框310的表面通过模塑料370暴露。
图4A至图4E是示出半导体器件组件400的各种视图的图。图4A是无散热块的组件400的等轴视图,以示出组件400的(设置在散热块下方的)元件的布置。图4B是包括散热块的组件400的等轴视图。与图2A、图2B、图3A和图3B一样,在图4A和图4B中,模塑料仅由轮廓(例如,透明的)指示,使得设置在模塑料内的组件400的元件在那些视图中是可见的。图4C是与图4B的视图相对应的组件400的等轴视图,将模塑料显示为不透明的。图4D是示出图4C所示的组件400的底侧的等轴视图。图4E是沿图4B中的剖面线4E-4E的组件400的剖视图,其中模塑料由轮廓示出。
参见图4A,组件400包括引线框410、半导体管芯420、422、424、426和428、导电夹430和435、导线接合部440和模塑料470。如上面所指出的,图4A中未示出散热块。引线框410可包括多个部分,该多个部分包括多个引线412,该多个引线被配置成与印刷电路板耦接(电耦接)。如图4A所示,半导体管芯420、422、424、426和428(其可实现双相控制器)可设置在引线框410上。导电夹430可设置在引线框410以及半导体管芯420和422上(并且与它们电耦接)。导电夹430可在引线框410与半导体管芯420和422之间提供电气连接。导电夹435可设置在引线框410以及半导体管芯424和426上(并且与它们电耦接)。导电夹435可在引线框410与半导体管芯424和426之间提供电气连接。在组件400中,半导体管芯428可不被导电夹接触(不与导电夹耦接)。也如图4A所示,导线接合部440还可在半导体管芯420、422、424、426和428与引线框410之间提供电气连接。即,导线接合部440可提供半导体管芯到半导体管芯的电气连接,以及半导体管芯到引线框的电气连接。
如图4A进一步所示,模塑料470(以轮廓示出)可包封(部分地包封)装置400。例如,引线框410(诸如引线412)的部分(表面)可通过模塑料470暴露以提供对与半导体管芯420、422、424、426和428的电气连接的建立。
参见图4B,示出了具有导热且电绝缘的散热块450的组件400。在一些实施方式中,如上面所讨论的,散热块450可包括陶瓷材料。例如,在一些实施方式中,散热块450可包括Al2O3、AlN和BeO中的至少一种。在一些实施方式中,散热块450可包括其他导热且电绝缘的材料。
如图4B所示,散热块450可设置在导电夹430和435上,并且可以诸如上文相对于图1所讨论的布置(竖直布置)在半导体管芯420、422、424、426和428以及导线接合部440中的一个或多个导线接合部之上(上方、竖直上方等)延伸(横向延伸)超过导电夹430和435。在组件400中,散热块450的表面(上表面)可通过模塑料470暴露。在一些实施方式中,散热器(或其他热耗散装置)可设置在散热块450以及对应电气系统中所包括的其他组件的散热块的暴露表面上。由于散热块450是电绝缘的,因此散热块450不电连接到导电夹430和435,从而防止通过散热块450电连接(电短路)到半导体管芯420、422、424和426的风险。图4B中还示出剖面线4E-4E,其中剖面线4E-4E与图4E所示的组件400的剖视图相对应。
参见图4C,示出了组件400,其中模塑料470被显示为不透明的,相比之下,模塑料470在图4A和图4B中被显示为透明的。如图4C所示,散热块450的表面(上表面)通过模塑料470暴露。此外,引线框的部分(诸如引线412的表面)也通过模塑料470暴露。图4D示出了组件400的底侧的视图(与图4C的视图相比)。如图4D所示,引线框的部分(诸如引线412的表面)通过模塑料470暴露。如本文所述,组件400可通过组件400的第一侧上的引线框并且通过组件400的第二侧上的散热块450来提供双面冷却(热耗散)。
如上面所指出的,图4E示出了沿图4B中的剖面线4E-4E的装置400的剖视图。由于图4E的横截面是穿过半导体管芯420和424的,因此图4E中未示出半导体管芯422和426。然而,穿过半导体管芯422和426的横截面将类似于图4E所示的横截面。
如图4E所示,半导体管芯420、424和428设置在引线框410上,导电夹430设置在半导体管芯420和424以及引线框410上(例如,设置在引线412上)。如图4E进一步所示,导电夹435设置在半导体管芯424和引线框410上(例如,设置在引线412上),并且散热块450设置在导电夹430和435上,其中粘合剂层460(例如,环氧树脂、粘合剂膜等)设置在散热块450与导电夹430和435之间。如本文所讨论的,由于散热块450是电绝缘的,因此散热块450可设置在这两个导电夹430和435上(桥接这两个导电夹),其中导电夹430和435保持彼此电绝缘隔离。图4E还进一步示出了模塑料470对装置400的包封,其中散热块450的表面和引线框410的表面通过模塑料470暴露。
图5A至图5E是示出半导体器件组件500的各种视图的图。图5A是无散热块的组件500的等轴视图,以示出组件500的(设置在散热块下方的)元件的布置。图5B是包括散热块的组件500的等轴视图。与图2A、图2B、图3A、图3B、图4A和图4B一样,在图5A和图5B中,模塑料仅由轮廓(例如,透明的)指示,使得设置在模塑料内的组件500的元件在那些视图中是可见的。图5C是与图5B的视图相对应的组件500的等轴视图,将模塑料显示为不透明的。图5D是示出图5C所示的组件500的底侧的等轴视图。图5E是沿图5B中的剖面线5E-5E的组件500的剖视图,其中模塑料由轮廓示出。
参见图5A,组件500包括引线框510、半导体管芯520、522、524、526、528和529、导电夹530、535和537、导线接合部540和模塑料570。如上面所指出的,图5A中未示出散热块。引线框510可包括多个部分,该多个部分包括多个引线512,该多个引线被配置成与印刷电路板耦接(电耦接)。如图5A所示,半导体管芯520、522、524、526、528和529(其可实现多相控制器)可设置在引线框510上。导电夹530可设置在引线框510以及半导体管芯520和522上(并且与它们电耦接)。导电夹530可在引线框510与半导体管芯520和522之间提供电气连接。导电夹535可设置在引线框510以及半导体管芯524和526上(并且与它们电耦接)。导电夹535可在引线框510与半导体管芯524和526之间提供电气连接。导电夹537可设置在引线框510以及半导体管芯528和529上(并且与它们电耦接)。导电夹537可在引线框510与半导体管芯528和529之间提供电气连接。也如图5A所示,导线接合部540还可在半导体管芯522、526和529与引线框510之间提供电气连接。
如图5A进一步所示,模塑料570(以轮廓示出)可包封(部分地包封)装置500。例如,引线框510(诸如引线512)的部分(表面)可通过模塑料570暴露以提供对与半导体管芯520、522、524、526、528和529的电气连接的建立。
参见图5B,示出了具有导热且电绝缘的散热块550的组件500。在一些实施方式中,如上面所讨论的,散热块550可包括陶瓷材料。例如,在一些实施方式中,散热块550可包括Al2O3、AlN和BeO中的至少一种。在一些实施方式中,散热块550可包括其他导热且电绝缘的材料。
如图5B所示,散热块550可设置在导电夹530、535和437上,并且可以诸如上文相对于图1所讨论的布置(竖直布置)在半导体管芯520、522、524、526、528和529以及导线接合部540中的一个或多个导线接合部之上(上方、竖直上方等)延伸(横向延伸)超过导电夹530、535和537。在组件500中,散热块550的表面(上表面)可通过模塑料570暴露。在一些实施方式中,散热器(或其他热耗散装置)可设置在散热块550以及对应电气系统中所包括的其他组件的散热块的暴露表面上。由于散热块550是电绝缘的,因此散热块550不电连接到导电夹530、535和537,从而防止通过散热块550电连接(电短路)到半导体管芯520、522、524、526、528和529的风险。图5B中还示出剖面线5E-5E,其中剖面线5E-5E与图5E所示的组件500的剖视图相对应。
参见图5C,示出了组件500,其中模塑料570被显示为不透明的,相比之下,模塑料570在图5A和图5B中被显示为透明的。如图5C所示,散热块550的表面(上表面)通过模塑料570暴露。此外,引线框的部分(诸如引线512的表面)也通过模塑料570暴露。图5D示出了组件500的底侧的视图(与图5C的视图相比)。如图5D所示,引线框的部分(诸如引线512的表面)通过模塑料570暴露。如本文所述,组件500可通过组件500的第一侧上的引线框并且通过组件500的第二侧上的散热块550来提供双面冷却(热耗散)。
如上面所指出的,图5E示出了沿图5B中的剖面线5E-5E的装置500的剖视图。当图5E的横截面是穿过半导体管芯520和522时,图5E中未示出半导体管芯524、526、528和529以及导电夹535和537。然而,穿过半导体管芯524和526或穿过半导体管芯528和529的横截面将类似于图5E所示的横截面。
如图5E所示,半导体管芯520和522设置在引线框510上,导电夹530设置在半导体管芯520和522以及引线框510上(例如,设置在引线512上)。如图5E进一步所示,散热块550设置在导电夹530(以及导电夹535和537,如图5B所示)上,其中粘合剂层560(例如,环氧树脂、粘合剂膜等)设置在散热块550与导电夹530(以及夹535和537)之间。如本文所讨论的,由于散热块550是电绝缘的,因此散热块550可设置在所有三个导电夹530、535和437上(桥接所有三个导电夹),其中导电夹530、535和537保持彼此电绝缘隔离。图5E还进一步示出了模塑料570对装置500的包封,其中散热块550的表面和引线框510的表面通过模塑料570暴露。
图6A是示出用于制造半导体器件组件(诸如本文所述的那些)的方法600的流程图。图6B和图6C是示出可结合图6A的方法600(例如,方法600的框635)实现的用于执行散热块附着操作的示例性方法的流程图。在方法600中,所示的操作以举例的方式并出于说明的目的给出。在一些实施方式中,方法600的操作可以与图6A所示不同的顺序执行,可包括附加操作,和/或可消除操作。
如图6A所示,方法600在框605处包括引线框印刷操作。取决于特定实施方式,框605处的引线框印刷操作包括焊料印刷操作、粘合剂印刷操作等。框605的引线框印刷操作可例如用于限定将在半导体器件组件的引线框与一个或多个半导体管芯之间诸如利用管芯附着焊盘、信号引线、功率端子等形成连接(例如,电气连接)的位置。在框610处,方法600包括管芯附着操作,可执行该管芯附着操作以利用框605的引线框印刷材料(焊料、粘合剂等)将一个或多个半导体管芯(例如,减薄的半导体管芯)附着到引线框。取决于引线框印刷材料,管芯附着操作610可包括焊料回流操作、固化操作等。在框615处,方法600包括导线接合操作,该导线接合操作可用于在一个或多个半导体与引线框之间形成导线接合部(例如,低回路导线接合部),或者形成到半导体管芯导线接合部的半导体管芯,诸如在本文所示的实施方式中。
在框620处,方法600包括管芯顶部印刷操作,该管芯顶部印刷操作可以是焊料(或其他导电粘合剂)印刷操作,其限定将在组件的一个或多个半导体管芯与组件的一个或多个导电夹之间形成相应的电气连接的位置。管芯顶部印刷还可包括引线框上的焊料(或其他)印刷,以限定将在引线框与一个或多个导电夹之间形成相应的电气连接的位置。在框625处,可执行夹具附着和回流操作以将一个或多个导电夹与对应组件的引线框和一个或多个半导体管芯耦接。在框630处,方法600可包括助焊剂清洗操作以从框625的回流中去除助焊剂残余物,这可防止在对应半导体器件组件的操作期间的不期望的泄漏电流(通过助焊剂残余物)。
在框635处,方法600包括散热块附着操作,例如以将导热且电绝缘的散热块附着到对应组件的一个或多个导电夹。如上文所指出的,图6B和图6C(其在下文进一步详细描述)示出了散热块附着操作的示例性实施方式。
在框640处,方法600可包括模塑和模塑固化(烘烤)操作以将对应半导体器件装置(至少部分地)包封在模塑料(例如,环氧树脂模塑料等)中。在方法600中,在框640处执行的模塑期间,可将框635的散热块包覆模制(包封在模塑料中),并且在框645处,可执行研磨操作以去除模塑料的一部分,以便暴露散热块的表面,诸如在本文所示的示例性实施方式中。
在框650处,可执行去毛边和去胶(dejunk)操作以从对应组件中清除(去除)不需要的(过量的等)模塑料,此类不需要的模塑料可以是框640的模塑操作的人造制品。在方法600的框655处,执行电镀操作以电镀(例如,镀焊)对应组件的引线框的暴露部分(例如,引线、信号引线、功率端子等)。在框660处,方法600包括执行标记操作(例如,激光标记),以在模塑料中标记部分标识符。在框665处,方法600包括器件切割,例如,当使用引线框的条带或矩阵来与方法600同时产生多个单独的半导体器件组件时,可执行该器件切割以将单独的半导体组件彼此分离。
图6B是示出图6A中的框635的散热块附着操作的示例性实施方式的流程图。如图6B所示,在框635a处,执行环氧树脂分配操作。例如,可将银(Ag)环氧树脂分配在器件组件的一个或多个导电夹(来自框625)上的一个或多个表面上。在框635b处,可将导热且电绝缘的散热块附着到一个或多个导电夹(设置在一个或多个导电夹上)(例如,在环氧树脂上),并且在框635c处,可执行固化操作以固化框635a的环氧树脂,从而将散热块耦接到一个或多个导电夹。
图6C是示出图6A中的框635的散热块附着操作的另一个示例性实施方式的流程图。如图6C所示,在框635d处,可将粘合剂膜(例如,线上膜)层合在导热且电绝缘的散热块上。在框635e处,可将散热块附着到一个或多个导电夹(设置在一个或多个导电夹上),其中粘合剂膜设置在散热块与一个或多个导电夹之间。在框635f处,可执行固化操作以固化框635d的粘合剂膜,从而利用粘合剂膜将散热块耦接到一个或多个导电夹。作为框635f的固化操作的结果,(框615的)一个或多个导线接合部的至少一部分可嵌入固化的粘合剂膜中,如本文所述。
将理解,在前述描述中,当元件被提及为在另一个元件上、连接到另一个元件、电连接到另一个元件、耦接到另一个元件或电耦接到另一个元件时,该元件可以是直接地在另一个元件上、连接或耦接到另一个元件,或可以存在一个或多个中间元件。相反,当元件被提及直接在另一个元件上、直接连接到另一个元件、或直接耦接到另一个元件时,不存在中间元件。虽然在整个具体实施方式中可能不会使用术语直接在…上、直接连接到…、或直接耦接到…,但是被示为直接在元件上、直接连接或直接耦接的元件能以此类方式提及。本申请的权利要求书(如果存在的话)可被修订以叙述在说明书中描述或者在附图中示出的示例性关系。
如在本说明书中所使用的,除非根据上下文明确地指出特定情况,否则单数形式可包括复数形式。除了附图中所示的取向之外,空间相对术语(例如,在…上方、在…上面、在…之上、在…下方、在…下面、在…之下、在…之以下等)旨在涵盖器件在使用或操作中的不同取向。在一些实施方式中,在…上面和在…下面的相对术语可分别包括竖直地在…上面和竖直地在…下面。在一些实施方式中,术语邻近能包括横向邻近或水平邻近。
本文所述的各种技术的实施方式可在数字电子电路中、计算机硬件、固件、软件中或它们的组合中实现(例如,包括在其中)。一些实施方式可使用各种半导体处理和/或封装技术来实现。一些实施方式可使用与半导体基板相关联的各种类型的半导体处理技术来实现,该半导体基板包含但不限于,例如硅(Si)、砷化镓(GaAs)、氮化镓(GaN)、碳化硅(SiC)等。
虽然所描述的实施方式的某些特征已经如本文所述进行了说明,但是本领域技术人员现在将想到许多修改形式、替代形式、变化形式和等同形式。因此,应当理解,所附权利要求书旨在涵盖落入具体实施的范围内的所有此类修改形式和变化形式。应当理解,这些修改形式和变化形式仅仅以举例而非限制的方式呈现,并且可以进行形式和细节上的各种变化。除了相互排斥的组合以外,本文所述的装置和/或方法的任何部分可以任意组合进行组合。本文所述的实施方式能包括所描述的不同实施方式的功能、部件和/或特征的各种组合和/或子组合。

Claims (12)

1.一种半导体器件装置,包括:
引线框,所述引线框包括多个引线,所述多个引线被配置成为所述装置提供电气连接;
半导体管芯,所述半导体管芯设置在所述引线框上;
导电夹,所述导电夹将所述半导体管芯与所述引线框电耦接;和
散热块,所述散热块设置在所述导电夹上,所述散热块包括导热且电绝缘的材料。
2.根据权利要求1所述的装置,其中所述导热且电绝缘的材料包括陶瓷材料硅、碳化硅或金刚石中的至少一种。
3.根据权利要求1所述的装置,还包括:
低回路导线接合部,所述低回路导线接合部将所述半导体管芯与所述引线框的所述多个引线中的引线电耦接;和
粘合剂膜,所述粘合剂膜将所述散热块与所述导电夹耦接,所述低回路导线接合部的至少一部分设置在所述粘合剂膜内。
4.根据权利要求1所述的装置,其中所述半导体管芯为第一半导体管芯并且所述导电夹为第一导电夹,所述装置还包括:
第二半导体管芯,所述第二半导体管芯设置在所述引线框上;
第二导电夹,所述第二导电夹将所述第二半导体管芯与所述引线框电耦接,所述散热块还设置在所述第二导电夹上;
第三半导体管芯,所述第三半导体管芯设置在所述引线框上;和
第三导电夹,所述第三导电夹将所述第三半导体管芯与所述引线框电耦接,所述散热块还设置在所述第三导电夹上。
5.根据权利要求1所述的装置,其中所述半导体管芯为第一半导体管芯,所述装置还包括:
第二半导体管芯,所述第二半导体管芯设置在所述引线框上;和
导线接合部,所述导线接合部将所述第二半导体管芯与所述引线框的所述多个引线中的引线电耦接,
所述第二半导体管芯布置在平面中,并且与所述平面正交的线与所述引线框、所述第二半导体管芯、所述导线接合部和所述散热块相交。
6.根据权利要求1所述的装置,其中所述半导体管芯为第一半导体管芯,所述装置还包括设置在所述引线框上的第二半导体管芯,所述导电夹将所述第二半导体管芯与所述第一半导体管芯和所述引线框电耦接。
7.一种半导体器件装置,包括:
引线框,所述引线框包括多个引线,所述多个引线被配置成为所述装置提供电气连接;
半导体管芯,所述半导体管芯设置在所述引线框上;
第一导电夹,所述第一导电夹将所述半导体管芯与所述引线框电耦接;
第二导电夹,所述第二导电夹将所述半导体管芯与所述引线框电耦接;
导线接合部,所述导线接合部将所述半导体管芯与所述引线框的所述多个引线中的引线电耦接;和
散热块,所述散热块设置在所述第一导电夹和所述第二导电夹上,所述散热块包括导热且电绝缘的材料,
所述半导体管芯布置在平面中;与所述平面正交的线与所述引线框、所述半导体管芯、所述导线接合部和所述散热块相交。
8.根据权利要求7所述的装置,还包括环氧树脂材料,所述环氧树脂材料将所述散热块与所述第一导电夹和所述第二导电夹耦接。
9.根据权利要求7所述的装置,还包括粘合剂膜,所述粘合剂膜将所述散热块与所述第一导电夹和所述第二导电夹耦接,所述导线接合部的至少一部分设置在所述粘合剂膜内。
10.一种半导体装置,包括:
引线框,所述引线框包括多个引线,所述多个引线被配置成为所述装置提供电气连接;
第一半导体管芯,所述第一半导体管芯设置在所述引线框上;
第二半导体管芯,所述第二半导体管芯设置在所述引线框上;
导电夹,所述导电夹将所述第一半导体管芯与所述第二半导体管芯和所述引线框电耦接;和
散热块,所述散热块设置在所述导电夹上,所述散热块包括导热且电绝缘的材料。
11.根据权利要求10所述的装置,其中所述导电夹为第一导电夹,所述装置还包括:
第三半导体管芯,所述第三半导体管芯设置在所述引线框上;
第四半导体管芯,所述第四半导体管芯设置在所述引线框上;
第二导电夹,所述第二导电夹将所述第三半导体管芯与所述第四半导体管芯和所述引线框电耦接,所述散热块还设置在所述第二导电夹上;
第五半导体管芯,所述第五半导体管芯设置在所述引线框上;和
导线接合部,所述导线接合部将所述第五半导体管芯与所述引线框的所述多个引线中的引线电耦接,
所述第五半导体管芯布置在平面中,与所述平面正交的线与所述引线框、所述第五半导体管芯、所述导线接合部和所述散热块相交。
12.根据权利要求10所述的装置,其中所述导电夹为第一导电夹,所述装置还包括:
第三半导体管芯,所述第三半导体管芯设置在所述引线框上;
第四半导体管芯,所述第四半导体管芯设置在所述引线框上;
第二导电夹,所述第二导电夹将所述第三半导体管芯与所述第四半导体管芯和所述引线框电耦接,
所述散热块还设置在所述第二导电夹上;
第五半导体管芯,所述第五半导体管芯设置在所述引线框上;
第六半导体管芯,所述第六半导体管芯设置在所述引线框上;和
第三导电夹,所述第三导电夹将所述第五半导体管芯与所述第六半导体管芯和所述引线框电耦接,
所述散热块还设置在所述第三导电夹上。
CN202010535742.XA 2019-06-28 2020-06-12 半导体器件组件 Pending CN112151476A (zh)

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DE102021129753A1 (de) * 2020-12-17 2022-06-23 Infineon Technologies Ag Halbleiter-Packages und Verfahren zum Herstellen derselben
US11742318B2 (en) * 2021-04-23 2023-08-29 Texas Instruments Incorporated Split tie bar for clip stability

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090001599A1 (en) 2007-06-28 2009-01-01 Spansion Llc Die attachment, die stacking, and wire embedding using film
US8354740B2 (en) 2008-12-01 2013-01-15 Alpha & Omega Semiconductor, Inc. Top-side cooled semiconductor package with stacked interconnection plates and method
US20120098117A1 (en) * 2010-10-22 2012-04-26 Renesas Technology America, Inc. Power and thermal design using a common heat sink on top of high thermal conductive resin package
US9961798B2 (en) * 2013-04-04 2018-05-01 Infineon Technologies Austria Ag Package and a method of manufacturing the same
JP6318064B2 (ja) * 2014-09-25 2018-04-25 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR101694657B1 (ko) * 2016-08-04 2017-01-09 제엠제코(주) 방열 구조를 갖는 반도체 패키지

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