CN112135933B - 晶核层的沉积方法 - Google Patents

晶核层的沉积方法 Download PDF

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CN112135933B
CN112135933B CN201980032612.XA CN201980032612A CN112135933B CN 112135933 B CN112135933 B CN 112135933B CN 201980032612 A CN201980032612 A CN 201980032612A CN 112135933 B CN112135933 B CN 112135933B
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C.M.莫德
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Abstract

本发明涉及一种直接在基板(1)的表面(2)上沉积晶核层(3)的方法，所述晶核层由第III主族和第V主族元素构成，所述基板由第IV主族元素构成，其中，含有第III主族元素的第一气态原料连同含有第V主族元素的第二气态原料在大于500℃的处理温度下被置入包含基板(1)的处理室(8)中。本质上，至少在开始沉积晶核层(3)时，第一和第二气态原料连同含有第IV主族元素的第三气态原料被输入到处理室(8)中，在沉积出的第III‑V主族晶体中施加n掺杂物，其中在掺杂物浓度小于1x1018cm‑3的情况下实现衰减降低。

Description

晶核层的沉积方法
技术领域
本发明涉及一种直接在基板的表面上沉积晶核层的方法，所述晶核层由第III主族和第V主族元素构成，所述基板由第IV主族元素构成，其中，连同含有第III主族元素的第一气态原料一起将含有第V主族元素的第二气态原料在大于500℃的处理温度下置入包含基板的处理室中。至少在晶核层开始沉积时，含有第V主族元素的气态原料附加地被输入到处理室中，该气态原料在层中实现掺杂。
此外，本发明涉及根据所述方法制备的层序列、尤其HFET晶体管(异质结场效应晶体管)。
背景技术
在文献JP 2013030725 A已知前述类型的方法。除了第III主族和第V主族元素之外还附加地将硅作为掺杂物以较高的浓度施加在晶核层中，从而抑制机械弯曲度。
HFET(高电子迁移率晶体管)或异质结场效应晶体管由一种层序列构成，其中在硅质基板上首先沉积出由AlN构成的晶核层。在晶核层上沉积出由GaN构成的缓冲层。在缓冲层上沉积出作为活性层的AlGaN层，从而在活性层和缓冲层之间构成二维的电子气体。
用于制备高电子迁移率晶体管的备选的方法在文献US 9,917,156 B1中描述。在硅质基板上首先沉积出由硅构成的晶核层。由于在处理室中的污染，这由于附着在处理室的壁部的锗、铝或类似物导致，因此硅质晶核层具有p传导的特性。应通过在晶核层中掺杂金属补偿p掺杂量。在硅质晶核层上沉积出第III-V主族的缓冲层。
当在基板上沉积第III-V主族的晶核层时，在晶核层和基板之间构成具有高导电性的界面。导电的界面的构成主要归因于在沉积晶核层(AlN层)时相对较高的温度。但这种导电性的原因至今还不是完全明了。原子经两个相互邻接的层的界面的扩散同样可以导致导电性。由此导致较强的内电场，其能够实现载流子在界面上的累积。在晶核层和基板之间的界面内导电性提高的这种现象在较高的开关频率情况下由于扩散和衰减强烈地损害了构件的特性。
文献“Growth and studies of Si-doped AlN-layer,Journal of crystalgrowth310(2008)4939-4941(硅掺杂的AlN层的生长与研究，晶体生长杂志)”描述了掺杂硅的AlN层在由蓝宝石构成的基板上的沉积，其中，使用硅烷作为掺杂物。
文献US 2002/0117104 A1和US 2003/0092263 A1描述了一种用于沉积第III和第V主族的半导体层的沉积。
发明内容
本发明所要解决的技术问题是，提供一种措施，通过这种措施可以尤其在以GaN为基础的HFET的构件结构下避免杂散的扩散效应。
所述技术问题按照本发明通过一种直接在基板的表面上沉积晶核层的方法解决，所述晶核层由第III主族和第V主族元素构成，所述基板由第IV主族元素构成，其中，连同含有第III主族元素的第一气态原料一起将含有第V主族元素的第二气态原料在大于500℃的处理温度下置入包含基板的处理室中，其中，至少在晶核层的沉积开始时，将含有第IV主族元素的第三气态原料连同第一和第二气态原料一起输入到处理室中，其中，在所述晶核层上沉积缓冲层，并且在所述缓冲层上沉积活性层，使得在所述活性层和缓冲层之间的界面上构成二维的电子气体，在此规定，在晶核层的沉积开始时所述第三气态原料在所述处理室中的分压或者质量流量选择为，使得所述第三气态原料实现大于2x1017cm-3并且小于5x1017cm-3的掺杂量并且实现高频衰减的减小。
所述技术问题按照本发明还通过一种直接在基板的表面上沉积晶核层的方法解决，所述晶核层由第III主族和第V主族元素构成，所述基板由第IV主族元素构成，其中，连同含有第III主族元素的第一气态原料一起将含有第V主族元素的第二气态原料在大于500℃的处理温度下置入包含基板的处理室中，其中，至少在晶核层的沉积开始时，将含有第IV主族元素的第三气态原料连同第一和第二气态原料一起输入到处理室中，在此规定，在晶核层的沉积开始时所述第三气态原料在所述处理室中的分压或者质量流量选择为，使得所述第三气态原料实现大于2x1017cm-3并且小于5x1017cm-3的掺杂量，其中，所述晶核层在30至300mbar的总压力下被沉积。
所述技术问题按照本发明还通过一种根据前述类型的方法制备的层序列解决，其中，在由第IV主族元素构成的基板的表面上沉积出由第IV主族和第V主族元素构成的晶核层，所述晶核层至少在其与所述表面直接邻接的区域中被掺杂有第IV主族元素。
首先和主要地，通过修改在晶核层生长时的沉积参数降低扩散和衰减。首先和主要建议，至少在晶核层沉积开始时，第三气态原料连同第一和第二气态原料被输入到处理室中，其中，第三气态原料发挥一定的掺杂效应。第一和第二气态原料如此输入到处理室中，使得在基板的表面上沉积出化学计量正确的多组分晶体、尤其第III-V主族的晶体。在本发明的优选的设计方案中，基板是具有(111)或(110)定向的硅质基板。第III主族元素可以是铝、但也可以是锗或铟；第V主族元素可以是氮，但是也可以是砷或磷。第一气态原料可以是含有铝、锗或铟的金属有机化合物、例如TMAl。第二气态原料可以是第V主族-氢化合物、尤其氮-氢化合物、例如NH3。发生晶核层沉积的处理温度在800℃至1200℃的范围内，在所述晶核层中优选将铝和氮以1：1的比例加入。沉积过程在30至300mbar的总压力下实施。在优选的设计方案中，第二气态原料相对于第一气态原料的摩尔比例、也就是优选氮化合物相对于铝化合物的摩尔比例大约为10至5000。在第一气态原料(第III主族)的分压下设定的晶核层的生长率优选在0.01至2μm/h之间。按照本发明，除了两个构成晶体矩阵的气态原料之外，还附加地将第三气态原料输入到处理室内，这实现n掺杂、尤其弱n掺杂，其中，在层中的掺杂物浓度小于1x1019cm-3。第三原料具有掺杂物的功能，该第三原料既可以在晶核层的整个沉积持续时间中输入，也可以仅部分地在晶核层沉积开始时输入。适合的原料是硅的氢化合物或锗的氢化合物。第三气态原料例如可以是SinH2n+2或GenH2n+2的结构式。原则上考虑含有硅或锗的各种气态原料。在处理室内的第三气态原料的分压或第三气态原料的气体流量优选如此设置，使得掺杂物水平在1x1017cm-3至1x1018cm-3的范围内。在优选的方法中，在硅质基板的表面上如此施加AlN晶核层，即，使得硅-氢化合物或锗-氢化合物、例如硅烷或锗烷连同TMAl和NH3被输入处理室中。
在本发明的改进方案中建议，在晶核层上沉积缓冲层，所述缓冲层由第III主族的氮化物的材料系统构成、尤其AlN、GaN、InN、AlGaN、InGaN或AlInGaN。另外的层同样也可以被掺杂。硅也可视作掺杂物。在至少一个缓冲层上可以沉积出另外一个或多个活性层，为了产生异质结场效应晶体管需要所述活性层，异质结场效应晶体管具有在例如活性层和缓冲层或者在两个活性层之间的二维的电子气体。GaN/AlN、GaN/AlGaN、GaN/AlInN、InGaN/AlN、InGaN/GaN和/或InGaN/AlInN异质结构尤其适用于此。
以这些结构(其中以前述方式沉积出晶核层)的实验实现明显更少的衰减。共面电路的测量的高频衰减(正向传输S21)在最大1018cm-3的掺杂物水平下具有明显低的衰减值，在Si基板上在大约200nm厚度的AlN层上沉积共面电路。
本发明还涉及一种根据所述方法制备的层序列，所述层序列由在硅质基板上沉积的第III-V主族的晶核层构成，该晶核层掺杂有V主族元素。所述晶核层承载由第III-V主族的材料构成的至少一个缓冲层。在缓冲层和活性层之间产生二维的电子气体。
附图说明
以下结合附图阐述本发明的实施例。在附图中：
图1示出高电子迁移率晶体管的层结构示意图，
图2示出用于沉积出图1所示的层顺序的CVD(化学气相沉积)反应器的示意图，
图3示出AlN/Si结构上的共面电路的S21衰减参数，该AlN/Si结构具有在AlN层中的不同的掺杂物。
具体实施方式
图1示出HEMT(高电子迁移率晶体管)的结构示意图，其中，在硅基板1的表面2上沉积晶核层3。在沉积晶核层3之前，以适合的方式预备硅基板1的表面2。为此，硅基板1布置在CVD反应器7的处理室8内。在通常的在50至800mbar之间的总压力下在氢气氛围中将处理室加热到900至1200℃。在预备阶段中，基板的自然的SiO2层被热学去除。随后，在更低或更高的温度下并且在其他压力下利用例如TMAl(三甲基铝)或NH3或其他气态原料的改变的压力下实施对基板的可选的另外的预处理。
AlN晶核层3的自主外延施加通过同时导入TMAl和NH3实现。晶核层3可以通过多级的工艺被沉积，其中，温度、压力和气体流量可以改变。用于沉积晶核层3的温度范围通常在800至1200℃的范围，其中，在处理室8内的总压力在30至300mbar的范围内。
气态的原料连同运载气体、例如氢气通过进气机构11被输入到处理室8内。在处理室8内，在被加热装置10加热的基座9上存在一个或多个基板1，所述基板被晶核层3覆层。以第V族原料相对于III族原料的在10至5000范围内的摩尔比例将气态的前体、尤其TMAl和NH3通过进气机构11输入到处理室8内。气态原料的流量如此设置，使得AlN晶核层3的生长率位于0.01至2μm/h之间的范围内。
在本发明中重要的是，在晶核层3沉积过程中，但至少在晶核层3沉积开始时，将实现弱n传导的气态原料输入到处理室8内。这种第三气态原料优选是硅烷或锗，其具有SinH2n+2或GenH2n+2的结构式。
III-V族晶核层的附加的n掺杂明显降低了前述的扩散效应并且降低了衰减，如图3示例性地所示地：
a)未掺杂的AlN，
b)以1x1018cm-3掺杂的AlN，或者
c)以2x1017cm-3掺杂的AlN
d)以5x1017cm-3掺杂的AlN。
图3示出在掺杂物浓度为2x1017cm-3和5x1017cm-3时衰减的显著的降低，然而在更高的1x1018cm-3的掺杂时衰减重新增强并且大约是未掺杂AlN的数值。
结果显示，在更高的掺杂物浓度下显然无法看到希望的效果。
在晶核层3上以已知的方式首先沉积出GaN缓冲层4，并且随后沉积出活性的AlGaN层6，从而在缓冲层4和活性层6之间的界面5上构造出二维的电子气体。附加地，以已知的方式制造出门极触点、源级触点和漏极触点。
上述实施方式用于阐述整体包含在申请中的发明，该发明至少通过以下特征组合分别独立地扩展了现有技术，其中，两个、多个或所有的技术特征组合也可以相互组合，即：
一种方法，其特征在于，至少在晶核层3的沉积开始时，连同第一和第二气态原料一起将含有第IV主族元素的第三气态原料输入到处理室8中。
一种方法，其特征在于，在所述处理室8中所述第三气态原料的分压比第一和第二气态原料的分压至少小10倍，和/或所述第三气态原料在所述处理室8中的分压或者质量流量如此选择，使得所述第三气态原料实现最多1x1018cm-3的掺杂量。
一种方法，其特征在于，所述处理温度在800℃至1200℃的范围、优选在950℃至1050℃的范围内。
一种方法，其特征在于，所述晶核层3在30至300mbar的总压力下被沉积。
一种方法，其特征在于，所述第二气态原料相对于第一气态原料的摩尔比例在10至5000的范围内。
一种方法，其特征在于，所述第三气态原料的加入导致晶核层的n掺杂量在1x1017cm-3至1x1018cm-3的范围内。
一种方法，其特征在于，所述基板1由硅或锗构成，和/或所述第三气态原料是SinH2n+2或GenH2n+2或者其它的含硅或锗的气态原料。
一种方法，其特征在于，第III主族元素是铝，和/或所述第一气态原料是TMAl。
一种方法，其特征在于，第V主族元素是氮，和/或所述第二气态原料是NH3。
一种方法，其特征在于，所述晶核层3沉积尤其由AlN构成的缓冲层4，并且在所述缓冲层4上沉积出活性层6，使得在所述活性层6和缓冲层4之间的界面5上构成二维的电子气体，和/或所述第三气态原料的输入减小了高频衰减的衰减值。
一种层序列，其特征在于，在由第IV主族元素构成的基板1的表面2上沉积出由第IV主族和第V主族元素构成的晶核层3，所述晶核层至少在其与所述表面2直接邻接的区域中掺杂有第IV主族元素。
一种层序列，其特征在于，在所述晶核层3上沉积至少一个缓冲层4，又在所述缓冲层上沉积活性层6，从而在所述缓冲层4和活性层6之间的界面5上构成二维的电子气体。
所有公开的特征(本身及其相互组合)都有发明意义或发明价值。在本申请的公开文件中，所属/附属的优先权文本(在先申请文件)的公开内容也被完全包括在内，为此也将该优先权文本中的特征纳入本申请中。本发明也涉及一些设计形式，其中，在前述说明书中提到的个别技术特征不能实现，尤其就此可被识别出对于各个应用目的是不必要的或者通过其它技术上可同样实现的器件可被替代。
附图标记列表
1 基板
2 表面
3 晶核层
4 缓冲层
5 界面
6 活性层
7 反应器
8 处理室
9 基座
10 加热装置
11 进气机构

Claims (12)

1.一种直接在基板(1)的表面(2)上沉积晶核层(3)的方法，所述晶核层由第III主族和第V主族元素构成，所述基板由第IV主族元素构成，其中，连同含有第III主族元素的第一气态原料一起将含有第V主族元素的第二气态原料在大于500℃的处理温度下置入包含基板(1)的处理室(8)中，其中，至少在晶核层(3)的沉积开始时，将含有第IV主族元素的第三气态原料连同第一和第二气态原料一起输入到处理室(8)中，其中，在所述晶核层(3)上沉积缓冲层(4)，并且在所述缓冲层(4)上沉积活性层(6)，使得在所述活性层(6)和缓冲层(4)之间的界面(5)上构成二维的电子气体，其特征在于，在晶核层的沉积开始时所述第三气态原料在所述处理室(8)中的分压或者质量流量选择为，使得所述第三气态原料实现大于2x1017cm-3并且小于5x1017cm-3的掺杂量并且实现高频衰减的减小。
2.按照权利要求1所述的方法，其特征在于，所述处理温度在800℃至1200℃的范围内。
3.按照权利要求2所述的方法，其特征在于，所述处理温度在950℃至1050℃的范围内。
4.按照权利要求1或2所述的方法，其特征在于，所述第二气态原料相对于第一气态原料的摩尔比例在10至5000的范围内。
5.按照权利要求1所述的方法，其特征在于，所述第三气态原料的加入导致晶核层的n掺杂量在1x1017cm-3至1x1018cm-3的范围内。
6.一种直接在基板(1)的表面(2)上沉积晶核层(3)的方法，所述晶核层由第III主族和第V主族元素构成，所述基板由第IV主族元素构成，其中，连同含有第III主族元素的第一气态原料一起将含有第V主族元素的第二气态原料在大于500℃的处理温度下置入包含基板(1)的处理室(8)中，其中，至少在晶核层(3)的沉积开始时，将含有第IV主族元素的第三气态原料连同第一和第二气态原料一起输入到处理室(8)中，其特征在于，在晶核层的沉积开始时所述第三气态原料在所述处理室(8)中的分压或者质量流量选择为，使得所述第三气态原料实现大于2x1017cm-3并且小于5x1017cm-3的掺杂量，其中，所述晶核层(3)在30至300mbar的总压力下被沉积。
7.按照权利要求1或6所述的方法，其特征在于，所述基板(1)由硅或锗构成，和/或所述第三气态原料是SinH2n+2或GenH2n+2或者其它的含硅或锗的气态原料。
8.按照权利要求1或6所述的方法，其特征在于，第III主族元素是铝，和/或所述第一气态原料是TMAl。
9.按照权利要求1或6所述的方法，其特征在于，第V主族元素是氮，和/或所述第二气态原料是NH3。
10.按照权利要求6所述的方法，其特征在于，在所述晶核层(3)上沉积由AlN构成的缓冲层(4)，并且在所述缓冲层(4)上沉积活性层(6)，使得在所述活性层(6)和缓冲层(4)之间的界面(5)上构成二维的电子气体，和/或所述第三气态原料的输入减小了高频衰减的衰减值。
11.一种根据权利要求1或6所述的方法制备的层序列，其特征在于，在由第IV主族元素构成的基板(1)的表面(2)上沉积出由第IV主族和第V主族元素构成的晶核层(3)，所述晶核层至少在其与所述表面(2)直接邻接的区域中被掺杂有第IV主族元素。
12.按照权利要求11所述的层序列，其特征在于，在所述晶核层(3)上沉积至少一个缓冲层(4)，又在所述缓冲层上沉积活性层(6)，从而在所述缓冲层(4)和活性层(6)之间的边界面(5)上构成二维的电子气体。
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DE102018108604A1 (de) 2019-10-17
JP2021520643A (ja) 2021-08-19
JP7441794B2 (ja) 2024-03-01
WO2019197433A1 (de) 2019-10-17
TW201945573A (zh) 2019-12-01
US11887848B2 (en) 2024-01-30
KR102583794B1 (ko) 2023-09-27

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