CN112133739A - 高电子迁移率晶体管和调整二维电子气体电子密度的方法 - Google Patents

高电子迁移率晶体管和调整二维电子气体电子密度的方法 Download PDF

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CN112133739A
CN112133739A CN201910553143.8A CN201910553143A CN112133739A CN 112133739 A CN112133739 A CN 112133739A CN 201910553143 A CN201910553143 A CN 201910553143A CN 112133739 A CN112133739 A CN 112133739A
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gallium nitride
nitride layer
aluminum gallium
silicon oxide
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李凯霖
李志成
陈威任
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United Microelectronics Corp
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United Microelectronics Corp
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Priority to US16/513,699 priority patent/US11239327B2/en
Priority to EP20168437.0A priority patent/EP3758069A3/en
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Abstract

本发明公开一种高电子迁移率晶体管和调整二维电子气体电子密度的方法，其中高电子迁移率晶体管包含一氮化镓层，一氮化铝镓层设置于氮化镓层上，氮化铝镓层具有一伸张应力，一源极电极以及一漏极电极设置于氮化铝镓层之上，一栅极电极设置于源极电极与漏极电极之间的氮化铝镓层上，至少一个氧化硅层埋入于氮化铝镓层中，其中氧化硅层是利用流动式化学气相沉积所制作，氧化硅层提升氮化铝镓层中的伸张应力。

Description

高电子迁移率晶体管和调整二维电子气体电子密度的方法
技术领域
本发明涉及一种高电子迁移率晶体管，特别是涉及具有氧化硅层或应力材料层埋入于氮化铝镓层的高电子迁移率晶体管。
背景技术
III-V族半导体化合物由于其半导体特性而可应用于形成许多种类的集成电路装置，例如高功率场效晶体管、高频晶体管或高电子迁移率晶体管(high electron mobilitytransistor，HEMT)。在高电子迁移率晶体管中，两种不同能带隙(band-gap)的半导体材料是结合而于结(junction)形成异质结(heterojunction)而为载流子提供通道。近年来，氮化镓系列的材料由于拥有较宽能隙与饱和速率高的特点而适合应用于高功率与高频率产品。氮化镓系列的高电子迁移率晶体管由材料本身的压电效应产生二维电子气(two-dimensional electron gas,2DEG)，相较于传统晶体管，高电子迁移率晶体管的电子速度及密度均较高，故可用以增加切换速度。
然而随着电子产品升级，因此需增加高电子迁移率晶体管的电子速度及密度。此外由于高电子迁移率晶体管需要在高电压下操作，因此需要增加高电子迁移率晶体管承受高电压的能力。
发明内容
有鉴于此，本发明提供了一种调整二维电子气体的电子密度的方法，以增加高电子迁移率晶体管的电子密度以及提升高电子迁移率晶体管承受高电压的能力。
根据本发明的一优选实施例，一种高电子迁移率晶体管包含一氮化镓层，一氮化铝镓层设置于氮化镓层上，氮化铝镓层具有一伸张应力，一源极电极以及一漏极电极设置于氮化铝镓层之上，一栅极电极，设置于源极电极与漏极电极之间的氮化铝镓层上，至少一个氧化硅层埋入于氮化铝镓层中，其中氧化硅层是利用流动式化学气相沉积所制作，氧化硅层提升氮化铝镓层中的伸张应力。
根据本发明的一优选实施例，一种高电子迁移率晶体管，包含一氮化镓层，一氮化铝镓层设置于氮化镓层上，氮化铝镓层具有一伸张应力，一源极电极以及一漏极电极设置于氮化铝镓层之上，一栅极电极设置于源极电极与漏极电极之间的氮化铝镓层上以及至少一个应力材料层埋入于氮化铝镓层中，应力材料层降低氮化铝镓层中的伸张应力。
根据本发明的一优选实施例，一种调整二维电子气体的电子密度的方法，包含首先提供一氮化镓层和一氮化铝镓层，其中氮化铝镓层接触氮化镓层，一源极电极、一漏极电极和一栅极电极设置于氮化铝镓层之上并且氮化铝镓层具有一伸张应力，在氮化镓层内具有二维电子气体，然后进行以下步骤A或步骤B，步骤A包含形成至少一个氧化硅层埋入于氮化铝镓层中，其中氧化硅层是利用流动式化学气相沉积所制作，氧化硅层提升氮化铝镓层中的伸张应力并且增加二维电子气体的电子密度，步骤B包含形成至少一个应力材料层埋入于氮化铝镓层中，应力材料层降低氮化铝镓层中的伸张应力，并且降低二维电子气体的电子密度。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合所附的附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1至图4为本发明的第一优选实施例所绘示的调整二维电子气体的电子密度的方法的示意图；
图5至图6为本发明的第三优选实施例所绘示的调整二维电子气体的电子密度的方法的示意图；
图7至图9为本发明的其它优选实施例所绘示的高电子迁移率晶体管的示意图；
图10为氧化硅层的压缩应力和应力材料层的伸张应力的示意图。
主要元件符号说明
10 氮化镓层 12 氮化铝镓层
14 二维电子气 16 沟槽
18 流动式化学气相沉积 20 氧化硅层
22 加热制作工艺 24 源极电极
26 栅极电极 28 漏极电极
30 P型氮化镓层 32 氟掺杂区
100 高电子迁移率晶体管 116 沟槽
118 化学气相沉积制作工 120 应力材料层
艺
200 高电子迁移率晶体管 300 高电子迁移率晶体管
400 高电子迁移率晶体管 500 高电子迁移率晶体管
A 距离 C1 压缩应力
C2 压缩应力 C3 压缩应力
D1 厚度 D2 厚度
G 间距 T1 伸张应力
T2 伸张应力 T3 伸张应力
W1 宽度 W2 宽度
具体实施方式
图1至图4为根据本发明的第一优选实施例所绘示的调整二维电子气体的电子密度的方法。如图1所示，首先提供一氮化镓层(gallium nitride，GaN)10，接着形成一氮化铝镓层(aluminum gallium nitride，AlxGa1-xN)12覆盖并接触氮化镓层10，氮化镓层10和氮化铝镓层12都可以使用外延制作工艺形成。因为氮化铝镓层12和氮化镓层10的两者的晶格大小不同，所以在氮化铝镓层12和氮化镓层10接触后氮化铝镓层12中会形成有伸张应力(tensile stress)T1，而在氮化镓层10中会形成有压缩应力(compressive stress)C1。此外伸张应力T1和压缩应力C1在氮化镓层10和氮化铝镓层12的接触面造成了压电效应(piezoelectricity)，进而在氮化镓层10中形成二维电子气14。
如图2所示，形成至少一沟槽16在氮化铝镓层12中，视情况需要可以形成多个沟槽16，在本发明的实施例中以形成多个沟槽16为例。接着，进行一流动式化学气相沉积(flowable chemical vapor deposition,FCVD)18，以形成一氧化硅层20填满沟槽16并且覆盖氮化铝镓层12。如图3所示，进行一加热制作工艺22固化氧化硅层20。如图4所示，平坦化氧化硅层20，例如利用一化学研磨制作工艺使得氧化硅层20的上表面和氮化铝镓层12的上表面切齐。接着形成一源极电极24、一栅极电极26和一漏极电极28在氮化铝镓层12上，栅极电极26位于源极电极24和漏极电极28之间。至此完成一高电子迁移率晶体管100。
图10绘示的是氧化硅层的压缩应力和应力材料层的伸张应力的示意图，在图10中绘示了氮化镓层10、氮化铝镓层12、氧化硅层20和应力材料层120，并且省略其它元件。
请同时参阅图4和图10，由于利用流动式化学气相沉积的方式所形成的氧化硅层20具有压缩应力C3，所以会造成周围的氮化铝镓层12承受伸张应力T2，也就是说，在形成氧化硅层20在氮化铝镓层12中后，氮化铝镓层12的伸张应力变成伸张应力T1加上伸张应力T2。因为氮化铝镓层12的伸张应力上升，进而提升了压电效应，所以增加了二维电子气14的电子密度，而高电子迁移率晶体管100的操作效能也因此提升。至此完成本发明调整二维电子气的电子密度的方法。
图4为根据本发明的第二优选实施例所绘示的高电子迁移率晶体管。高电子迁移率晶体管100为一常开启(normally-on)高电子迁移率晶体管，高电子迁移率晶体管100包含一氮化镓层10，一氮化铝镓层12设置于氮化镓层10上，氮化铝镓层12具有一伸张应力T1，氮化镓层10具有一压缩应力C1，一源极电极24以及漏极电极28设置于氮化铝镓层12之上，一栅极电极26设置于源极电极24与漏极电极28之间的氮化铝镓层12上，至少一个氧化硅20层埋入于氮化铝镓层12中，氧化硅层20厚度D1不大于氮化铝镓层12的厚度。此外，氧化硅层20的上表面和氮化铝镓层12的上表面切齐。氧化硅层20可以设置在源极电极24正下方的氮化铝镓层12内、漏极电极28正下方的氮化铝镓层12内或源极电极24正下方和漏极电极28正下方之间的氮化铝镓层12内，在图4中以多个氧化硅层20分别从源极电极24正下方的氮化铝镓层12到漏极电极28正下方之间的氮化铝镓层12内都有设置。
值得注意的是：氧化硅层20是利用流动式化学气相沉积所制作，所以氧化硅层20本身具有压缩应力，因此将氧化硅层20埋入在氮化铝镓层12后，可以提升氮化铝镓层12中的伸张应力。此外，根据本发明的优选实施例，氧化硅层20的高宽比为0.5至5之间，相邻的氧化硅层20之间的间距G为氧化硅层20宽度W1的0.2至200倍之间，举例而言氧化硅层20厚度D1约50纳米，宽度W1约10至100纳米，相邻的氧化硅层20之间的间距G为20至2000纳米。但是根据高电子迁移率晶体管100的大小改变或对二维电子气14的电子密度要求改变时，氧化硅层20的大小、间距和厚度也可以调整。
图5至图6为根据本发明的第三优选实施例所绘示的调整二维电子气体的电子密度的方法，其中具有相同功能和位置的元件将给予第一优选实施例中的标号。
如图1所示，提供一氮化镓层10，接着形成一氮化铝镓层12覆盖并接触氮化镓层10。如图5所示，在氮化铝镓层12形成至少一沟槽116，在图5中以多个沟槽116为例，然后进行一化学气相沉积制作工艺118以形成一应力材料层120填满沟槽。应力材料层120可以为氧化硅、氮化硅等可以承载应力的材料。如图6所示，平坦化应力材料层120，例如利用一化学研磨制作工艺使得应力材料层120的上表面和氮化铝镓层12的上表面切齐，最后形成一源极电极24、一栅极电极26和一漏极电极28在氮化铝镓层12上，栅极电极26位于源极电极24和漏极电极28之间。至此完成高电子迁移率晶体管200。
请参阅图6和图10，值得注意的是：应力材料层120本身具有伸张应力T3，所以会给予周围的氮化铝镓层12压缩应力C2，进而降低氮化铝镓层12原本的伸张应力T1，也就是说氮化铝镓层12的伸张应力变成伸张应力T1减去压缩应力C2，因此压电效应会减少，造成二维电子气14的电子密度下降，至此完成本发明调整二维电子气的电子密度的方法。
此外，因为高电子迁移率晶体管200系在高压下操作，所以在栅极电极26尖端会有突然大量放电的现象，会损坏高电子迁移率晶体管200，而本发明外加了应力材料层120造成二维电子气14的电子密度下降，电子密度下降相当于增加了电阻，如此即使高电子迁移率晶体管200被施加了高电压，电压也会缓慢下降，不会有突然高电流导通的情况。
图6为根据本发明的第四优选实施例所绘示的高电子迁移率晶体管，其中具有相同功能和位置的元件将给予第一优选实施例中的标号。高电子迁移率晶体管200为一常开启高电子迁移率晶体管，其包含一氮化镓层10，一氮化铝镓层12设置于氮化镓层10上，氮化铝镓层12具有一伸张应力T1，氮化镓层10具有一压缩应力C1，一源极电极24以及漏极电极28设置于氮化铝镓层12之上，一栅极电极26设置于源极电极24与漏极电极28之间的氮化铝镓层12上，至少一个应力材料层120埋入于氮化铝镓层12中，应力材料层120降低氮化铝镓层12中的伸张应力T1。应力材料层120的厚度D2小于氮化铝镓层12的厚度，此外，应力材料层120的上表面和氮化铝镓层12的上表面切齐。应力材料层120可以设置在栅极电极26正下方的氮化铝镓层12内、漏极电极28正下方的氮化铝镓层12内或栅极电极26正下方和漏极电极24正下方之间的氮化铝镓层12内，应力材料层120较佳离栅极电极26较远离漏极电极28较近。在图4中以多个应力材料层120设置在离漏极电极28较近的氮化铝镓层12内为例。
根据本发明的优选实施例，栅极电极26和漏极电极28的距离A为应力材料层116的厚度D2的233倍以上，栅极电极26和漏极电极28的距离A和应力材料层116的宽度W2比值介于14至140之间，举例而言，当栅极电极26和漏极电极28的距离A约7微米时，各个应力材料层116的厚度D2小于30纳米，宽度W2约50至500纳米。但是根据高电子迁移率晶体管200的大小改变或施加在高电子迁移率晶体管200上的电压改变时，应力材料层120的大小、间距和厚度也可以调整。
图7至图9为根据本发明的其它优选实施例所绘示的高电子迁移率晶体管，其中具有相同功能和位置的元件将给予第一优选实施例和第三优选实施例中的标号。本发明前文所述的调整二维电子气体的电子密度的方式，包含增加二维电子气体的电子密度和降低二维电子气体的电子密度的方式，不仅可以使用在常开启的高电子迁移率晶体管，也适用于常关闭(normally-off)的高电子迁移率晶体管。
如图7所示，高电子迁移率晶体管300为常关闭型，其和图4的高电子迁移率晶体管100差别在于高电子迁移率晶体管300多了P型氮化镓层30。此外这种常关闭型高电子迁移率晶体管，除了如本实施例中使用氧化硅层20增加二维电子气体14的电子密度，也可以使用如图6所示的应力材料层120来降低二维电子气体14的电子密度。
如图8所示，高电子迁移率晶体管400为常关闭型，其和图6的高电子迁移率晶体管200差别在于高电子迁移率晶体管400多了氟掺杂区32在氮化铝镓层12中。此外这种常关闭型高电子迁移率晶体管，除了如本实施例中使用应力材料层120降低二维电子气体14的电子密度，也可以使用如图4所示的氧化硅层20来增加二维电子气体14的电子密度。
如图9所示，高电子迁移率晶体管500为常关闭型，其和图6的高电子迁移率晶体管200差别在于高电子迁移率晶体管500的栅极电极26埋入于氮化铝镓层12中。此外这种常关闭型高电子迁移率晶体管，除了如本实施例中使用应力材料层120降低二维电子气体14的电子密度，也可以使用如图4所示的氧化硅层20来增加二维电子气体14的电子密度。
本发明通过将流动式化学气相沉积所制作的氧化硅埋入于氮化铝镓中，以增加二维电子气的电子密度，进而提升高电子迁移率晶体管的操作效能。此外本发明通过将应力材料层埋入于氮化铝镓中，以降低二维电子气的电子密度，使得进而提升高电子迁移率晶体管的承载高压的能力。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种高电子迁移率晶体管，其特征在于，包含：
氮化镓层；
氮化铝镓层，设置于该氮化镓层上，该氮化铝镓层具有一伸张应力；
源极电极以及漏极电极，设置于该氮化铝镓层之上；
栅极电极，设置于该源极电极与该漏极电极之间的该氮化铝镓层上；以及
至少一个氧化硅层埋入于该氮化铝镓层中，其中该氧化硅层是利用流动式化学气相沉积所制作，该氧化硅层提升该氮化铝镓层中的该伸张应力。
2.如权利要求1所述的高电子迁移率晶体管，其中该氧化硅层的上表面和该氮化铝镓层的上表面切齐。
3.如权利要求1所述的高电子迁移率晶体管，其中该氧化硅层位于该源极电极正下方的该氮化铝镓层内、该漏极电极正下方的该氮化铝镓层内或该源极电极正下方和该漏极电极正下方之间的该氮化铝镓层内。
4.如权利要求1所述的高电子迁移率晶体管，其中该高电子迁移率晶体管另包含多个该氧化硅层埋入于该氮化铝镓层中。
5.如权利要求1所述的高电子迁移率晶体管，其中该氧化硅层具有收缩应力。
6.如权利要求1所述的高电子迁移率晶体管，其中该氧化硅层的厚度不大于该氮化铝镓层的厚度。
7.一种高电子迁移率晶体管，其特征在于，包含：
氮化镓层；
氮化铝镓层，设置于该氮化镓层上，该氮化铝镓层具有一伸张应力；
源极电极以及漏极电极，设置于该氮化铝镓层之上；
栅极电极，设置于该源极电极与该漏极电极之间的该氮化铝镓层上；以及
至少一个应力材料层埋入于该氮化铝镓层中，该应力材料层降低该氮化铝镓层中的该伸张应力。
8.如权利要求7所述的高电子迁移率晶体管，其中该应力材料层的上表面和该氮化铝镓层的上表面切齐。
9.如权利要求7所述的高电子迁移率晶体管，其中该应力材料层位于该栅极电极正下方的该氮化铝镓层内、该漏极电极正下方的该氮化铝镓层内或该栅极电极正下方和该漏极电极正下方之间的该氮化铝镓层内。
10.如权利要求9所述的高电子迁移率晶体管，其中该应力材料层离该栅极电极较远，离该漏极电极较近。
11.如权利要求7所述的高电子迁移率晶体管，其中该高电子迁移率晶体管另包含多个该应力材料层埋入于该氮化铝镓层中。
12.如权利要求7所述的高电子迁移率晶体管，其中该应力材料层具有伸张应力。
13.如权利要求7所述的高电子迁移率晶体管，其中该应力材料层为氧化硅或氮化硅。
14.如权利要求7所述的高电子迁移率晶体管，其中该应力材料层为利用化学气相沉积制作工艺所制作的氧化硅。
15.如权利要求7所述的高电子迁移率晶体管，其中该应力材料层的厚度小于该氮化铝镓层的厚度。
16.一种调整二维电子气体的电子密度的方法，包含：
提供氮化镓层和氮化铝镓层，其中该氮化铝镓层接触该氮化镓层，源极电极、漏极电极和栅极电极，设置于该氮化铝镓层之上并且该氮化铝镓层具有一伸张应力，在该氮化镓层内具有二维电子气体；以及
进行以下步骤A和步骤B其中之一的步骤：
步骤A：形成至少一个氧化硅层埋入于该氮化铝镓层中，其中该氧化硅层是利用流动式化学气相沉积所制作，该氧化硅层提升该氮化铝镓层中的该伸张应力并且增加该二维电子气体的电子密度；以及
步骤B：形成至少一个应力材料层埋入于该氮化铝镓层中，该应力材料层降低该氮化铝镓层中的该伸张应力，并且降低该二维电子气体的电子密度。
17.如权利要求16所述的调整二维电子气体的电子密度的方法，其中该氧化硅层位于该源极电极正下方的该氮化铝镓层内、该漏极电极正下方的该氮化铝镓层内或该源极电极正下方和该漏极电极正下方之间的该氮化铝镓层内。
18.如权利要求16所述的调整二维电子气体的电子密度的方法，其中该应力材料层位于该栅极电极正下方的该氮化铝镓层内、该漏极电极正下方的该氮化铝镓层内或该栅极电极正下方和该漏极电极正下方之间的该氮化铝镓层内。
19.如权利要求16所述的调整二维电子气体的电子密度的方法，其中该氧化硅层形成方法包含：
形成沟槽于该氮化铝镓层；
进行流动式化学气相沉积制作工艺以形成该氧化硅层填入该沟槽；
进行加热制作工艺固化该氧化硅层；
平坦化该氧化硅层，使得该氧化硅层的上表面和该氮化铝镓层的上表面切齐。
20.如权利要求16所述的调整二维电子气体的电子密度的方法，其中该应力材料层形成方法包含：
形成沟槽于该氮化铝镓层；
进行化学气相沉积制作工艺以形成该应力材料层填入该沟槽；
平坦化该应力材料层，使得该应力材料层的上表面和该氮化铝镓层的上表面切齐。
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