CN112216741A - 高电子迁移率晶体管的绝缘结构以及其制作方法 - Google Patents

高电子迁移率晶体管的绝缘结构以及其制作方法 Download PDF

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CN112216741A
CN112216741A CN201910618716.0A CN201910618716A CN112216741A CN 112216741 A CN112216741 A CN 112216741A CN 201910618716 A CN201910618716 A CN 201910618716A CN 112216741 A CN112216741 A CN 112216741A
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gallium nitride
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CN112216741B (zh
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张峻铭
廖文荣
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United Microelectronics Corp
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Abstract

本发明公开一种高电子迁移率晶体管(high electron mobility transistor,HEMT)的绝缘结构以及其制作方法，其中该高电子迁移率晶体管的绝缘结构，包含一氮化镓层，一氮化铝镓层，位于该氮化镓层上，一绝缘掺杂区，位于该氮化镓层与该氮化铝镓层中，以及两侧壁绝缘结构，分别位于该绝缘掺杂区的两侧。

Description

高电子迁移率晶体管的绝缘结构以及其制作方法
技术领域
本发明涉及一种高电子迁移率晶体管的绝缘结构及其制作方法。
背景技术
III-V族半导体化合物由于其半导体特性而可应用于形成许多种类的集成电路装置，例如高功率场效晶体管、高频晶体管或高电子迁移率晶体管(high electron mobilitytransistor，HEMT)。在高电子迁移率晶体管中，两种不同能带隙(band-gap)的半导体材料是结合而于结(junction)形成异质结(heterojunction)而为载流子提供通道。近年来，氮化镓系列的材料由于拥有较宽带隙与饱和速率高的特点而适合应用于高功率与高频率产品。氮化镓系列的高电子迁移率晶体管由材料本身的压电效应产生二维电子气(two-dimensional electron gas,2DEG)，相较于传统晶体管，高电子迁移率晶体管的电子速度及密度均较高，故可用以增加切换速度。
以氮化镓基材料(GaN-based materials)为基础的高电子迁移率晶体管具有于电子、机械以及化学等特性上的众多优点，例如宽带隙、高击穿电压、高电子迁移率、大弹性模数(elastic modulus)、高压电与压阻系数(high piezoelectric and piezoresistivecoefficients)等与化学钝性。上述优点使氮化镓基材料可用于如高亮度发光二极管、功率开关元件、调节器、电池保护器、面板显示驱动器、通讯元件等应用的元件的制作。
发明内容
本发明提供一种高电子迁移率晶体管(high electron mobility transistor,HEMT)的绝缘结构，包含一氮化镓层，一氮化铝镓层，位于该氮化镓层上，一绝缘掺杂区，位于该氮化镓层与该氮化铝镓层中，以及两侧壁绝缘结构，分别位于该绝缘掺杂区的两侧。
本发明另提供一种形成高电子迁移率晶体管(high electron mobilitytransistor,HEMT)的绝缘结构的方法，包含：首先，形成一氮化镓层，并形成一氮化铝镓层于该氮化镓层上，然后进行一掺杂步骤，以掺杂多个离子于该氮化镓层与该氮化铝镓层中，并且在该氮化镓层与该氮化铝镓层中形成一绝缘掺杂区，接着形成两凹槽于该绝缘掺杂区的两侧，以及填入一绝缘层于该两凹槽中，并形成两侧壁绝缘结构分别位于该绝缘掺杂区的两侧。
本发明在绝缘掺杂区完成后，额外在绝缘掺杂区两侧形成两侧壁绝缘结构。通过两侧壁绝缘结构设置在绝缘掺杂区的两侧，即使后续对半导体元件进行加热步骤，活化的离子由于受到侧壁绝缘结构的阻挡，因此不容易逸散至别处，确保绝缘掺杂区的绝缘效果。
附图说明
图1至图8为本发明一实施例制作一高电子迁移率晶体管的绝缘结构的方法示意图，其中：
图2是图1之后的步骤的示意图；
图3是图5之后的步骤的示意图；
图4是图3之后的步骤的示意图；
图5是图4之后的步骤的示意图；
图6是图5之后的步骤的示意图；
图7是图6之后的步骤的示意图；以及
图8是图7之后的步骤的示意图。
主要元件符号说明
10 基底
12 缓冲层
14 氮化镓层
16 氮化铝镓层
18 二维电子气层
20 图案化光致抗蚀剂
22 开口
24 绝缘掺杂区
26 第二图案化光致抗蚀剂
28 开口
30 凹槽
32 绝缘层
34 侧壁绝缘结构
P1 掺杂步骤
E1 步骤
E2 蚀刻步骤
E3 蚀刻步骤
具体实施方式
为使熟悉本发明所属技术领域的一般技术者能更进一步了解本发明，下文特列举本发明的优选实施例，并配合所附的附图，详细说明本发明的构成内容及所欲达成的功效。
为了方便说明，本发明的各附图仅为示意以更容易了解本发明，其详细的比例可依照设计的需求进行调整。在文中所描述对于图形中相对元件的上下关系，在本领域的人都应能理解其是指物件的相对位置而言，因此都可以翻转而呈现相同的构件，此都应同属本说明书所揭露的范围，在此容先叙明。
请参照图1至图8，图1至图8为本发明一实施例制作一高电子迁移率晶体管的绝缘结构的方法示意图。其中，图2是图1之后的步骤的示意图；图3是图2之后的步骤的示意图；图4是图3之后的步骤的示意图；图5是图4之后的步骤的示意图；图6是图5之后的步骤的示意图；图7是图6之后的步骤的示意图；以及图8是图7之后的步骤的示意图。如图1所示，首先提供一基底10，例如一由硅、碳化硅或氧化铝(或可称蓝宝石)所构成的基底，其中基底10可为单层基底、多层基底、梯度基底或上述的组合。依据本发明其他实施例基底10又可包含一硅覆绝缘(silicon-on-insulator,SOI)基底。
接着，在基底10表面形成一缓冲层12，缓冲层12主要作用为帮助后续形成的氮化镓层可以更容易被形成于基底10上。举例来说，若基底10为蓝宝石(氧化铝)基底，而氧化铝与氮化镓的晶格常数差距较大，因此需要形成一缓冲层12设置在基底10与氮化镓层之间，缓冲层12的晶格常数介于基底10的晶格常数与氮化镓的晶格常数之间。在本实施例中，缓冲层12例如为氮化铝(AlN)，但不限于此。
然后于缓冲层12表面形成一氮化镓层14，其厚度可介于0.5微米至10微米之间。在一实施利中，可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemical vapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phaseepitaxy,HVPE)制作工艺或上述组合于缓冲层12上形成氮化镓层14。
接着形成一氮化铝镓层16于氮化镓层14表面。其中氮化铝镓层16较佳包含一由外延成长制作工艺所形成之外延层。如同上述形成氮化镓层14的方式，可利用分子束外延制作工艺(molecular-beam epitaxy,MBE)、有机金属气相沉积(metal organic chemicalvapor deposition,MOCVD)制作工艺、化学气相沉积(chemical vapor deposition,CVD)制作工艺、氢化物气相外延(hydride vapor phase epitaxy,HVPE)制作工艺或上述组合于氮化镓层14上形成氮化铝镓层16。
值得注意的是，在形成氮化铝镓层16于氮化镓层14表面之后，由于氮化镓层与氮化铝镓层的材料能带间隙(band gap)不同之故，氮化镓层与氮化铝镓层的界面数较佳形成异质结(heterojunction)。异质结处的能带弯曲，导带(conduction band)弯曲深处形成量子阱(quantum well)，将压电效应(piezoelectricity)所产生的电子约束于量子阱中，因此在氮化镓层与氮化铝镓层的界面处形成通道区或二维电子气(two-dimensionalelectron gas,2DEG)层18，进而形成导通电流。
在上述的结构中，若要形成绝缘层，其中一方法就是对氮化镓层以及氮化铝镓层进行掺杂离子步骤，例如掺杂氦(He)、磷(P)、氩(Ar)、氮(N)、氧(O)或砷(As)离子。在离子掺杂步骤进行后，二维电子气层会被破坏，进而使得上述导通电流被切断，也就是说，被离子掺杂的区域，将会形成等同于绝缘层的区域。
然而，申请人发现，以掺杂离子的方式形成绝缘区域将会有一风险，那就是在后续步骤中，例如形成晶体管的步骤过程中，若使用到加热步骤，将可能会让被掺杂在氮化镓层与氮化铝镓层内的离子活化并且可能会溢散出原本掺杂的区域，进而导致该区域的绝缘效果消失。换句话说，在利用离子掺杂步骤形成绝缘区域后，若后续又进行加热步骤，将可能导致该绝缘区域消失或是降低其绝缘能力，进而影响高电子迁移率晶体管的良率。
为了避免上述问题，如图2至图8所示，其绘示本发明制作高电子迁移率晶体管(high electron mobility transistor,HEMT)的绝缘结构的流程示意图。其延续图1所示的结构继续制作高电子迁移率晶体管的绝缘结构。首先，如图2所示，形成一图案化光致抗蚀剂20于氮化铝镓层16的表面，其中图案化光致抗蚀剂包含有一开口22，开口22的位置大致对应后续需要形成绝缘区域的位置。此外，此处开口22的宽度会略大于后续实际形成的绝缘区域的宽度。换句话说，在此步骤中，不需要形成绝缘区域的部分将会被图案化光致抗蚀剂20所覆盖。
接下来如图3所示，进行一掺杂步骤P1，例如掺杂氦(He)、磷(P)、氩(Ar)、氮(N)、氧(O)或砷(As)离子至氮化铝镓层16、二维电子气层18、氮化镓层14中，在一些实施例中，若掺杂离子的深度足够，也可能会掺杂到部分的缓冲层12内。在此定义被掺杂离子的区域为绝缘掺杂区24。在绝缘掺杂区24内，由于氮化铝镓层16与氮化镓层14都被掺杂有离子，因此两者之间的二维电子气层18被破坏而消失，如上所述，二维电子气层18存在可形成导通电流，因此二维电子气层18若在绝缘掺杂区24中消失，代表绝缘掺杂区24形成一绝缘的区域。也就是说，在绝缘掺杂区24内不包含有二维电子气层18。
如图4所示，进行一步骤E1以移除图案化光致抗蚀剂20，其中移除图案化光致抗蚀剂20的步骤E1包括但不限于灰化、光刻、湿/干蚀刻、平坦化(例如，化学机械抛光CMP或反应离子蚀刻RIE回蚀刻)，本发明并不以此为限。由于移除光致抗蚀剂的方法属于本领域的已知技术，在此不多加赘述。
如图5所示，形成一第二图案化光致抗蚀剂26于氮化铝镓层16的表面，其中图案化光致抗蚀剂26包含有多个开口28。此处所述的第二图案化光致抗蚀剂26可能包含与上述图案化光致抗蚀剂20相同或不同的材料，但不限于此。值得注意的是，开口28的位置对应各绝缘掺杂区24的两侧边缘区域。也就是说，各绝缘掺杂区24靠近两侧边缘的部分区域被曝露，而除此之外，绝缘掺杂区24的中央部分或是其余非绝缘掺杂区24的区域都被第二图案化光致抗蚀剂26所覆盖。
如图6所示，进行一蚀刻步骤E2，利用第二图案化光致抗蚀剂26当作遮罩，移除绝缘掺杂区24内部分的氮化铝镓层16以及部分的氮化镓层14，并形成至少两凹槽30于绝缘掺杂区24的两侧。在一些实施例中，通过调整蚀刻步骤E2的参数，可以控制凹槽30的深度，因此凹槽30有可能达到部分的缓冲层12内，也就是说部分的缓冲层12可能也会在蚀刻步骤E2中被一并移除。此处的蚀刻步骤E2可能包含干蚀刻或湿蚀刻，由于该蚀刻技术属于本领域的已知技术，在此不多加赘述。
如图7所示，进行一蚀刻步骤E3，以移除第二图案化光致抗蚀剂26。此处所述的蚀刻步骤E3可能包含与上述蚀刻步骤E1相同或不同的步骤，在此不多加赘述。接着如图8所示，形成一绝缘层32，其中绝缘层32可能包含有各种绝缘材料，例如氧化硅、氮化硅、硅氧化物、TEOS等，而绝缘层32可通过例如化学气相沉积(CVD)、物理气相沉积(PVD)、等离子体增强化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)、高密度等离子体化学气相沉积(HDP-CVD)、快速热化学气相沉积(RTCVD)、金属有机化学气相沉积(MOCVD)、原子层沉积(ALD)、溅镀、热氧化或氮化或者其组合等技术来形成，本发明并不限于此。绝缘层32至少填满凹槽30，在绝缘层32填入凹槽30之后，将凹槽30以及位于其中的绝缘层32共同定义为侧壁绝缘结构34。侧壁绝缘结构34位于绝缘掺杂区24的两侧。在本发明中，侧壁绝缘结构34具有阻挡离子逸散的效果。为了让侧壁绝缘结构34具有更好的阻挡效果，侧壁绝缘结构34的底面较佳低于绝缘掺杂区24的底面，但本发明不限于此。
截至目前为止，已经完成本发明所述的高电子迁移率晶体管的绝缘结构的基本结构。如图8所示，此绝缘结构包含有一氮化镓层14、一氮化铝镓层16，位于氮化镓层14上、一绝缘掺杂区24，位于氮化镓层14与氮化铝镓层16中，以及两侧壁绝缘结构34，分别位于绝缘掺杂区24的两侧。
如上所述，以离子掺杂的方式，在氮化镓层与氮化铝镓层掺杂离子以破坏二维电子气层并且形成绝缘区域的方法有一缺点，那就是若后续面临加热步骤，此时掺杂于氮化镓层与氮化铝镓层中的离子可能会溢散，并且使得该绝缘区域的绝缘效果降低，甚至可能让绝缘区域失去绝缘效果。为了避免此情况，本发明在绝缘掺杂区24完成后，额外在绝缘掺杂区两侧形成两侧壁绝缘结构34。通过两侧壁绝缘结构34设置在绝缘掺杂区24的两侧，即使后续对半导体元件进行加热步骤，活化的离子由于受到侧壁绝缘结构34的阻挡，因此不容易逸散至别处，确保绝缘掺杂区24的绝缘效果。
后续，可对已经完成绝缘区域的半导体结构，继续进行其他制作工艺，例如形成高电子迁移率晶体管相应的栅极、源/漏极、接触结构等。由于该些制作工艺属于本领域的已知技术，在此不多加赘述。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (19)

1.一种高电子迁移率晶体管(high electron mobility transistor,HEMT)的绝缘结构，其特征在于，包含：
氮化镓层；
氮化铝镓层，位于该氮化镓层上；
绝缘掺杂区，位于该氮化镓层与该氮化铝镓层中；以及
两侧壁绝缘结构，分别位于该绝缘掺杂区的两侧。
2.如权利要求1所述的高电子迁移率晶体管的绝缘结构，其中该绝缘掺杂区包含有多个掺杂离子，该些掺杂离子包含有氦(He)、磷(P)、氩(Ar)、氮(N)、氧(O)或砷(As)离子。
3.如权利要求1所述的高电子迁移率晶体管的绝缘结构，其中该两侧壁绝缘结构包含有绝缘层，位于两凹槽中，且该两凹槽分别位于该绝缘掺杂区的两侧。
4.如权利要求3所述的高电子迁移率晶体管的绝缘结构，其中该绝缘层覆盖于该绝缘掺杂区上。
5.如权利要求1所述的高电子迁移率晶体管的绝缘结构，其中部分该氮化镓层与部分该氮化铝镓层之间包含有二维电子气层。
6.如权利要求5所述的高电子迁移率晶体管的绝缘结构，其中该二维电子气层不位于该绝缘掺杂区中。
7.如权利要求1所述的高电子迁移率晶体管的绝缘结构，还包含有缓冲层，位于该氮化镓层下方。
8.如权利要求7所述的高电子迁移率晶体管的绝缘结构，其中该绝缘掺杂区的范围包含部分该氮化镓层、部分该氮化铝镓层以及部分该缓冲层。
9.如权利要求1所述的高电子迁移率晶体管的绝缘结构，其中该两侧壁绝缘结构中的至少一个该侧壁绝缘结构的底面低于该绝缘掺杂区的底面。
10.一种形成高电子迁移率晶体管(high electron mobility transistor,HEMT)的绝缘结构的方法，包含：
形成氮化镓层；
形成氮化铝镓层于该氮化镓层上；
进行掺杂步骤，以掺杂多个离子于该氮化镓层与该氮化铝镓层中，并且在该氮化镓层与该氮化铝镓层中形成绝缘掺杂区；
形成两凹槽于该绝缘掺杂区的两侧；以及
填入绝缘层于该两凹槽中，并形成两侧壁绝缘结构分别位于该绝缘掺杂区的两侧。
11.如权利要求10所述的形成高电子迁移率晶体管的绝缘结构的方法，其中该绝缘掺杂区包含有多个掺杂离子，该些掺杂离子包含有氦(He)、磷(P)、氩(Ar)、氮(N)、氧(O)或砷(As)离子。
12.如权利要求10所述的形成高电子迁移率晶体管的绝缘结构的方法，其中还包含:
在该氮化铝镓层形成后，形成第一图案化光致抗蚀剂层于该氮化铝镓层上；以及
在该掺杂步骤后，移除该第一图案化光致抗蚀剂层。
13.如权利要求10所述的形成高电子迁移率晶体管的绝缘结构的方法，其中还包含:
在该掺杂步骤后，形成第二图案化光致抗蚀剂于该氮化铝镓层上；以及
进行蚀刻步骤，移除部分该氮化镓层与该氮化铝镓层，并形成该两凹槽。
14.如权利要求10所述的形成高电子迁移率晶体管的绝缘结构的方法，其中该绝缘层覆盖于该绝缘掺杂区上。
15.如权利要求10所述的形成高电子迁移率晶体管的绝缘结构的方法，其中部分该氮化镓层与部分该氮化铝镓层之间包含有二维电子气层。
16.如权利要求15所述的形成高电子迁移率晶体管的绝缘结构的方法，其中该二维电子气层不位于该绝缘掺杂区中。
17.如权利要求10所述的形成高电子迁移率晶体管的绝缘结构的方法，还包含形成有缓冲层于该氮化镓层下方。
18.如权利要求17所述的形成高电子迁移率晶体管的绝缘结构的方法，其中该绝缘掺杂区的范围包含部分该氮化镓层、部分该氮化铝镓层以及部分该缓冲层。
19.如权利要求10所述的形成高电子迁移率晶体管的绝缘结构的方法，其中该两侧壁绝缘结构中的至少一个该侧壁绝缘结构的底面低于该绝缘掺杂区的底面。
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