CN112133686B - 多芯片倒装贴片三维集成封装结构及其制造方法 - Google Patents

多芯片倒装贴片三维集成封装结构及其制造方法 Download PDF

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CN112133686B
CN112133686B CN202010833497.0A CN202010833497A CN112133686B CN 112133686 B CN112133686 B CN 112133686B CN 202010833497 A CN202010833497 A CN 202010833497A CN 112133686 B CN112133686 B CN 112133686B
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CN112133686A (zh
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刘本强
陈翔
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Shandong Hanture Technology Co ltd
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Abstract

本申请公开了一种多芯片倒装贴片三维集成封装结构,包括一级芯片和二级芯片,二级芯片以倒装方式与一级芯片连接,所述的一级芯片和二级芯片之间通过若干短凸点连接,所述的一级芯片通过装配层正装固定并连接在装配板上,所述的二级芯片通过若干长凸点与装配板连接,位于装配板上部且一级芯片的一侧固定有芯间连接编程盒,所述若干短凸点均连接一个短凸连接板,所述若干长凸点均连接一个长凸连接板,所述长凸连接板与短凸点的接触处通过绝缘材料隔绝,所述的长凸连接板通过上行线连接芯间连接编程盒,所述的短凸连接板通过折弯的下行线连接芯间连接编程盒,所述的下行线布线中穿插过位于装配板上的装配缺口。本申请还公开了上述结构的制造方法。

Description

多芯片倒装贴片三维集成封装结构及其制造方法
技术领域
本申请涉及一种多芯片倒装贴片三维集成封装结构及其制造方法。
背景技术
在现有的多芯片倒装贴片技术中,中国发明CN201811366711.5公开了一种多芯片倒装贴片三维集成封装结构及其制造方法,其多芯片倒装贴片三维集成封装结构,如图7所示,该多芯片倒装贴片三维集成封装结构100包括封装基板110、第一芯片120、贴片层130、第二芯片140、第一凸点141、第二凸点142塑封层150以及外接焊盘160。封装基板110为普通封装基板,如亚克力、PCB、玻璃等封装基板。在其公开的一个实施例中封装基板为多层板,其内和或表面设置有重新布局布线线路,上下表面的对应位置分别设置有焊盘。第一芯片120可以为处理器、存储器、SOC等各类功能芯片,通过贴皮层130正装贴片至封装基板110的对应位置,第一芯片120的正面具有焊盘。第二芯片140通过第一凸点141和第二凸点142倒装焊接在第一芯片120 和封装基板110的对应焊盘上,其中通过第一凸点141与第一芯片120形成电和或信号互连;通过第二凸点142与封装基板110第一面的焊盘形成电和或信号的互连。其中第一凸点141的高度低于第二凸点142的高度,在封装结构中,第二凸点142的高度H等于第一凸点141的高度h与第一芯片120的厚度T 以及贴片层130的厚度t之和。塑封层150位于封装基板110的第一面上,包覆第一芯片120、第二芯片 140,并填充封装基板110、第一芯片120以及第二芯片140之间的间隙。外接焊盘160位于封装基板110的第二面,通过基板通孔 和或重新布局布线互连与第二芯片140电连接。
上述专利还公开了上述多芯片倒装贴片三维集成封装结构的制造方法,其包括步骤:
在第一芯片上形成第一凸点;在第一芯片上形成第二凸点;提供第二芯片、贴片材料和封装基板;将第二芯片正装贴片至封装基板;将第一芯片倒装焊接至第二芯片和封装基板;
对封装结构进行塑封保护;以及在封装基板的外表面形成外接焊球。
上述的多芯片倒装贴片三维集成封装结构是现有技术中比较普遍的结构,该结构的核心是将两层芯片(两个芯片或多个芯片形成的两层芯片)的中间部分以倒装的方式连接(如上述专利中的第一芯片120和第二芯片140的中间部分以倒装的方式连接),然而实际上该结构的局限是两层芯片的中间部分不能再进行凸点的设置,即不能再设置第三层等其他层,也不能将两层的多个芯片多级连接,而只能进行两级的连接交互,这实际上限制了封装芯片的集成度,在封装芯片时很多时候对芯片的集成度要求很高,比如需要很多级芯片之间相连,因为上述专利涉及的技术中两层芯片的中间部分不能再进行凸点的设置,就不能再连接其他芯片的凸点或引脚,所以上述技术中实质仅能实现两级芯片的逻辑连接而不能实现多级芯片之间相连及封装。
发明内容
本申请的目的在于提供一种多芯片倒装贴片三维集成封装结构及其制造方法:
其中的多芯片倒装贴片三维集成封装结构,包括一级芯片和二级芯片,所述的二级芯片以倒装方式与一级芯片连接,所述的一级芯片和二级芯片之间通过若干短凸点连接,所述的一级芯片通过装配层正装固定并连接在装配板上,所述的二级芯片通过若干长凸点与装配板连接,位于装配板上部且一级芯片的一侧固定有芯间连接编程盒,所述若干短凸点均连接一个短凸连接板,所述若干长凸点均连接一个长凸连接板,所述长凸连接板与短凸点的接触处通过绝缘材料隔绝,所述的长凸连接板通过上行线连接芯间连接编程盒,所述的短凸连接板通过折弯的下行线连接芯间连接编程盒,所述的下行线布线中穿插过位于装配板上的装配缺口。
进一步,所述的芯间连接编程盒包括若干单位接头,每一个单位接头上均设置若干用于插接下行线或上行线的接槽,每个单位接头对应设置一个集线板,每一个单位接头都通过一根盒内线与其他的单位接头连接,每一个盒内线上都设置一个编程块;所述的集线板内设置用于连接盒内线和接槽的电路。
进一步,所述单位接头的数量为n,则对于每一个单位接头共有n-1根盒内线与其连接,芯间连接编程盒内共有Cn 2个编程块。
进一步,所述的盒内线是多条独立线集合而成,每根盒内线独立线的数量与其所连接芯片引脚数量一样。
多芯片倒装贴片三维集成封装结构还包括熔断编程器件,所述的熔断编程器件包括熔断板,所述熔断板的横截面为矩形结构,所述的芯间连接编程盒横截面也是矩形结构,编程块在芯间连接编程盒内排布在同一个水平横截面且每一个编程块的上端均镂空,熔断板的横截面尺寸大于芯间连接编程盒横截面尺寸,熔断板上在竖直方向按照编程块在芯间连接编程盒内的排布固定若干熔断针,以使得熔断板贴合芯间连接编程盒顶部时,部分熔断针正好落在编程块内。
进一步,所述熔断板的边缘设置操作柄。
进一步,所述的熔断针可活动固定在熔断板上,以使得熔断针在熔断板上的位置可上下活动。
其中,多芯片倒装贴片三维集成封装结构的制造方法包括步骤:
按照标准配置好若干短凸连接板、若干长凸连接板、芯间连接编程盒和若干一级芯片、若干二级芯片和设置有装配缺口的装配板;
将若干一级芯片通过装配层正装在装配板上;
在一级芯片的上部预设若干短凸点同时在一级芯片的两侧预设若干长凸点;
在短凸点上安装短凸连接板然后在长凸点上安装长凸连接板;
使用下行线将短凸连接板和芯间连接编程盒连接,使用上行线将长凸连接板和芯间连接编程盒连接;
将二级芯片倒装到一级芯片的上部并且将其引脚与短凸点、长凸点连接;
使用封装材料进行封装,并且将短凸连接板、长凸连接板、下行线、上行线、芯间连接编程盒都封装在内。
进一步,所述的配置好芯间连接编程盒是指根据芯片要求将芯间连接编程盒进行熔断编程。
有益效果:
本申请中通过芯间连接编程盒的可熔断编程和短凸连接板、长凸连接板、下行线、上行线的连接配合可以将各级别的芯片中任意两个芯片的引脚连接在一起,这样就解决了背景技术中“不能实现多级芯片之间逻辑相连及封装”的问题,通过实现芯片之间的多级连接可以提高芯片在封装时的集成度,进而丰富单个封装结构的芯片控制逻辑,支持多个级别的芯片在一个封装结构中协同工作。
附图说明
图1是本申请中封装结构在一种实施例中的示意图并具体是竖向截面图;
图2是本申请中封装结构在一种实施例中的示意图并具体是俯视方向图;
图3是本申请中封装结构在具有两组芯片并由芯间连接编程盒连接的示意图;
图4是本申请中封装结构中芯间连接编程盒的结构示意图;
图5是本申请中封装结构中芯间连接编程盒的结构示意图;
图6是本申请中封装结构中芯间连接编程盒与熔断编程器的结构示意图;
图7是现有技术中的一种封装结构图;
图中:
一级芯片1 ,二级芯片2, 装配板3,装配层4,短凸点5,长凸点6,短凸连接板7,长凸连接板8,下行线9,上行线10,装配缺口11,芯间连接编程盒12,单位接头121,接槽122,集线板123 ,编程块124, 盒内线125 ,熔断板126 , 熔断针127 ,操作柄128;
具体实施方式
以下结合具体实施例,对本申请进一步说明。当然,以下实施例仅用于说明本申请而非用于限制本申请的范围。
具体实施中,如图1和图2所示,本申请的封装结构包括一级芯片1和二级芯片2,所述的二级芯片2以倒装方式与一级芯片1连接,所述的一级芯片1和二级芯片2之间通过若干短凸点5连接,所述的一级芯片1通过装配层4正装固定并连接在装配板3上,所述的二级芯片2通过若干长凸点6与装配板3连接,位于装配板3上部且一级芯片1的一侧固定有芯间连接编程盒12,所述若干短凸点5均连接一个短凸连接板7,所述若干长凸点6均连接一个长凸连接板8,所述长凸连接板8与短凸点5的接触处通过绝缘材料隔绝,所述的长凸连接板8通过上行线10连接芯间连接编程盒12,所述的短凸连接板7通过折弯的下行线9连接芯间连接编程盒12,所述的下行线9布线中穿插过位于装配板3上的装配缺口11;所述的下行线9布线中穿插过位于装配板3上的装配缺口11具体为:所述的装配缺口11包括位置在长凸点6内侧方向的第一类装配缺口11和位置在长凸点6外侧方向的第二类装配缺口11,所述的装配缺口11均贯通设置在装配板3上,所述的下行线9一端与短凸连接板7连接,所述的下行线9另外一端首先穿过一个第一类装配缺口11然后再穿过一个第二类装配缺口11后与芯间连接编程盒12连接;如图3所示,两组一级芯片1或二级芯片2通过下行线9和上行线10连接在同一个芯间连接编程盒12上,在实施中本申请实质增加了具有核心功能的芯间连接编程盒12,所述的芯间连接编程盒12用于将各级别的芯片中任意两个芯片的引脚连接在一起,这样就解决了背景技术中的问题,具体地,再如图3所示的一个具体实施例中,两组一级芯片1或二级芯片2通过下行线9和上行线10连接在同一个芯间连接编程盒12上实质上可以构成两级芯片的连接,也可以构成三级芯片的连接,也可以构成四级芯片连接,假设四个芯片分别为A、B、C、D,其中的A、B在位置关系上对应一级芯片1和二级芯片2的关系,其中的C、D在位置关系上也对应一级芯片1和二级芯片2的关系,如果使用芯间连接编程盒12来连接则实质上芯片共有两个级别关系即:A到B,或者C到D。
如果使用下行线9或上行线10(当然也使用了长凸连接板8和短凸连接板7)将A、B中任一个芯片连接到芯间连接编程盒12的接头E,同时也将C、D中任一个芯片连接到芯间连接编程盒12的接头F,然后在芯间连接编程盒12内部E和F连接,这样就可以完成多级的芯片连接,如三级关系:A到B到C,或者A到B到D;或者四级关系:A到B到C再到D。
通过实现芯片之间的多级连接可以提高芯片在封装时的集成度,进而丰富单个封装结构的芯片控制逻辑,让多个级别的芯片在一个封装结构中协同工作成为可能。支持多个级别的芯片在一个封装结构中协同工作。在具体实施中,根据封装结构的具体功能选择确定的芯片数量和种类后就可以将上述的芯间连接编程盒12、短凸连接板7、长凸连接板8、下行线9、上行线10全部制定标准化的接口,比如将芯间连接编程盒12制作成标准化的集成电路,将短凸连接板7、长凸连接板8制作为与特定芯片适配的标准化电板,将下行线9和上行线10制作为标准线。
具体实施中,如图4所示,所述的芯间连接编程盒12包括若干单位接头121,每一个单位接头121上均设置若干用于插接下行线9或上行线10的接槽122,每个单位接头121对应设置一个集线板123,每一个单位接头121都通过一根盒内线125与其他的单位接头121连接,每一根盒内线125上都设置一个编程块124;所述的集线板123内设置用于连接盒内线125和接槽122的电路;在实施中,所述的芯间连接编程盒12被配置成可编程的器件,具体是指通过其内部不同的编程块124进行熔断(留下未熔断的编程块124),进而可以导通不同的盒内线125,如图5所示,所述的每一根盒内线125都是多条独立线集合而成,每根盒内线125独立线的数量与其所连接芯片引脚数量一样;每一根盒内线125两端都连接一个单位接头121,单位接头121可以通过接槽122连接所需要的下行线9或上行线10(下行线9或上行线10最终连接芯片的引脚),这样通过熔断不同的编程块124就可以对不同的芯片之间的连接进行编程控制,当然实施中所述的芯间连接编程盒12以及其内部的编程块124、盒内线125的结构也可以根据芯片选择的需求制定为标准化的。
再如图4所示的一种实施例中,单位接头121的数量为十根,对于每一个单位接头121共有九根盒内线125与其连接,芯间连接编程盒12内共有四十五个编程块124,上述的实施例最多可以同时连接十个芯片的下行线9或上行线10,通过之前实施举例可以知最多可以支持五组芯片级连,并且最高可以形成十级芯片关系。所以假设,所述单位接头121的数量为n,则对于每一个单位接头121共有n-1根盒内线125与其连接,芯间连接编程盒12内共有Cn 2个编程块124。
在具体实施中,如图6所示,本申请的封装结构在装配中还可以配置熔断编程器件,所述的熔断编程器件包括熔断板126,所述熔断板126的横截面为矩形结构,所述的芯间连接编程盒12横截面也是矩形结构,编程块124在芯间连接编程盒12内排布在同一个水平横截面且每一个编程块124的上端均镂空(用于插入后面所述的熔断针127以实现熔断编程),熔断板126的横截面尺寸大于芯间连接编程盒12横截面尺寸,熔断板126上在竖直方向按照编程块124在芯间连接编程盒12内的排布固定若干熔断针127,以使得熔断板126贴合芯间连接编程盒12顶部时,部分熔断针127正好落在编程块124内。
在具体实施中,如果逐个对编程块124进行熔断编程则效率较低,为了方便熔断芯间连接编程盒12内的编程块124以实现对盒内线125线路的编程可以配置上述的熔断编程器件,熔断编程器件上设置排列好的熔断针127,实施中通过电加热或外部加热将熔断针127升温后,将熔断板126从芯间连接编程盒12上部压下使得熔断板126贴合芯间连接编程盒12顶部时,部分熔断针127(被编制预设的)正好落在编程块124内,进而可以熔断编程不需要的编程块124,留下需要的编程块124,通过这种方式就可以高效快速熔断编程块124。
实施中可以在所述熔断板126的边缘设置操作柄128,设置操作柄128可以隔绝熔断板126上的高温,可以避免外部器件对熔断板126操控时受到高温的影响;在实施中,所述的熔断针127可活动固定在熔断板126上,以使得熔断针127在熔断板126上的位置可上下活动;通过设置可上下活动的熔断针127,在实施中如果因为芯片升级等原因需要改变芯间连接编程盒12内编程块124的熔断关系,则只需要调整不同的熔断针127的上下位置就可以完成,当熔断针127根据需要做调整了,那么被熔断的编程块124也会发生变化,这样就可以精准控制更新。
在具体实施中,前述本申请封装结构的制造方法如下:
按照标准配置好若干短凸连接板7、若干长凸连接板8、芯间连接编程盒12和若干一级芯片1、若干二级芯片2和设置有装配缺口11的装配板3;
将若干一级芯片1通过装配层4正装在装配板3上;
在一级芯片1的上部预设若干短凸点5同时在一级芯片1的两侧预设若干长凸点6;
在短凸点5上安装短凸连接板7然后在长凸点6上安装长凸连接板8;
使用下行线9将短凸连接板7和芯间连接编程盒12连接,使用上行线10将长凸连接板8和芯间连接编程盒12连接;
将二级芯片2倒装到一级芯片1的上部并且将其引脚与短凸点5、长凸点6连接;
使用封装材料进行封装,并且将短凸连接板7、长凸连接板8、下行线9、上行线10、芯间连接编程盒12都封装在内。
其中配置好芯间连接编程盒12是指根据芯片要求将芯间连接编程盒12进行熔断编程。

Claims (9)

1.一种多芯片倒装贴片三维集成封装结构,包括一级芯片和二级芯片,所述的二级芯片以倒装方式与一级芯片连接,所述的一级芯片和二级芯片之间通过若干短凸点连接,所述的一级芯片通过装配层正装固定并连接在装配板上,所述的二级芯片通过若干长凸点与装配板连接,其特征在于,位于装配板上部且一级芯片的一侧固定有芯间连接编程盒,所述若干短凸点均连接一个短凸连接板,所述若干长凸点均连接一个长凸连接板,所述长凸连接板与短凸点的接触处通过绝缘材料隔绝,所述的长凸连接板通过上行线连接芯间连接编程盒,所述的短凸连接板通过折弯的下行线连接芯间连接编程盒,所述的下行线布线中穿插过位于装配板上的装配缺口;所述的下行线布线中穿插过位于装配板上的装配缺口具体为:所述的装配缺口包括位置在长凸点内侧方向的第一类装配缺口和位置在长凸点外侧方向的第二类装配缺口,所述的装配缺口均贯通设置在装配板上,所述的下行线一端与短凸连接板连接,所述的下行线另外一端首先穿过一个第一类装配缺口然后再穿过一个第二类装配缺口后与芯间连接编程盒连接;所述的芯间连接编程盒用于将各级别的芯片中任意两个芯片的引脚连接在一起;两组一级芯片和二级芯片通过下行线和上行线连接在同一个芯间连接编程盒上构成三级芯片的连接或构成四级芯片连接;所述短凸连接板和长凸连接板均位于一级芯片和二级芯片之间,短凸连接板靠近一级芯片,长凸连接板靠近二级芯片。
2.根据权利要求1所述的一种多芯片倒装贴片三维集成封装结构,其特征在于,所述的芯间连接编程盒包括若干单位接头,每一个单位接头上均设置若干用于插接下行线或上行线的接槽,每个单位接头对应设置一个集线板,每一个单位接头都通过一根盒内线与其他的单位接头连接,每一个盒内线上都设置一个编程块;所述的集线板内设置用于连接盒内线和接槽的电路。
3.根据权利要求2所述的一种多芯片倒装贴片三维集成封装结构,其特征在于,所述单位接头的数量为n,则对于每一个单位接头共有n-1根盒内线与其连接,芯间连接编程盒内共有Cn 2个编程块。
4.根据权利要求2或3所述的一种多芯片倒装贴片三维集成封装结构,其特征在于,所述的盒内线是多条独立线集合而成,每根盒内线独立线的数量与其所连接芯片引脚数量一样。
5.根据权利要求2所述的一种多芯片倒装贴片三维集成封装结构,其特征在于,还包括熔断编程器件,所述的熔断编程器件包括熔断板,所述熔断板的横截面为矩形结构,所述的芯间连接编程盒横截面也是矩形结构,编程块在芯间连接编程盒内排布在同一个水平横截面且每一个编程块的上端均镂空,熔断板的横截面尺寸大于芯间连接编程盒横截面尺寸,熔断板上在竖直方向按照编程块在芯间连接编程盒内的排布固定若干熔断针,以使得熔断板贴合芯间连接编程盒顶部时,部分熔断针正好落在编程块内。
6.根据权利要求5所述的一种多芯片倒装贴片三维集成封装结构,其特征在于,所述熔断板的边缘设置操作柄。
7.根据权利要求5所述的一种多芯片倒装贴片三维集成封装结构,其特征在于,所述的熔断针可活动固定在熔断板上,以使得熔断针在熔断板上的位置可上下活动。
8.一种如权利要求1或2或3所述的一种多芯片倒装贴片三维集成封装结构的制造方法,其特征在于,包括步骤:
按照标准配置好若干短凸连接板、若干长凸连接板、芯间连接编程盒和若干一级芯片、若干二级芯片和设置有装配缺口的装配板;
将若干一级芯片通过装配层正装在装配板上;
在一级芯片的上部预设若干短凸点同时在一级芯片的两侧预设若干长凸点;
在短凸点上安装短凸连接板然后在长凸点上安装长凸连接板;
使用下行线将短凸连接板和芯间连接编程盒连接,使用上行线将长凸连接板和芯间连接编程盒连接;
将二级芯片倒装到一级芯片的上部并且将其引脚与短凸点、长凸点连接;
使用封装材料进行封装,并且将短凸连接板、长凸连接板、下行线、上行线、芯间连接编程盒都封装在内。
9.根据权利要求8所述的一种多芯片倒装贴片三维集成封装结构的制造方法,其特征在于,所述的配置好芯间连接编程盒是指根据芯片要求将芯间连接编程盒进行熔断编程。
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101587847A (zh) * 2009-06-15 2009-11-25 美新半导体(无锡)有限公司 利用pcb基板进行垂直互连的多芯片组件封装方法
CN104750581A (zh) * 2015-04-01 2015-07-01 浪潮电子信息产业股份有限公司 一种冗余互连的内存共享的服务器系统

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WO2018058359A1 (en) * 2016-09-28 2018-04-05 Intel Corporation Stacked chip package having substrate interposer and wirebonds

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101587847A (zh) * 2009-06-15 2009-11-25 美新半导体(无锡)有限公司 利用pcb基板进行垂直互连的多芯片组件封装方法
CN104750581A (zh) * 2015-04-01 2015-07-01 浪潮电子信息产业股份有限公司 一种冗余互连的内存共享的服务器系统

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