CN112133686B - 多芯片倒装贴片三维集成封装结构及其制造方法 - Google Patents
多芯片倒装贴片三维集成封装结构及其制造方法 Download PDFInfo
- Publication number
- CN112133686B CN112133686B CN202010833497.0A CN202010833497A CN112133686B CN 112133686 B CN112133686 B CN 112133686B CN 202010833497 A CN202010833497 A CN 202010833497A CN 112133686 B CN112133686 B CN 112133686B
- Authority
- CN
- China
- Prior art keywords
- chip
- programming
- plate
- box
- inter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 32
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000011810 insulating material Substances 0.000 claims abstract description 4
- 230000000149 penetrating effect Effects 0.000 claims description 3
- 239000005022 packaging material Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 description 18
- 238000010586 diagram Methods 0.000 description 7
- 238000005538 encapsulation Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 229930091051 Arenine Natural products 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 230000001174 ascending effect Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/1701—Structure
- H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
Claims (9)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010833497.0A CN112133686B (zh) | 2020-08-18 | 2020-08-18 | 多芯片倒装贴片三维集成封装结构及其制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010833497.0A CN112133686B (zh) | 2020-08-18 | 2020-08-18 | 多芯片倒装贴片三维集成封装结构及其制造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN112133686A CN112133686A (zh) | 2020-12-25 |
CN112133686B true CN112133686B (zh) | 2022-06-28 |
Family
ID=73850398
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010833497.0A Active CN112133686B (zh) | 2020-08-18 | 2020-08-18 | 多芯片倒装贴片三维集成封装结构及其制造方法 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN112133686B (zh) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101587847A (zh) * | 2009-06-15 | 2009-11-25 | 美新半导体(无锡)有限公司 | 利用pcb基板进行垂直互连的多芯片组件封装方法 |
CN104750581A (zh) * | 2015-04-01 | 2015-07-01 | 浪潮电子信息产业股份有限公司 | 一种冗余互连的内存共享的服务器系统 |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102149150B1 (ko) * | 2013-10-21 | 2020-08-28 | 삼성전자주식회사 | 전자 장치 |
WO2018058359A1 (en) * | 2016-09-28 | 2018-04-05 | Intel Corporation | Stacked chip package having substrate interposer and wirebonds |
-
2020
- 2020-08-18 CN CN202010833497.0A patent/CN112133686B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101587847A (zh) * | 2009-06-15 | 2009-11-25 | 美新半导体(无锡)有限公司 | 利用pcb基板进行垂直互连的多芯片组件封装方法 |
CN104750581A (zh) * | 2015-04-01 | 2015-07-01 | 浪潮电子信息产业股份有限公司 | 一种冗余互连的内存共享的服务器系统 |
Also Published As
Publication number | Publication date |
---|---|
CN112133686A (zh) | 2020-12-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5696027A (en) | Method of manufacturing a semiconductor chip carrier affording a high-density external interface | |
US5247423A (en) | Stacking three dimensional leadless multi-chip module and method for making the same | |
US7919355B2 (en) | Multi-surface IC packaging structures and methods for their manufacture | |
US5172303A (en) | Electronic component assembly | |
US4616406A (en) | Process of making a semiconductor device having parallel leads directly connected perpendicular to integrated circuit layers therein | |
US10163874B2 (en) | Packaged devices with multiple planes of embedded electronic devices | |
US20020047196A1 (en) | Multi-chip module with extension | |
JPH10504934A (ja) | 組立て型半導体チップキャリア | |
US11664348B2 (en) | Substrate assembly semiconductor package including the same and method of manufacturing 1HE semiconductor package | |
JPH07202378A (ja) | パッケージ化電子ハードウェア・ユニット | |
KR101145041B1 (ko) | 반도체칩 패키지, 반도체 모듈 및 그 제조 방법 | |
CN103258806A (zh) | 具桥接结构的半导体封装构造及其制造方法 | |
CN101924047A (zh) | 半导体器件及其制造方法 | |
CN206259351U (zh) | 电子设备 | |
CN112133686B (zh) | 多芯片倒装贴片三维集成封装结构及其制造方法 | |
US20090201656A1 (en) | Semiconductor package, and method of manufacturing semiconductor package | |
CN105225975B (zh) | 封装结构及其制法 | |
US6208027B1 (en) | Temporary interconnect for semiconductor devices | |
US11721686B2 (en) | Semiconductor package structure and packaging method thereof | |
US6365437B2 (en) | Method of connecting a die in an integrated circuit module | |
KR20080012671A (ko) | 인터포저와 그를 이용한 반도체 패키지 | |
CN103928416B (zh) | 具有无源器件的半导体封装件及其堆叠方法 | |
KR100489476B1 (ko) | 엠씨엠 볼 그리드 어레이 패키지 제조방법 | |
KR20190057801A (ko) | 와이어 본딩 구조를 갖는 반도체 장치 및 그 형성방법 | |
KR20060046891A (ko) | 반도체 장치 및 그의 제조 방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
PE01 | Entry into force of the registration of the contract for pledge of patent right | ||
PE01 | Entry into force of the registration of the contract for pledge of patent right |
Denomination of invention: Multi chip flip chip 3D integrated packaging structure and manufacturing method Effective date of registration: 20230417 Granted publication date: 20220628 Pledgee: Zaozhuang rural commercial bank Limited by Share Ltd. Yicheng sub branch Pledgor: SHANDONG HANTURE TECHNOLOGY CO.,LTD. Registration number: Y2023980038276 |
|
PC01 | Cancellation of the registration of the contract for pledge of patent right |
Granted publication date: 20220628 Pledgee: Zaozhuang rural commercial bank Limited by Share Ltd. Yicheng sub branch Pledgor: SHANDONG HANTURE TECHNOLOGY CO.,LTD. Registration number: Y2023980038276 |