CN112074958A - 具有不同绝缘栅极氧化物的分裂栅闪存存储器单元及其形成方法 - Google Patents

具有不同绝缘栅极氧化物的分裂栅闪存存储器单元及其形成方法 Download PDF

Info

Publication number
CN112074958A
CN112074958A CN201980030337.8A CN201980030337A CN112074958A CN 112074958 A CN112074958 A CN 112074958A CN 201980030337 A CN201980030337 A CN 201980030337A CN 112074958 A CN112074958 A CN 112074958A
Authority
CN
China
Prior art keywords
thickness
polysilicon layer
polysilicon
insulating
insulated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201980030337.8A
Other languages
English (en)
Other versions
CN112074958B (zh
Inventor
N·多
苏千乗
杨任伟
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Silicon Storage Technology Inc
Original Assignee
Silicon Storage Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Storage Technology Inc filed Critical Silicon Storage Technology Inc
Publication of CN112074958A publication Critical patent/CN112074958A/zh
Application granted granted Critical
Publication of CN112074958B publication Critical patent/CN112074958B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Inorganic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明公开了一种存储器设备，该存储器设备包括：半导体衬底，该半导体衬底具有间隔开的源极区和漏极区，其中衬底的沟道区在该源极区与该漏极区之间延伸；多晶硅的浮栅，该浮栅设置在沟道区的第一部分上方并且通过具有第一厚度的绝缘材料与该第一部分绝缘，其中该浮栅具有终止于锐利边缘的倾斜上表面；多晶硅的字线栅，该字线栅设置在沟道区的第二部分上方并且通过具有第二厚度的绝缘材料与该第二部分绝缘；以及多晶硅的擦除栅，该擦除栅设置在源极区上方并且通过具有第三厚度的绝缘材料与该源极区绝缘，其中该擦除栅包括包绕在浮栅的锐利边缘周围并与该锐利边缘绝缘的凹口。该第三厚度大于该第一厚度，并且该第一厚度大于该第二厚度。

Description

具有不同绝缘栅极氧化物的分裂栅闪存存储器单元及其形成 方法
相关专利申请
本申请要求于2018年5月9日提交的美国临时申请号62/669263和于2018年8月7日提交的美国专利申请号16/057750的权益。
技术领域
本发明涉及分裂栅非易失性存储器单元。
背景技术
具有三个栅极的分裂栅非易失性存储器单元是已知的。参见例如美国专利7315056，其公开了分裂栅存储器单元，分裂栅存储器单元各自具有：在半导体衬底中的源极区和漏极区，该半导体衬底具有在该源极区与该漏极区之间延伸的沟道区；位于沟道区的第一部分上方的浮栅；位于沟道区的第二部分上方的控制栅(也称为字线栅)；以及位于源极区上方的P/E栅。
需要制造方法改进来更好地控制存储器单元的各种元件的形成。
发明内容
上述问题和需求通过存储器设备来解决，该存储器设备包括：半导体衬底，该半导体衬底具有间隔开的源极区和漏极区，其中衬底的沟道区在该源极区与该漏极区之间延伸；多晶硅的浮栅，该浮栅设置在沟道区的第一部分上方并且通过具有第一厚度的绝缘材料与该第一部分绝缘，其中浮栅具有终止于锐利边缘的倾斜上表面；多晶硅的字线栅，该字线栅设置在沟道区的第二部分上方并且通过具有第二厚度的绝缘材料与该第二部分绝缘；和多晶硅的擦除栅，该擦除栅设置在源极区上方并且通过具有第三厚度的绝缘材料与该源极区绝缘，其中擦除栅包括包绕在浮栅的锐利边缘周围并与该锐利边缘绝缘的凹口。第三厚度大于第一厚度，并且第一厚度大于第二厚度。
存储器设备包括半导体衬底，该半导体衬底具有源极区、第一漏极区和第二漏极区，其中衬底的第一沟道区在源极区与第一漏极区之间延伸，并且衬底的第二沟道区在源极区和第二漏极区之间延伸。多晶硅的第一浮栅设置在第一沟道区的第一部分上方并且通过具有第一厚度的绝缘材料与该第一部分绝缘，其中第一浮栅具有终止于第一锐利边缘的倾斜上表面。多晶硅的第二浮栅设置在第二沟道区的第一部分上方并且通过具有第一厚度的绝缘材料与该第一部分绝缘，其中第二浮栅具有终止于第二锐利边缘的倾斜上表面。多晶硅的第一字线栅设置在第一沟道区的第二部分上方并且通过具有第二厚度的绝缘材料与该第二部分绝缘。多晶硅的第二字线栅设置在第二沟道区的第二部分上方并且通过具有第二厚度的绝缘材料与该第二部分绝缘。多晶硅的擦除栅设置在源极区上方并且通过具有第三厚度的绝缘材料与该源极区绝缘，其中擦除栅包括第一凹口和第二凹口，该第一凹口包绕在第一浮栅的第一锐利边缘周围并与该第一锐利边缘绝缘，该第二凹口包绕在第二浮栅的第二锐利边缘周围并与该第二锐利边缘绝缘。第三厚度大于第一厚度，并且第一厚度大于第二厚度。
一种形成存储器设备的方法包括：
在半导体衬底上形成具有第一厚度的第一绝缘层；
在第一绝缘层上形成第一多晶硅层；
在第一多晶硅层上形成间隔开的第一绝缘间隔物和第二绝缘间隔物；
移除第一多晶硅层的部分，使得第一多晶硅层的第一块保持在第一绝缘间隔物下方，并且第一多晶硅层的第二块保持在第二绝缘间隔物下方，其中第一多晶硅层的第一块和第二块中的每一者具有终止于锐利边缘的倾斜上表面；
在衬底中形成源极区，该源极区被设置在位于第一多晶硅层的第一块和第二块之间的间隙下方；
在半导体衬底上在源极区上方形成具有第二厚度的第二绝缘层；
在半导体衬底上形成具有第三厚度的第三绝缘层，该第三绝缘层与第一多晶硅层的第一块和第二块的彼此背离的侧表面相邻；
在衬底以及第一绝缘间隔物和第二绝缘间隔物上方形成第二多晶硅层；
移除第二多晶硅层的部分，使得第二多晶硅层的第一块保持被设置在第二绝缘层上以及第一绝缘间隔物和第二绝缘间隔物之间，并且第二多晶硅层的第二块和第三块保持被设置在第三绝缘层上，其中第一绝缘间隔物被设置在第二多晶硅层的第一块和第二块之间，并且其中第二绝缘间隔物被设置在第二多晶硅层的第一块和第三块之间；
在与第二多晶硅层的第二块相邻的衬底中形成第一漏极区；以及
在与第二多晶硅层的第三块相邻的衬底中形成第二漏极区；
其中第二多晶硅层的第一块包括第一凹口和第二凹口，该第一凹口包绕在第一多晶硅层的第一块的锐利边缘周围并与该锐利边缘绝缘，该第二凹口包绕在第一多晶硅层的第二块的锐利边缘周围并与该锐利边缘绝缘；
其中第二厚度大于第一厚度，并且其中第一厚度大于第三厚度。
通过查看说明书、权利要求书和附图，本发明的其他目的和特征将变得显而易见。
附图说明
图1至图17是示出形成存储器单元的步骤的侧剖视图。
具体实施方式
本发明是形成每个存储器单元具有三个栅极的非易失性分裂栅存储器单元的改进方法。虽然附图仅示出了形成一对存储器单元，但应当理解，在该工艺期间形成存储器单元的阵列。该工艺通过在半导体衬底10的上表面上形成二氧化硅层(氧化物)12以及在氧化物层12上形成多晶硅层(多晶硅)14开始，如图1所示。为了掺杂多晶硅，此时可执行多晶硅注入。氮化硅层(氮化物)16在多晶硅层12上形成为硬掩模，如图2所示。光致抗蚀剂18形成在结构上方并且使用光刻工艺(即，光致抗蚀剂形成，光致抗蚀剂的选择性曝光，移除光致抗蚀剂的选择性部分，使下面的材料的部分暴露)来图案化。此处，氮化物层16的部分保持暴露。然后，使用氮化物蚀刻来移除氮化物层16的未被图案化的光致抗蚀剂18保护的暴露部分，从而留下多晶硅层14上的氮化物块16。然后，使用多晶硅倾斜蚀刻来蚀刻多晶硅层14的上表面，从而形成多晶硅层的倾斜上表面，其中上表面在其接近氮化物块16时向上倾斜。为了控制浮栅阈值电压，然后在多晶硅层14的暴露部分上执行注入，如图3所示。
在移除光致抗蚀剂之后，在多晶硅层14上形成氧化物间隔物20。间隔物的形成是众所周知的，并且涉及材料的沉积，随后是材料的各向异性蚀刻，由此除了其邻接竖直取向结构的部分之外移除材料。间隔物的上表面通常是圆形的。在这种情况下，沉积氧化物，之后进行各向异性氧化物蚀刻，从而使氧化物间隔物20邻接氮化物块16的侧壁，如图4所示。执行多晶硅蚀刻以移除多晶硅层14的未被氧化物间隔物20保护的部分，如图5所示。为了控制字线阈值电压，此时可执行到衬底的也未被氮化物块16和氧化物间隔物20保护的部分中的注入(使用衬底表面上的氧化物层12作为缓冲层)。通过执行氧化物沉积(例如，高温氧化物HTO沉积)和各向异性氧化物蚀刻来在多晶硅层14的暴露端部上形成氧化物间隔物22以在多晶硅14与稍后要形成的字线栅之间形成主隔离部，这在多晶硅层14的端部上(沿着侧表面)留下氧化物间隔物22，如图6所示。然后，例如通过高温氧化物沉积将另一个氧化物层24沉积在该结构上(作为高压外围设备的稍后要形成的栅极氧化物的主要部分)，如图7所示。
该结构覆盖有光致抗蚀剂26，该光致抗蚀剂被图案化以移除氮化物块16上方的光致抗蚀剂的部分。执行氧化物蚀刻、氮化物蚀刻和多晶硅蚀刻以移除氮化物块16上的氧化物层24、氮化物块16以及通过移除氮化物块16而暴露的多晶硅层14的部分，从而留下具有终止于锐利边缘14b的向上倾斜的上表面的多晶硅块14a。随后进行注入工艺以在氧化物间隔物20之间以及多晶硅块14a之间的衬底10中形成源极区28(即，源极区形成在氧化物间隔物20之间存在的间隙与多晶硅块14a之间存在的间隙下方)。所得结构在图8中示出。
然后，在包括锐利边缘14b的多晶硅块14a的暴露端部上形成隧道氧化物层30，如图9所示。具体地讲，隧道氧化物层30通过以下方式来形成：首先执行氧化物蚀刻(例如，湿法蚀刻)以使每个间隔物20的远离多晶硅块14a的相应端部的侧壁横向凹陷，从而暴露锐利边缘14b。然后，通过高温氧化物HTO沉积形成隧道氧化物层30。隧道氧化物层30沿着多晶硅层块14a的暴露侧壁延伸，并且包绕在锐利边缘14b周围。然而，HTO沉积不消耗多晶硅锐利边缘14b，从而保持其形状。
然后，使用湿法氧化使位于源极区28上方的氧化物32以及包绕在锐利边缘14b周围的隧道氧化物层30增厚，如图10所示。然后，在氧化物间隔物20之间形成光致抗蚀剂34，并且使用氧化物蚀刻来移除在该对间隔物外侧的衬底上的氧化物层，从而使衬底表面暴露，如图11所示。然后，在该对间隔物外侧的衬底上形成薄氧化物层(WL氧化物)36，如图12所示(在光致抗蚀剂移除之后)。
然后，多晶硅层38形成在结构上方。该多晶硅层可用于同一衬底的逻辑区域中。如果期望多晶硅层厚度在存储器阵列中比在逻辑区域中更厚，则盖氧化物层可形成在多晶硅层38上并且被图案化以从设备的存储器区域移除盖氧化物层，之后沉积附加多晶硅以增厚存储器区域中的多晶硅层38。逻辑区域中的盖氧化物层上的附加多晶硅稍后将通过下面所述的多晶硅CMP移除。所得结构在图13中示出。
然后，通过多晶硅CMP(化学机械抛光)将该结构平面化到氧化物间隔物20的顶部下方。多晶硅层38可通过利用材料注入来掺杂，并且此时退火。所得结构在图14中示出。光致抗蚀剂40在该结构上形成并被图案化，从而仅留下多晶硅层38的位于氧化物间隔物20之间的那些部分以及紧接氧化物间隔物20外侧的由光致抗蚀剂40覆盖的那些部分。然后，使用多晶硅蚀刻来移除多晶硅层38的未被光致抗蚀剂40保护的暴露部分，从而留下多晶硅层38的与氧化物间隔物20的外侧相邻的块38a、以及多晶硅层38的位于氧化物间隔物20之间的块38b。所得结构在图15中示出。
然后，执行注入以在与多晶硅块38a相邻的衬底中形成漏极区42。然后，在多晶硅块38a的外侧上形成绝缘材料的间隔物44。优选地，这些间隔物通过以下方式来形成：形成一个或多个绝缘层(例如，氧化物、氮化物、氧化物)，之后进行一个或多个各向异性蚀刻，如图16所示。然后，可使用附加注入和退火来进一步增强漏极区42。然后，在多晶硅块38a和38b的暴露上表面上形成自对准多晶硅化物46，以用于改进导电性。然后，ILD绝缘部形成在结构上方，其优选地包括在绝缘层48b上方形成的绝缘材料48a。然后，穿过ILD绝缘部形成接触孔，从而暴露漏极区42。然后，导电材料在该结构上形成并被图案化，填充接触孔，以形成在ILD绝缘部48上方延伸的位线50、以及在位线50和漏极区42之间延伸并在该位线和该漏极区之间提供导电的触点52。最终结构示于图17中。
如图17所示，该工艺形成成对的存储器单元。每个存储器单元对包括源极区28和两个漏极区42，其中两个沟道区54各自在源极区28与漏极区42中的一个漏极区之间延伸。擦除栅38b设置在源极区28上方并且通过厚氧化物层32与该源极区绝缘。每个存储器单元包括设置在沟道区54的第一部分上方并且与该第一部分绝缘的浮栅14a、以及设置在沟道区54的第二部分上方并且与该第二部分绝缘的字线栅38a。浮栅14a具有锐利尖端14b(由倾斜表面引起)，该锐利尖端面向形成在擦除栅38b中的凹口56，由此擦除栅38b包绕在浮栅14a的锐利尖端14b周围。锐利尖端14b通过隧道氧化物层30与擦除栅38b绝缘。字线栅38a通过氧化物层36与衬底绝缘，该氧化物层比位于浮栅14a与衬底10之间的氧化物12薄，该氧化物比位于擦除栅38b与源极区28之间的氧化物32薄。隧道氧化物30和位于字线栅38a下方的氧化物层36单独形成，并且因此可根据厚度单独调整以实现最佳性能。
可通过缩短沟道区54的在字线栅38a下方的部分(即，使字线栅38a在沟道区方向上的长度更短)以及减薄字线栅38a下方的氧化物层36(这可以相对于其他绝缘层诸如可以保持较厚的隧道氧化物独立地完成)来按比例缩小单元尺寸，这允许存储器单元的较高电流驱动。擦除栅38b和字线栅38a通过同一多晶硅沉积形成，因此对于所有存储器单元仅需要两次多晶硅沉积来形成浮栅14a、字线栅38a和擦除栅38b。通过光刻法确定每个字线栅38a的长度(在沟道区的方向上)以用于更好的尺寸控制。通过化学机械抛光确定字线栅38a和擦除栅38b的高度，这避免了字线栅应该代替地通过多晶硅间隔物技术制成的可能存在的缺陷问题。浮栅14a与字线栅38a之间的隔离(氧化物)可以被独立地优化，因为该氧化物最初形成为氧化物22，然后通过后续加工使该氧化物增厚。最后，隧道氧化物30形成为包绕在浮栅的锐利尖端周围的单个层，并且通过后续湿法氧化工艺使该隧道氧化物增厚。使用上述方法，可独立地优化擦除效率和字线栅性能。
应当理解，本发明不限于上述的和在本文中示出的实施方案，而是涵盖在任何权利要求书的范围内的任何和所有变型形式。举例来说，本文中对本发明的提及并不意在限制任何权利要求书或权利要求术语的范围，而是仅参考可由这些权利要求中的一项或多项权利要求涵盖的一个或多个特征。上文所述的材料、工艺和数值的示例仅为示例性的，而不应视为限制权利要求书。另外，并非所有方法步骤都需按照所示出或所要求的准确顺序执行，而是需要按照允许本发明的非易失性存储器单元正确形成的任何顺序执行。材料的单个层可形成为此类材料或类似材料的多个层，并且反之亦然。最后，如本文所用，术语“形成”和“形成的”应包括材料沉积、材料生长或用于提供所公开或要求保护的材料的任何其他技术。
应当指出的是，如本文所用，术语“在…上方”和“在…上”均包括性地包括“直接在…上”(之间没有设置中间材料、元件或空间)和“间接在…上”(之间设置有中间材料、元件或空间)。类似地，术语“相邻”包括“直接相邻”(之间没有设置中间材料、元件或空间)和“间接相邻”(之间设置有中间材料、元件或空间)，“被安装到”包括“被直接安装到”(之间没有设置中间材料、元件或空间)和“被间接安装到”(之间设置有中间材料、元件或空间)，并且“被电连接到”包括“被直接电连接到”(之间没有将元件电连接在一起的中间材料或元件)和“被间接电连接到”(之间有将元件电连接在一起的中间材料或元件)。例如，“在衬底上方”形成元件可包括在两者间无中间材料/元件的情况下直接在衬底上形成该元件，以及在两者间有一种或多种中间材料/元件的情况下间接在衬底上形成该元件。

Claims (18)

1.一种存储器设备，包括：
半导体衬底，所述半导体衬底具有间隔开的源极区和漏极区，其中所述衬底的沟道区在所述源极区与所述漏极区之间延伸；
多晶硅的浮栅，所述浮栅设置在所述沟道区的第一部分上方并且通过具有第一厚度的绝缘材料与所述第一部分绝缘，其中所述浮栅具有终止于锐利边缘的倾斜上表面；
多晶硅的字线栅，所述字线栅设置在所述沟道区的第二部分上方并且通过具有第二厚度的绝缘材料与所述第二部分绝缘；和
多晶硅的擦除栅，所述擦除栅设置在所述源极区上方并且通过具有第三厚度的绝缘材料与所述源极区绝缘，其中所述擦除栅包括包绕在所述浮栅的所述锐利边缘周围并与所述锐利边缘绝缘的凹口；
其中所述第三厚度大于所述第一厚度，并且其中所述第一厚度大于所述第二厚度。
2.根据权利要求1所述的存储器设备，其中：
具有所述第一厚度的所述绝缘材料为氧化物；
具有所述第二厚度的所述绝缘材料为氧化物；并且
具有所述第三厚度的所述绝缘材料为氧化物。
3.根据权利要求1所述的存储器设备，还包括：
绝缘材料间隔物，所述绝缘材料间隔物直接设置在所述浮栅上并在所述字线栅和所述擦除栅之间直接延伸。
4.根据权利要求1所述的存储器设备，还包括：
自对准多晶硅化物，所述自对准多晶硅化物形成在所述字线栅和所述擦除栅的上表面上。
5.根据权利要求1所述的存储器设备，其中：
所述擦除栅的所述凹口通过具有第四厚度的绝缘材料与所述浮栅的所述锐利边缘绝缘；并且
第二厚度小于所述第四厚度。
6.一种存储器设备，包括：
半导体衬底，所述半导体衬底具有源极区、第一漏极区和第二漏极区，其中所述衬底的第一沟道区在所述源极区与所述第一漏极区之间延伸，并且所述衬底的第二沟道区在所述源极区和所述第二漏极区之间延伸；
多晶硅的第一浮栅，所述第一浮栅设置在所述第一沟道区的第一部分上方并且通过具有第一厚度的绝缘材料与所述第一部分绝缘，其中所述第一浮栅具有终止于第一锐利边缘的倾斜上表面；
多晶硅的第二浮栅，所述第二浮栅设置在所述第二沟道区的第一部分上方并且通过具有所述第一厚度的绝缘材料与所述第一部分绝缘，其中所述第二浮栅具有终止于第二锐利边缘的倾斜上表面；
多晶硅的第一字线栅，所述第一字线栅设置在所述第一沟道区的第二部分上方并且通过具有第二厚度的绝缘材料与所述第二部分绝缘；
多晶硅的第二字线栅，所述第二字线栅设置在所述第二沟道区的第二部分上方并且通过具有第二厚度的绝缘材料与所述第二部分绝缘；和
多晶硅的擦除栅，所述擦除栅设置在所述源极区上方并且通过具有第三厚度的绝缘材料与所述源极区绝缘，其中所述擦除栅包括第一凹口和第二凹口，所述第一凹口包绕在所述第一浮栅的所述第一锐利边缘周围并与所述第一锐利边缘绝缘，所述第二凹口包绕在所述第二浮栅的所述第二锐利边缘周围并与所述第二锐利边缘绝缘；
其中所述第三厚度大于所述第一厚度，并且其中所述第一厚度大于所述第二厚度。
7.根据权利要求6所述的存储器设备，其中：
具有所述第一厚度的所述绝缘材料为氧化物；
具有所述第二厚度的所述绝缘材料为氧化物；并且
具有所述第三厚度的所述绝缘材料为氧化物。
8.根据权利要求6所述的存储器设备，还包括：
第一绝缘材料间隔物，所述第一绝缘材料间隔物直接设置在所述第一浮栅上并在所述第一字线栅和所述擦除栅之间直接延伸；
第二绝缘材料间隔物，所述第二绝缘材料间隔物直接设置在所述第二浮栅上并在所述第二字线栅和所述擦除栅之间直接延伸。
9.根据权利要求6所述的存储器设备，还包括：
自对准多晶硅化物，所述自对准多晶硅化物形成在所述第一字线栅和所述第二字线栅以及所述擦除栅的上表面上。
10.根据权利要求6所述的存储器设备，其中：
所述擦除栅的所述第一凹口和所述第二凹口分别通过具有第四厚度的绝缘材料与所述第一浮栅的所述第一锐利边缘和所述第二浮栅的所述第二锐利边缘绝缘；并且
第二厚度小于所述第四厚度。
11.一种形成存储器设备的方法，包括：
在半导体衬底上形成具有第一厚度的第一绝缘层；
在所述第一绝缘层上形成第一多晶硅层；
在所述第一多晶硅层上形成间隔开的第一绝缘间隔物和第二绝缘间隔物；
移除所述第一多晶硅层的部分，使得所述第一多晶硅层的第一块保持在所述第一绝缘间隔物下方，并且所述第一多晶硅层的第二块保持在所述第二绝缘间隔物下方，其中所述第一多晶硅层的所述第一块和所述第二块中的每一者具有终止于锐利边缘的倾斜上表面；
在所述衬底中形成源极区，所述源极区被设置在位于所述第一多晶硅层的所述第一块和所述第二块之间的间隙下方；
在所述半导体衬底上在所述源极区上方形成具有第二厚度的第二绝缘层；
在所述半导体衬底上形成具有第三厚度的第三绝缘层，所述第三绝缘层与所述第一多晶硅层的所述第一块和所述第二块的彼此背离的侧表面相邻；
在所述衬底以及所述第一绝缘间隔物和所述第二绝缘间隔物上方形成第二多晶硅层；
移除所述第二多晶硅层的部分，使得所述第二多晶硅层的第一块保持被设置在所述第二绝缘层上以及所述第一绝缘间隔物和所述第二绝缘间隔物之间，并且所述第二多晶硅层的第二块和第三块保持被设置在所述第三绝缘层上，其中所述第一绝缘间隔物被设置在所述第二多晶硅层的所述第一块和所述第二块之间，并且其中所述第二绝缘间隔物被设置在所述第二多晶硅层的所述第一块和所述第三块之间；
在与所述第二多晶硅层的所述第二块相邻的所述衬底中形成第一漏极区；以及
在与所述第二多晶硅层的所述第三块相邻的所述衬底中形成第二漏极区；
其中所述第二多晶硅层的所述第一块包括第一凹口和第二凹口，所述第一凹口包绕在所述第一多晶硅层的所述第一块的所述锐利边缘周围并与所述锐利边缘绝缘，所述第二凹口包绕在所述第一多晶硅层的所述第二块的所述锐利边缘周围并与所述锐利边缘绝缘；
其中所述第二厚度大于所述第一厚度，并且其中所述第一厚度大于所述第三厚度。
12.根据权利要求11所述的方法，还包括：
在所述第二多晶硅层的所述第一多晶硅块、所述第二多晶硅块和所述第三多晶硅块的上表面上形成自对准多晶硅化物。
13.根据权利要求11所述的方法，其中所述第一绝缘间隔物和所述第二绝缘间隔物的所述形成包括：
在所述第一多晶硅层上形成氮化物块；
在所述氮化物块上和所述第一多晶硅层上形成氧化物；
执行氧化物蚀刻以移除所述氧化物的除邻接所述氮化物块的侧表面的所述氧化物的所述第一绝缘间隔物和所述第二绝缘间隔物之外的部分；以及
移除所述氮化物块。
14.根据权利要求13所述的方法，其中所述第一多晶硅层的所述第一块和所述第二块的所述倾斜上表面通过以下方式形成：
在所述第一多晶硅层上形成氮化物块；
在所述第一多晶硅层的所述上表面上执行多晶硅蚀刻，使得所述第一多晶硅层的所述上表面在其接近所述氮化物块的侧壁时向上倾斜。
15.根据权利要求11所述的方法，其中所述第二多晶硅层的所述部分的所述移除包括化学机械抛光，所述化学机械抛光还移除所述绝缘间隔物的顶部部分。
16.根据权利要求15所述的方法，其中所述第二多晶硅层的所述部分的所述移除包括所述第二多晶硅层的光刻蚀刻。
17.根据权利要求11所述的方法，其中：
所述第一绝缘层为氧化物；
所述第二绝缘层为氧化物；并且
所述第三绝缘层为氧化物。
18.根据权利要求11所述的方法，其中：
所述第二多晶硅层的所述第一块的所述第一凹口和所述第二凹口分别通过具有第四厚度的绝缘材料与所述第一多晶硅层的所述第一块和所述第二块绝缘；并且
第三厚度小于所述第四厚度。
CN201980030337.8A 2018-05-09 2019-04-09 具有不同绝缘栅极氧化物的分裂栅闪存存储器单元及其形成方法 Active CN112074958B (zh)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201862669263P 2018-05-09 2018-05-09
US62/669,263 2018-05-09
US16/057,750 US10418451B1 (en) 2018-05-09 2018-08-07 Split-gate flash memory cell with varying insulation gate oxides, and method of forming same
US16/057,750 2018-08-07
PCT/US2019/026671 WO2019217022A1 (en) 2018-05-09 2019-04-09 Split-gate flash memory cell with varying insulation gate oxides, and method of forming same

Publications (2)

Publication Number Publication Date
CN112074958A true CN112074958A (zh) 2020-12-11
CN112074958B CN112074958B (zh) 2024-09-03

Family

ID=67909170

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201980030337.8A Active CN112074958B (zh) 2018-05-09 2019-04-09 具有不同绝缘栅极氧化物的分裂栅闪存存储器单元及其形成方法

Country Status (7)

Country Link
US (1) US10418451B1 (zh)
EP (1) EP3815149B1 (zh)
JP (1) JP7316302B2 (zh)
KR (1) KR102397576B1 (zh)
CN (1) CN112074958B (zh)
TW (1) TWI681543B (zh)
WO (1) WO2019217022A1 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112185970B (zh) 2019-07-02 2024-05-28 硅存储技术公司 形成分裂栅存储器单元的方法
CN112185815B (zh) 2019-07-04 2024-07-23 硅存储技术公司 形成分裂栅闪存存储器单元的方法
US11018147B1 (en) * 2020-02-04 2021-05-25 Silicon Storage Technology, Inc. Method of forming split gate memory cells with thinned tunnel oxide
US11362218B2 (en) * 2020-06-23 2022-06-14 Silicon Storage Technology, Inc. Method of forming split gate memory cells with thinned side edge tunnel oxide
CN114335186A (zh) * 2020-09-30 2022-04-12 硅存储技术股份有限公司 具有设置在字线栅上方的擦除栅的分裂栅非易失性存储器单元及其制备方法
US11462622B1 (en) * 2021-06-23 2022-10-04 Globalfoundries Singapore Pte. Ltd. Memory cells and methods of forming a memory cell
TW202329418A (zh) * 2022-01-11 2023-07-16 聯華電子股份有限公司 半導體記憶體元件

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050269622A1 (en) * 2004-06-07 2005-12-08 Pavel Klinger Semiconductor memory array of floating gate memory cells with program/erase and select gates, and methods of making and operating same
US20140217489A1 (en) * 2011-08-24 2014-08-07 SILICON STORAGE TECHNOLOGY. Inc. A method of making a split gate non-volatile floating gate memory cell having a separate erase gate, and a memory cell made thereby
US20150194519A1 (en) * 2014-01-08 2015-07-09 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
US20160254269A1 (en) * 2015-02-27 2016-09-01 Silicon Storage Technology, Inc. Array Of Non-volatile Memory Cells With ROM Cells
US20160336415A1 (en) * 2015-05-15 2016-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Memory cell structure for improving erase speed
US20170012049A1 (en) * 2015-07-10 2017-01-12 Silicon Storage Technology, Inc. Split Gate Non-volatile Memory Cell Having A Floating Gate, Word Line, Erase Gate, And Method Of Manufacturing
US20170117285A1 (en) * 2015-10-21 2017-04-27 Silicon Storage Technology, Inc. Method Of Forming Flash Memory With Separate Wordline And Erase Gates

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5029130A (en) 1990-01-22 1991-07-02 Silicon Storage Technology, Inc. Single transistor non-valatile electrically alterable semiconductor memory device
US5856943A (en) * 1996-03-18 1999-01-05 Integrated Memory Technologies, Inc. Scalable flash EEPROM memory cell and array
JP4222675B2 (ja) 1999-03-29 2009-02-12 三洋電機株式会社 不揮発性半導体記憶装置
US6727545B2 (en) 2000-09-20 2004-04-27 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling
US6952034B2 (en) 2002-04-05 2005-10-04 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with buried source line and floating gate
US6747310B2 (en) 2002-10-07 2004-06-08 Actrans System Inc. Flash memory cells with separated self-aligned select and erase gates, and process of fabrication
TWI284415B (en) * 2005-10-26 2007-07-21 Promos Technologies Inc Split gate flash memory cell and fabrication method thereof
US20090039410A1 (en) 2007-08-06 2009-02-12 Xian Liu Split Gate Non-Volatile Flash Memory Cell Having A Floating Gate, Control Gate, Select Gate And An Erase Gate With An Overhang Over The Floating Gate, Array And Method Of Manufacturing
US8878281B2 (en) 2012-05-23 2014-11-04 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for non-volatile memory cells
US9018690B2 (en) 2012-09-28 2015-04-28 Silicon Storage Technology, Inc. Split-gate memory cell with substrate stressor region, and method of making same
US20150213898A1 (en) 2014-01-27 2015-07-30 Silicon Storage Technololgy, Inc. Byte Erasable Non-volatile Memory Architecture And Method Of Erasing Same
US20150255614A1 (en) * 2014-03-05 2015-09-10 Powerchip Technology Corporation Split gate flash memory and manufacturing method thereof
KR102240022B1 (ko) * 2014-11-26 2021-04-15 삼성전자주식회사 반도체 장치 및 반도체 장치의 제조 방법
US9793281B2 (en) * 2015-07-21 2017-10-17 Silicon Storage Technology, Inc. Non-volatile split gate memory cells with integrated high K metal gate logic device and metal-free erase gate, and method of making same
US9859291B2 (en) 2015-08-03 2018-01-02 Iotmemory Technology Inc. Non-volatile memory and manufacturing method thereof
EP3371829B1 (en) * 2015-11-03 2020-11-25 Silicon Storage Technology, Inc. Integration of split gate non-volatile flash memory with finfet logic
WO2017184315A1 (en) 2016-04-20 2017-10-26 Silicon Storage Technology, Inc. Method of forming pairs of three-gate non-volatile flash memory cells using two polysilicon deposition steps

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050269622A1 (en) * 2004-06-07 2005-12-08 Pavel Klinger Semiconductor memory array of floating gate memory cells with program/erase and select gates, and methods of making and operating same
US20140217489A1 (en) * 2011-08-24 2014-08-07 SILICON STORAGE TECHNOLOGY. Inc. A method of making a split gate non-volatile floating gate memory cell having a separate erase gate, and a memory cell made thereby
US20150194519A1 (en) * 2014-01-08 2015-07-09 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
US20160254269A1 (en) * 2015-02-27 2016-09-01 Silicon Storage Technology, Inc. Array Of Non-volatile Memory Cells With ROM Cells
US20160336415A1 (en) * 2015-05-15 2016-11-17 Taiwan Semiconductor Manufacturing Co., Ltd. Memory cell structure for improving erase speed
US20170012049A1 (en) * 2015-07-10 2017-01-12 Silicon Storage Technology, Inc. Split Gate Non-volatile Memory Cell Having A Floating Gate, Word Line, Erase Gate, And Method Of Manufacturing
US20170117285A1 (en) * 2015-10-21 2017-04-27 Silicon Storage Technology, Inc. Method Of Forming Flash Memory With Separate Wordline And Erase Gates

Also Published As

Publication number Publication date
WO2019217022A1 (en) 2019-11-14
JP2021523566A (ja) 2021-09-02
US10418451B1 (en) 2019-09-17
TW201947741A (zh) 2019-12-16
KR102397576B1 (ko) 2022-05-12
JP7316302B2 (ja) 2023-07-27
TWI681543B (zh) 2020-01-01
CN112074958B (zh) 2024-09-03
EP3815149A4 (en) 2022-06-15
EP3815149A1 (en) 2021-05-05
EP3815149B1 (en) 2023-08-09
KR20200140312A (ko) 2020-12-15

Similar Documents

Publication Publication Date Title
CN112074958B (zh) 具有不同绝缘栅极氧化物的分裂栅闪存存储器单元及其形成方法
CN111418063B (zh) 具有集成高k金属控制栅的非易失性分裂栅存储器单元及制造方法
CN107112328B (zh) 具有同时形成的低电压逻辑器件和高电压逻辑器件的非易失性存储器阵列
US11652162B2 (en) Method of forming a three-gate non-volatile flash memory cell using two polysilicon deposition steps
US8928060B2 (en) Architecture to improve cell size for compact array of split gate flash cell
TWI600144B (zh) 使用增強橫向控制閘至浮閘耦合之改良尺度之分離閘快閃記憶體單元
KR101992590B1 (ko) 분리형-게이트, 트윈-비트 비휘발성 메모리 셀
CN111133515B (zh) 制造具有擦除栅极的分裂栅极闪存存储器单元的方法
US20210005725A1 (en) Method of Forming Split Gate Memory Cells
EP3994731B1 (en) Method of forming split-gate flash memory cell with spacer defined floating gate and discretely formed polysilicon gates
KR102017462B1 (ko) 낮은 높이의 분리형 게이트 메모리 셀들의 형성 방법
KR20230031334A (ko) 워드 라인 게이트 위에 배치된 소거 게이트를 갖는 스플릿 게이트, 2-비트 비휘발성 메모리 셀, 및 그 제조 방법
CN116058093A (zh) 利用薄型侧边缘隧道氧化物形成分裂栅极存储器单元的方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant