CN112071809A - 半导体装置 - Google Patents

半导体装置 Download PDF

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Publication number
CN112071809A
CN112071809A CN202010441462.2A CN202010441462A CN112071809A CN 112071809 A CN112071809 A CN 112071809A CN 202010441462 A CN202010441462 A CN 202010441462A CN 112071809 A CN112071809 A CN 112071809A
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source
pad
gate
layer
semiconductor device
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CN112071809B (zh
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大岳浩隆
近松健太郎
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Rohm Co Ltd
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Rohm Co Ltd
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Abstract

本发明提供一种谋求寄生电感的降低化的半导体装置。本发明的半导体装置(1)包含：半导体芯片(2)，具有正面(2a)及背面(2b)且在正面(2a)具有源极垫(11)、漏极垫(12)及栅极垫(13)；晶粒垫(3)，配置在半导体芯片(2)的下方，且接合着半导体芯片(2)的背面(2b)；源极引线(4)，电连接于晶粒垫(3)；漏极引线(5)及栅极引线(6)，配置在晶粒垫(3)的周围；以及密封树脂(8)，将半导体芯片(2)、晶粒垫(3)及各引线(4、5、6)密封。在半导体芯片(2)，形成着在俯视时配置在半导体芯片(2)的周缘部且连接于源极垫(11)的至少1个外部连接用通孔(60)。

Description

半导体装置
技术领域
本发明涉及一种半导体装置，例如涉及一种具备包含III族氮化物半导体(以下有时简称为“氮化物半导体”)的氮化物半导体芯片的半导体装置。
背景技术
所谓III族氮化物半导体，是指在III-V族半导体中使用氮作为V族元素的半导体。氮化铝(AlN)、氮化镓(GaN)、氮化铟(InN)为代表例。一般而言，可表示为AlxInyGa1-x-yN(0≦x≦1，0≦y≦1，0≦x+y≦1)。
提出有使用这种氮化物半导体的HEMT(High Electron Mobility Transistor；高电子迁移率晶体管)。这种HEMT例如包含：电子移行层，含有GaN；及电子供给层，外延生长在该电子移行层上且含有AlGaN。以与电子供给层相接的方式形成一对源极电极及漏极电极，在它们之间配置栅极电极。
由于GaN与AlGaN的晶格失配所引起的极化，而在电子移行层内，在距电子移行层与电子供给层的界面向内侧仅数
Figure BDA0002504313500000011
的位置，形成二维电子气(two dimensional electrongas)。以该二维电子气作为通道，源极、漏极间连接。如果通过对栅极电极施加控制电压而将二维电子气遮断，那么源极、漏极间被遮断。在未对栅极电极施加控制电压的状态下，源极、漏极间导通，所以成为常导通型(normally on type)器件。
使用氮化物半导体的器件由于具有高耐压、高温动作、大电流密度、高速切换及低导通电阻等特征，所以例如在专利文献1中提出应用于功率器件，目前这种概念的器件被量产，正在市场流通。
专利文献1揭示了如下构成：在AlGaN电子供给层上积层隆脊(ridge)形状的p型GaN栅极层(氮化物半导体栅极层)，且在该p型GaN栅极层上配置栅极电极，利用从所述p型GaN栅极层扩展的耗尽层使通道消失，由此达成常断开(normally off)。
[背景技术文献]
[专利文献]
[专利文献1]日本专利特开2017-73506号公报
发明内容
[发明要解决的问题]
作为半导体装置，已知有将氮化物半导体芯片上的源极垫、漏极垫及栅极垫利用金属导线分别连接于源极引线、漏极引线及栅极引线而成的构造。
然而，在这种构造中，半导体装置内部的寄生电感称不上足够低。因此，有漏极-源极间或栅极-源极间的电压电涌变大，而导致雪崩击穿、误动作、产生噪音等问题的担忧。
本发明的目的在于提供一种谋求寄生电感的降低化的半导体装置。
[解决问题的技术手段]
本发明的一实施方式提供一种半导体装置，包含：半导体芯片，具有正面及背面且在所述正面具有源极垫、漏极垫及栅极垫；晶粒垫，配置在所述半导体芯片的下方，且接合着所述半导体芯片的背面；源极引线，电连接于所述晶粒垫；漏极引线及栅极引线，配置在所述晶粒垫的周围；以及密封树脂，将所述半导体芯片、所述晶粒垫及所述各引线密封；在所述半导体芯片，形成着在俯视时配置在所述半导体芯片的周缘部且连接于所述源极垫的至少1个外部连接用通孔。
在该构成中，能够提供一种谋求寄生电感的降低化的半导体装置。
在本发明的一实施方式中，所述半导体芯片在背面侧包含衬底，所述外部连接用通孔电连接于所述衬底。
在本发明的一实施方式中，所述外部连接用通孔包含形成在所述半导体芯片的导孔、及形成在所述导孔内的导电膜。
在本发明的一实施方式中，所述晶粒垫与所述源极引线一体地形成。
在本发明的一实施方式中，所述漏极垫与所述漏极引线经由第1金属连接部件而连接，所述栅极垫与所述栅极引线经由第2金属连接部件而连接。
在本发明的一实施方式中，所述半导体芯片包含：所述衬底；第1氮化物半导体层，形成在所述衬底上，构成电子移行层；第2氮化物半导体层，形成在所述第1氮化物半导体层上，构成电子供给层；隆脊形状的栅极部，形成在所述第2氮化物半导体层上；以及源极电极及漏极电极，在所述第2氮化物半导体层上隔着所述栅极部对向配置；所述栅极部包含配置在所述第2氮化物半导体层上且包含受体型杂质的氮化物半导体栅极层、及配置在所述氮化物半导体栅极层上的栅极电极，所述源极电极电连接于所述源极垫，所述漏极电极电连接于所述漏极垫，所述栅极电极电连接于所述栅极垫。
在本发明的一实施方式中，在俯视时，所述外部连接用通孔与所述源极引线的距离比所述外部连接用通孔与所述漏极引线的距离更短且比所述外部连接用通孔与所述栅极引线的距离更短。
在本发明的一实施方式中，所述半导体芯片在俯视时为矩形，所述外部连接用通孔包含在俯视时沿着从所述半导体芯片的一个角向2个方向延伸的2条边中的至少1条边配置的外部连接用通孔。
在本发明的一实施方式中，所述外部连接用通孔还包含在俯视时沿着从相对于所述角处于对角线上的角向2个方向延伸的2条边中的至少1条边配置的外部连接用通孔。
在本发明的一实施方式中，还包含配置在所述晶粒垫的周围的驱动源极引线，所述源极垫与所述驱动源极引线经由第3金属连接部件而连接。
在本发明的一实施方式中，所述半导体芯片还包含：第1层间绝缘膜，形成在所述第2氮化物半导体层及所述栅极部上；第1源极配线，形成在所述第1层间绝缘膜上且连接于所述源极电极；第2层间绝缘膜，以覆盖所述第1源极配线的方式形成在所述第1层间绝缘膜上；第2源极配线，形成在所述第2层间绝缘膜上且连接于所述第1源极配线；以及第3层间绝缘膜，以覆盖所述第2源极配线的方式形成在所述第2层间绝缘膜上；所述源极垫形成在所述第3层间绝缘膜上且连接于所述第2源极配线。
在本发明的一实施方式中，所述导电膜与所述源极垫同时形成。
在本发明的一实施方式中，所述导孔的形成在所述衬底内的部分的至少一部分形成所述导孔的底部，所述导电膜包括形成在所述导孔中的除底部以外的部分的第1导电膜、及形成在所述导孔中的形成在所述底部的部分的第2导电膜，所述第1导电膜与所述第2导电膜的材料不同。
在本发明的一实施方式中，在所述导孔的侧面形成着绝缘膜。
在本发明的一实施方式中，所述导孔内表面具有在所述衬底内通过下侧的导孔直径小于上侧的导孔直径而产生的环状阶部。
在本发明的一实施方式中，所述导孔到达至衬底的背面。
附图说明
图1是用来说明本发明的一实施方式的半导体装置的构成的局部俯视图。
图2是沿着图1的II-II线的剖视图。
图3是沿着图1的III-III线的剖视图。
图4是用来说明半导体芯片的构成的剖视图，且是沿着图1的IV-IV线的局部放大剖视图。
图5是表示电极金属构造的图式性俯视图。
图6是将图5的一部分放大表示的局部放大俯视图。
图7是主要表示形成在第1层间绝缘膜上的第1层配线金属构造的图式性俯视图。
图8是主要表示形成在第2层间绝缘膜上的第2层配线金属构造的图式性俯视图。
图9是主要表示形成在第3层间绝缘膜上的第3层配线金属构造(垫构造)的图式性俯视图。
图10是表示半导体芯片的变化例的剖视图，且是与图4对应的剖视图。
图11是表示外部连接用通孔的配置图案的变化例的俯视图，且是与图1对应的剖视图。
图12是表示外部连接用通孔的配置图案的另一变化例的俯视图，且是与图1对应的剖视图。
图13是表示外部连接用通孔的配置图案的又一变化例的俯视图，且是与图1对应的剖视图。
图14是表示外部连接用通孔的配置图案的又一变化例的俯视图，且是与图1对应的剖视图。
图15是表示安装有半导体装置的配线衬底上的配线图案的一例的图解性俯视图。
图16是表示安装有半导体装置的配线衬底上的配线图案的另一例的图解性俯视图。
具体实施方式
以下，参照附图对本发明的实施方式详细地进行说明。
图1是用来说明本发明的一实施方式的半导体装置的构成的图解性俯视图。图2是沿着图1的II-II线的放大剖视图。图3是沿着图1的III-III线的放大剖视图。
为了方便说明，以下，有时使用图1、图2及图3所示的+X方向、-X方向、+Y方向及-Y方向。+X方向是在俯视时沿着半导体装置1的正面的指定方向，+Y方向是沿着半导体装置1的正面的方向，且是与+X方向正交的方向。-X方向是与+X方向相反的方向，-Y方向是与+Y方向相反的方向。将+X方向及-X方向总称时简称为“X方向”。将+Y方向及-Y方向总称时简称为“Y方向”。
半导体装置1具备半导体芯片(氮化物半导体芯片)2、晶粒垫3、2个源极引线4、4个漏极引线5、1个栅极引线6、1个驱动源极引线7、及密封树脂8。晶粒垫3及各引线4、5、6、7例如由包含铜或含有铜的合金的金属薄板构成。
晶粒垫3由俯视时在Y方向上为长方形的金属薄板构成。晶粒垫3用来支撑半导体芯片2。各引线4、5、6、7电连接于半导体芯片2。密封树脂8将半导体芯片2、晶粒垫3及各引线4、5、6、7密封。
半导体芯片2具有俯视时在Y方向上较长的矩形长方体形状。半导体芯片2在将正面2a朝向上方的状态下，晶粒接合在晶粒垫3的中央部上。具体来说，半导体芯片2的背面2b利用焊料9接合在晶粒垫3的上表面中央部。
在半导体芯片2的正面2a，形成着源极垫11、漏极垫12及栅极垫13。源极垫11形成在半导体芯片2的正面2a的-X方向侧半部分中的除-Y方向端部以外的区域的大致整个区域。栅极垫13形成在半导体芯片2的正面2a的-X方向侧半部分中的-Y方向端部。漏极垫12形成在半导体芯片2的正面2a的+X方向侧半部分的大致整个区域。
各引线4、5、6、7配置在晶粒垫3的周围。各引线4、5、6、7在俯视时形成为X方向上较长的长方形。各源极引线4与其它引线5、6、7相比，X方向的长度较长。
2个源极引线4与晶粒垫3一体地形成。2个源极引线4分别在俯视时，从晶粒垫3的-X方向侧边的+Y方向端部的在Y方向上不同的位置向-X方向延伸。各源极引线4在与晶粒垫3连结的+X方向端部，具有从Y方向观察时向上侧凸起的圆弧状弯曲部4a。
4个漏极引线5在俯视时，在从晶粒垫3的+X方向侧边向+X方向离开的位置，相互在Y方向上隔开间隔排列配置。各漏极引线5利用金属导线14连接于漏极垫12。
栅极引线6在俯视时，配置在从晶粒垫3的-X方向侧边的-Y方向侧端部向-X方向离开的位置。栅极引线6利用金属导线15连接于栅极垫13。
驱动源极引线7在俯视时，配置在-Y方向侧的源极引线4与栅极引线6之间的位置且从晶粒垫3的-X方向侧边向-X方向离开的位置。栅极引线6利用金属导线15连接于栅极垫13。
密封树脂8例如包含环氧树脂。密封树脂8为俯视时X方向上较长的长方形，且形成为上下方向上扁平的长方体形状。晶粒垫3的下表面从密封树脂8的下表面露出。各源极引线4的下表面除弯曲部4a以外，从密封树脂8的下表面露出。各漏极引线5的下表面、栅极引线6的下表面及驱动源极引线7的下表面从密封树脂8的下表面露出。
在半导体芯片2的周缘部，形成着电连接于源极垫11的多个外部连接用通孔60。多个外部连接用通孔60在俯视时，在半导体芯片的X方向侧边与+Y方向侧边的连接点即1个角C1的附近，沿着半导体芯片的X方向侧边及+Y方向侧边配置。如下所述，多个外部连接用通孔60连接于半导体芯片2的衬底21(参照图4)。源极垫11经由外部连接用通孔60、半导体芯片2的衬底21、半导体芯片2的背面电极34(参照图4)、焊料9及晶粒垫3而电连接于源极引线4。
在俯视时，各外部连接用通孔60与源极引线4的距离(最短距离)比该外部连接用通孔60与漏极引线5的距离更短且比该外部连接用通孔60与栅极引线6的距离更短。
图4是用来说明半导体芯片的构成的剖视图，且是沿着图1的IV-IV线的局部放大剖视图。图5是表示电极金属构造的图式性俯视图。图6是将图5的一部分放大表示的俯视图。图7是主要表示形成在第1层间绝缘膜上的第1层配线金属构造的图式性俯视图。图8是主要表示形成在第2层间绝缘膜上的第2层配线金属构造的图式性俯视图。图9是主要表示形成在第3层间绝缘膜上的第3层配线金属构造(垫构造)的图式性俯视图。
半导体芯片2包含半导体积层构造20、及配置在半导体积层构造20上的电极金属构造。另外，半导体芯片2包含形成在电极金属构造上的第1层间绝缘膜41、形成在第1层间绝缘膜41上的第1层配线金属构造、形成在第1层配线金属构造上的第2层间绝缘膜43、及形成在第2层间绝缘膜43上的第2层配线金属构造。进而，半导体芯片2包含形成在第2层配线金属构造上的第3层间绝缘膜45、及形成在第3层间绝缘膜45上的第3层配线金属构造(垫构造)。
如图4所示，半导体积层构造20包含衬底21、形成在衬底21的正面的缓冲层22、外延生长在缓冲层22上的第1氮化物半导体层23、及外延生长在第1氮化物半导体层23上的第2氮化物半导体层24。但是，第2氮化物半导体层24未形成在第1氮化物半导体层23的周缘部上。此外，与去除了第2氮化物半导体层24的区域对应的第1氮化物半导体层23的周缘部也可以将它的表层部去除。
衬底21在该实施方式中是低电阻的硅衬底。低电阻的硅衬底例如也可以为具有0.001Ωmm～0.5Ωmm(更具体来说为0.01Ωmm～0.1Ωmm左右)的电阻率的p型衬底。另外，衬底21除了低电阻的硅衬底以外，也可以为低电阻的SiC衬底、低电阻的GaN衬底等。衬底21的厚度在半导体工艺中例如为650μm左右，在芯片化的前阶段中，被研削为300μm以下程度。
缓冲层22在该实施方式中由积层多个氮化物半导体膜而成的多层缓冲层构成。在该实施方式中，缓冲层22包括：第1缓冲层(省略图示)，与衬底21的正面相接且包含AlN膜；以及第2缓冲层(省略图示)，积层在该第1缓冲层的正面(与衬底21相反侧的表面)且包含AlN/AlGaN超晶格层。第1缓冲层的膜厚为100nm～500nm左右。第2缓冲层的膜厚为500nm～2μm左右。缓冲层22例如也可以由AlGaN的单膜或复合膜构成。
第1氮化物半导体层23构成电子移行层。在该实施方式中，第1氮化物半导体层23包含GaN层，其厚度为0.5μm～2μm左右。另外，为了抑制在第1氮化物半导体层23中流通的漏电流，也可以在正面区域以外导入用来设为半绝缘性的杂质。在该情况下，杂质的浓度优选为4×1016cm-3以上。另外，杂质例如为C或Fe。
第2氮化物半导体层24构成电子供给层。第2氮化物半导体层24包含带隙比第1氮化物半导体层23更大的氮化物半导体。在该实施方式中，第2氮化物半导体层24包含Al组成比第1氮化物半导体层23更高的氮化物半导体。在氮化物半导体中，Al组成越高则带隙越大。在该实施方式中，第2氮化物半导体层24包含Alx1Ga1－x1N层(0＜x1＜1)，其厚度为5nm～15nm左右。
这样，第1氮化物半导体层(电子移行层)23与第2氮化物半导体层(电子供给层)24包含带隙(Al组成)不同的氮化物半导体，在它们之间产生了晶格失配。而且，由于第1氮化物半导体层23及第2氮化物半导体层24的自发极化及它们之间的晶格失配所引起的压电极化，使第1氮化物半导体层23与第2氮化物半导体层24的界面中的第1氮化物半导体层23的传导带的能量级别低于费米能级。由此，在第1氮化物半导体层23内，在接近第1氮化物半导体层23与第2氮化物半导体层24的界面的位置(例如距界面数
Figure BDA0002504313500000071
左右的距离)，二维电子气(2DEG)19扩展。
如图4、图5及图6所示，电极金属构造包含多个源极电极31、多个栅极电极32及多个漏极电极33。源极电极31及漏极电极33在X方向延伸。
栅极电极32包含相互平行地在X方向延伸的一对栅极主电极部32A、以及将这一对栅极主电极部32A的对应的端部彼此分别连结的2个基部32B。
1个源极电极31在俯视时以覆盖1个栅极电极32的一对栅极主电极部32A的方式形成。如图4及图6所示，源极电极31在俯视时包含配置在栅极电极32的一对栅极主电极部32A的长度中间部之间的源极主电极部31A、及源极主电极部31A周围的延长部31B。在该实施方式中，所谓源极主电极部31A，是指在俯视时源极电极31的整个区域中包含由源极接触孔27的轮廓包围的区域及它的周边区域的区域。在图5中，作为源极电极31，仅图示了源极主电极部31A。
延长部31B是指在俯视时源极电极31的整个区域中除源极主电极部31A以外的部分。延长部31B在俯视时覆盖栅极电极32的一对栅极主电极部32A及2个第2基部32B的一部分。
在1个源极电极31的两侧分别配置着漏极电极33。相邻的漏极电极33及源极主电极部31A在俯视时隔着栅极电极32的栅极主电极部32A相互对向。
在图4、图5及图6的示例中，源极主电极部31A(S)、栅极主电极部32A(G)及漏极电极33(D)在Y方向上按照DGSGDGS的顺序周期性地配置。由此，通过由源极主电极部31A(S)及漏极电极33(D)夹着栅极主电极部32A(G)而构成元件构造。
在第2氮化物半导体层24上，局部地形成着氮化物半导体栅极层(以下，称为“半导体栅极层”)25。半导体栅极层25通过外延生长而形成在第2氮化物半导体层24的正面。
半导体栅极层25在俯视时具有与栅极电极32大致相同的形状。具体来说，半导体栅极层25包含相互平行地在X方向延伸的一对隆脊部25A、以及将这一对隆脊部25A的对应的端部彼此分别连结的2个连结部25B。
栅极电极32形成在半导体栅极层25上。栅极电极32的一对栅极主电极部32A形成在半导体栅极层25的一对隆脊部25A上。栅极电极32的2个基部32B形成在半导体栅极层25的2个连结部25B上。
半导体栅极层25及栅极电极32分别在俯视时形成为环状(封闭曲线状)。如图4所示，由半导体栅极层25的隆脊部25A与形成在其上的栅极主电极部32A形成隆脊形状的栅极部30。
半导体栅极层25包含掺杂着受体型杂质的氮化物半导体。在该实施方式中，半导体栅极层25包含掺杂着受体型杂质的GaN层(p型GaN层)，其厚度为40nm～100nm左右。注入到半导体栅极层25的受体型杂质的浓度优选为1×1019cm-3以上。在该实施方式中，受体型杂质为Mg(镁)。受体型杂质也可以为Zn(锌)等除Mg以外的受体型杂质。
半导体栅极层25为了如下情况而设置，即，在栅极部30正下方的区域中，使第1氮化物半导体层23与第2氮化物半导体层24之间的界面中的传导带的能量级别变化，在不施加栅极电压的状态下，在栅极部30正下方的区域不产生二维电子气19。
在该实施方式中，栅极电极32由TiN层构成，其厚度为50nm～200nm左右。栅极电极32也可以由Ti、TiN及TiW中的任一种的单膜或包含它们中的2种以上的任意组合的复合膜构成。
如图4所示，在第2氮化物半导体层24上，形成着覆盖第2氮化物半导体层24的露出面及栅极部30的露出面的钝化膜26。因此，栅极部30的侧面及正面由钝化膜26覆盖。在该实施方式中，钝化膜26包含SiN膜，其厚度为50nm～200nm左右。钝化膜26也可以由SiN、SiO2及SiON中的任一种的单膜或包含它们中的2种以上的任意组合的复合膜构成。
在钝化膜26形成着源极接触孔27及漏极接触孔28。源极接触孔27及漏极接触孔28以隔着栅极部30的配置而形成。
源极电极31的源极主电极部31A的一部分进入到源极接触孔27内，在源极接触孔27内与第2氮化物半导体层24接触。如图6所示，源极电极31的延长部31B覆盖以隔着该源极电极31的源极主电极部31A的方式配置的一对栅极部30。源极电极31的延长部31B的一部分覆盖栅极电极32的基部32B的一部分。漏极电极33的一部分进入到漏极接触孔28内，在漏极接触孔28内与第2氮化物半导体层24接触。
源极电极31及漏极电极33例如包含与第2氮化物半导体层24相接的第1金属层(欧姆金属层)、积层在第1金属层的第2金属层(主电极金属层)、积层在第2金属层的第3金属层(密接层)、及积层在第3金属层的第4金属层(阻挡金属层)。第1金属层例如是厚度为10nm～20nm左右的Ti层。第2金属层例如是厚度为100nm～300nm左右的含有Al的层。第3金属层例如是厚度为10nm～20nm左右的Ti层。第4金属层例如是厚度为10nm～50nm左右的TiN层。
在第1氮化物半导体层23的露出面上及钝化膜26上，以覆盖源极电极31及漏极电极33的方式，形成着第1层间绝缘膜41。第1层间绝缘膜41上的第1层配线金属构造如图4及图7所示，包含在Y方向延伸的第1源极配线金属51(S1)及第1漏极配线金属52(D1)。在图7的示例中，第1源极配线金属51及第1漏极配线金属52在X方向上交替地排列配置。第1源极配线金属51及第1漏极配线金属52与源极电极31、栅极电极32及漏极电极33正交。
第1源极配线金属51经由贯通第1层间绝缘膜41的第1源极通孔42，电连接于与该第1源极配线金属51正交的多个源极电极31。第1漏极配线金属52经由贯通第1层间绝缘膜41的未图示的第1漏极通孔，电连接于与该第1漏极配线金属52正交的多个漏极电极33。
在第1层间绝缘膜41上，以覆盖第1源极配线金属51及第1漏极配线金属52的方式，形成着第2层间绝缘膜43。第2层间绝缘膜43上的第2层配线金属构造如图4及图8所示，包含在X方向延伸的第2源极配线金属53(S2)及第2漏极配线金属54(D2)。在图8的示例中，第2源极配线金属53及第2漏极配线金属54在Y方向上交替地排列配置。第2源极配线金属53及第2漏极配线金属54与第1源极配线金属51及第1漏极配线金属52正交。
第2源极配线金属53经由贯通第2层间绝缘膜43的第2源极通孔44，电连接于与该第2源极配线金属53正交的第1源极配线金属51。第2漏极配线金属54经由贯通第2层间绝缘膜43的第2漏极通孔(省略图示)，电连接于与该第2漏极配线金属54正交的多个第1漏极配线金属52。
在第2层间绝缘膜43上，以覆盖第2源极配线金属53及第2漏极配线金属54的方式，形成着第3层间绝缘膜45。在半导体积层构造20及第1～第3层间绝缘膜41、43、45，形成着多个导孔61，所述导孔61贯通第3层间绝缘膜45、第2层间绝缘膜43、第1层间绝缘膜41、第2氮化物半导体层24、第1氮化物半导体层23及缓冲层22，且到达至衬底21内部。关于导孔61的详细情况将在下文叙述。在第3层间绝缘膜45的正面上及多个导孔61的侧面上，形成着绝缘膜46。绝缘膜46例如包含SiN等绝缘膜。
第3层间绝缘膜45上的第3层配线金属构造如图4及图9所示，包含在Y方向延伸的源极垫11(第3源极配线金属S3)及漏极垫12(第3漏极配线金属D3)。虽然在图4及图9中的任一图中均未图示，但第3层的配线金属构造包含如图1所示的栅极垫13。
此外，图9所示的源极垫11及漏极垫12的大小及配置位置不对应于图1所示的源极垫11及漏极垫12。源极垫11及漏极垫12相对于半导体芯片2正面的大小比率及配置位置在图1中准确地呈现。
源极垫11及漏极垫12与第2源极配线金属53及第2漏极配线金属54正交。源极垫11经由贯通绝缘膜46及第3层间绝缘膜45的第3源极通孔47，电连接于与源极垫11正交的多个第2源极配线金属53。漏极垫12经由贯通绝缘膜46及第3层间绝缘膜45的未图示的第3漏极通孔，电连接于与漏极垫12正交的多个第2漏极配线金属54。栅极垫13经由形成在半导体芯片2内部的未图示的栅极配线电连接于所有栅极电极32。
第1层间绝缘膜41、第2层间绝缘膜43及第3层间绝缘膜45例如含有SiO2。第1源极配线金属51、第1漏极配线金属52、第2源极配线金属53、第2漏极配线金属54、源极垫11、漏极垫12及栅极垫13例如含有AlCu。
在该实施方式中，多个导孔61在俯视时形成在源极垫11的内侧区域且半导体芯片2的第1角C1(参照图1)的附近区域。更具体来说，在俯视时，多个导孔61包含沿着半导体芯片2的与第1角C1相邻的2条边中的一条边形成的多个导孔61、及沿着另一条边形成的多个导孔61。
在该实施方式中，导孔61的横截面形状为正方形。导孔61的横截面形状也可以为像圆形、长方形等一样除正方形以外的形状。在该实施方式中，导孔61包含从第3层间绝缘膜45的正面挖掘至衬底21的表层部内为止的第1部分61A、及从第1部分61A的底面的中央部朝向衬底21的背面挖掘的第2部分61B。
第1部分61A的4个侧面形成为第1部分61A的横截面积朝向下方逐渐变小的倾斜面。第2部分61B的4个侧面也形成为第2部分61B横截面积朝向下方逐渐变小的倾斜面。在俯视时，第2部分61B上端的横截面的4条边分别比第1部分61A下端的横截面的对向的边更向内侧后退。由此，在第1部分61A的侧面下端与第2部分61B的侧面上端之间形成着矩形环状阶部61C。
在导孔61内的绝缘膜46上，形成着导电膜62。此外，形成在导孔61的侧面的绝缘膜55为了如下情况而设置，即，将有可能存在绝缘不充分的部位的缓冲层22与导电膜62绝缘，从而抑制在导电膜62中流通的电流泄漏到缓冲层22。
导电膜62例如含有AlCu。导电膜62的上端部与源极垫11连接，导电膜62的下部连接于衬底21。由导孔61与导电膜62构成将源极垫11连接于衬底21的外部连接用通孔60。在该实施方式中，源极垫11与导孔61内的导电膜62在相同的制造工序中同时形成。
在衬底21的背面21b，形成着背面电极34。背面电极34例如包含Ni、Ag、Ti或Au及它们中的2个以上的组合等。
在该半导体芯片2中，在第1氮化物半导体层(电子移行层)23上形成带隙(Al组成)不同的第2氮化物半导体层(电子供给层)24而形成异质结。由此，在第1氮化物半导体层23与第2氮化物半导体层24的界面附近的第1氮化物半导体层23内形成二维电子气19，且形成着将该二维电子气19用作通道的HEMT。栅极电极32的栅极主电极部32A隔着半导体栅极层25的隆脊部25A与第2氮化物半导体层24对向。
在栅极主电极部32A的下方，利用包含p型GaN层的隆脊部24A中所包含的离子化受体，第1氮化物半导体层23及第2氮化物半导体层24的能量级别被提升。因此，第1氮化物半导体层23与第2氮化物半导体层24之间的异质结界面中的传导带的能量级别大于费米能级。因此，在栅极主电极部32A(栅极部30)的正下方，不会形成第1氮化物半导体层23及第2氮化物半导体层24的自发极化以及因它们的晶格失配所致的压电极化所引起的二维电子气19。
因此，当未对栅极电极32施加偏压时(零偏压时)，由二维电子气19所形成的通道在栅极主电极部32A的正下方被遮断。这样一来，实现了常断开型HEMT。如果对栅极电极32施加适当的导通电压(例如5V)，那么在栅极主电极部32A正下方的第1氮化物半导体层23内诱发通道，将栅极主电极部32A两侧的二维电子气19连接。由此，源极-漏极间导通。
在使用时，例如，对源极电极31与漏极电极33之间施加漏极电极33侧成为正的指定电压(例如50V～100V)。在该状态下，将源极电极31设为基准电位(0V)，对栅极电极32施加断开电压(0V)或导通电压(5V)。
在所述半导体装置1中，源极电极31经由第1源极通孔42、第1源极配线金属51、第2源极通孔44、第2源极配线金属53及第3源极通孔47而连接于源极垫11。源极垫11经由外部连接用通孔60、衬底21、背面电极34及晶粒垫3而连接于作为外部源极端子的源极引线4。
因此，与将源极垫11利用金属导线连接于源极引线4的情况相比，能够降低半导体装置1内的寄生电感。
另外，外部连接用通孔60在俯视时，形成在半导体芯片2中的最接近源极引线4的角C1附近。由此，当在源极引线4与漏极引线5之间经由外部连接用通孔60流通主电流时，能够限制主电流路径。由此，能够抑制在半导体芯片2正下方流通的电流的电位分布形成，所以能够抑制栅极阈值电压或电流崩溃(collapse)等特性变动，从而能够实现稳定的动作。
在所述实施方式中，在导孔61的第1部分61A的侧面及导孔61的第2部分61B的侧面形成着绝缘膜46，但也可以不在第2部分61B的侧面形成绝缘膜46。
另外，在所述实施方式中，形成在第1部分61A内的导电膜(以下，称为“第1导电膜”)与形成在第2部分61B内的导电膜(以下，称为“第2导电膜”)为相同材料，但它们也可以为不同材料。例如，也可以为第1导电膜由与源极垫11相同的AlCu构成，第2导电膜由与Si衬底21欧姆连接的Ni构成。如果这样，那么能够降低从源极垫11到背面电极34为止的主电流路径的电阻。
图10是表示半导体芯片的变化例的剖视图，且是与图4对应的剖视图。在图10中，对与图4的各部对应的部分，标注与图4相同的符号来表示。
在该半导体芯片2A中，外部连接用通孔60贯通衬底21，并连接于背面电极34。具体来说，在该半导体芯片2A中，导孔61贯通衬底21。更具体来说，导孔61的第2部分61B贯通衬底21。在导孔61的侧面整体形成着绝缘膜46，在绝缘膜46上形成着导电膜62。导电膜62的下端连接于背面电极34。
在图10的半导体芯片2A中，能够降低从源极垫11到背面电极34为止的主电流路径的电阻。
在图10的半导体芯片2A中，在第1部分61A及第2部分61B的侧面形成着绝缘膜46，但也可以不在第2部分61B的侧面形成绝缘膜46。另外，形成在第1部分61A内的第1导电膜与形成在第2部分61B内的第2导电膜也可以由不同材料构成。也可以为第1导电膜由AlCu构成，第2导电膜由与Si衬底21欧姆连接的Ni构成。
图11～图14分别是表示外部连接用通孔60的配置图案的变化例的俯视图，且是与图1对应的剖视图。在图11～图14中，对与图1的各部对应的部分，标注与图1相同的符号来表示。
在图11的半导体装置1A中，多个外部连接用通孔60仅沿着半导体芯片2的与第1角C1相邻的2条边中的-X方向侧的一边形成。
在图12的半导体装置1B中，多个外部连接用通孔60仅沿着半导体芯片2的与第1角C1相邻的2条边中的+Y侧方向侧的一边形成。
图13的半导体装置1C的漏极垫12C具有将图1的半导体装置1的漏极垫12的+Y方向侧端部切除而成的形状。因此，在图13的半导体装置1C中，在俯视时，半导体芯片2的+Y方向侧边与漏极垫12C的+Y方向侧边的间隔与图1的半导体装置1相比变大。
图13的半导体装置1C的源极垫11C具有与图1的半导体装置1的漏极垫12相同的源极垫本体部11Ca、及从源极垫本体部11Ca的+X方向侧边中的+Y方向侧端部向+X方向延伸的延长部11Cb。延长部11Cb从源极垫本体部11Ca的+X方向侧边中的+Y方向侧端部延伸到半导体芯片2的+Y方向侧边与漏极垫12C的+Y方向侧边之间的区域。
在图13的半导体装置1C中，形成着与图1的半导体装置1相同的多个外部连接用通孔60，并且俯视时在延长部11Cb内在X方向上隔开间隔地形成着多个外部连接用通孔60。
图14的半导体装置1D的漏极垫12D具有将图1的半导体装置1的漏极垫12的-Y方向侧端部切除而成的形状。切除部的Y方向长度为栅极垫13的Y方向长度的2倍左右。由此，在俯视时，在相对于半导体芯片2的第1角C1处于对角线上的第2角C2附近形成着未形成漏极垫12D的切除区域。
图14的半导体装置1D的源极垫11D具有与图1的半导体装置1的漏极垫12相同的源极垫本体部11Da、及从源极垫本体部11Da的+X方向侧边中的-Y方向侧端部向+X方向延伸且覆盖切除区域的大致整个区域的延长部11Db。
在图14的半导体装置1D中，形成着与图1的半导体装置1相同的多个外部连接用通孔60，并且在俯视时，在半导体芯片2的第2角C2附近，沿着与第2角C2相邻的2条边分别形成着多个外部连接用通孔60。
图15是表示安装有半导体装置1的配线衬底上的配线图案的一例的图解性俯视图。在图15中，对与图1的各部对应的部分，标注与图1相同的符号来表示。但是，为了方便说明，省略了半导体芯片2。
在配线衬底70上，作为配线图案，形成着源极导体层71、漏极导体层72、栅极导体层73及驱动源极导体层74。源极导体层71包含在俯视时在Y方向上较长的长方形的第1部分71A、及从第1部分71A的-X方向侧边的+Y方向侧半部分向-X方向延伸且在俯视时在X方向上较长的长方形的第2部分71B。在俯视时，第2部分71B的包含-X方向侧端部在内的大半部分从半导体装置1的-X方向侧边向-X方向突出。在第1部分71A的正面接合着晶粒垫3的下表面，在第2部分71B的正面的+X方向侧缘部上，接合着2个源极引线4的下表面。
漏极导体层72为在俯视时Y方向上较长的长方形，相对于源极导体层71向+X方向侧隔开间隔而配置。在俯视时，漏极导体层72的包含+X方向侧的侧部在内的大半部分从半导体装置1的+X方向侧边向+X方向突出。在漏极导体层72的-X方向侧缘部上，接合着4个漏极引线5的下表面。
驱动源极导体层74为在俯视时X方向上较长的长方形，与源极导体层71的第2部分71B的-Y方向侧隔开间隔地配置。在俯视时，驱动源极导体层74的包含-X方向侧端部在内的大半部分从半导体装置1的-X方向侧边向-X方向突出。在驱动源极导体层74正面的X方向侧端部上，接合着驱动源极引线7。
栅极导体层73包含在俯视时配置在驱动源极引线7的-Y方向侧且在Y方向上较长的长方形的第1部分73A、及从第1部分73A的-X方向侧边的-Y方向侧端向-X方向延伸且在俯视时在X方向上较长的长方形的第2部分73B。在俯视时，第1部分73A的-Y方向侧端部从半导体装置1的-Y方向侧边向-Y方向突出。在第1部分73A正面的X方向侧半部分上接合着栅极引线6的下表面。
在使用这种配线图案的情况下，主电流像图15中箭头A所示那样沿X方向流动。在这种情况下，作为外部连接用通孔60的配置图案，优选为使用在主电流路径上形成着较多外部连接用通孔60的图11的配置图案。
图16是表示安装有半导体装置1的配线衬底上的配线图案的另一例的图解性俯视图。在图16中，对与图15的各部对应的部分，标注与图15相同的符号来表示。但是，在图16中，对源极导体层标注与图15不同的符号171来表示。
在图16中，源极导体层171的形状与图15的源极导体层71的形状不同。源极导体层171于在配线衬底70上安装着半导体装置1的状态下，包含在俯视时配置在半导体装置1内侧的内侧部分171A、及在俯视时配置在半导体装置1外侧的外侧部分171B。
内侧部分171A包含Y方向上较长的长方形的第1部分171Aa、及从第1部分171Aa的-X方向侧边的+Y方向侧半部分向-X方向延伸且在俯视时Y方向上较长的长方形的第2部分171Ab。在第1部分171Aa的正面接合着晶粒垫3的下表面，在第2部分171Ab的正面接合着2个源极引线4的下表面。
外侧部分171B包含从内侧部分171A的+Y方向侧缘的整个区域向+Y方向延伸且在俯视时X方向上较长的长方形的第3部分171Ba、及从第3部分171Ba的除+X方向侧缘的-Y方向侧端部以外的区域向X方向突出的第4部分171Bb。
在使用这种配线图案的情况下，主电流像图16中箭头A所示那样，在俯视时呈L字状流动。具体来说，在源极导体层171内主电流沿Y方向流动，在漏极导体层72内主电流沿X方向流动。在这种情况下，作为外部连接用通孔60的配置图案，优选为使用在主电流路径上形成着较多外部连接用通孔60的图12的配置图案。
根据图15及图16的说明可知，半导体装置1优选为以主电流在形成着外部连接用通孔60的附近流动的方式连接于配线衬底70。因此，在外部连接用通孔60像图1所示那样形成在半导体芯片2的第1角C1附近的情况下，不优选以主电流横穿半导体装置1的-Y方向侧边而流动的方式将半导体装置1连接于配线衬底70。因此，为了提醒使用者注意该情况，也可以像图1中双点划线所示那样，在晶粒垫3的-Y方向侧边附近形成在俯视时X方向上细长的长方形的开口部3a。由此，能够抑制在半导体芯片2正下方流动的电流的电位分布形成，所以能够抑制栅极阈值电压或电流崩溃等特性变动，从而能够实现稳定的动作。
此外，能够在权利要求书所记载的事项的范围内实施各种设计变更。
[符号的说明]
1、1A、1B、1C、1D 半导体装置
2、2A 半导体芯片
3 晶粒垫
3a 开口部
4 源极引线
5 漏极引线
6 栅极引线
7 驱动源极引线
8 密封树脂
9 焊料
11 源极垫
12 漏极垫
13 栅极垫
14、15、16 金属导线
19 二维电子气
20 半导体积层构造
21 衬底
22 缓冲层
23 第1氮化物半导体层(电子移行层)
24 第2氮化物半导体层(电子供给层)
25 氮化物半导体栅极层
25A 隆脊部
25B 连结部
26 钝化膜
27 源极接触孔
28 漏极接触孔
30 栅极部
31 源极电极
31A 源极主电极部
31B 延长部
32 栅极电极
32A 栅极主电极部
32B 基部
33 漏极电极
34 背面电极
41、43、45 层间绝缘膜
42、44、47 源极通孔
46 绝缘膜
51 第1源极配线金属
52 第1漏极配线金属
53 第2源极配线金属
54 第2漏极配线金属
60 外部连接用通孔
61 导孔
61A 第1部分
61B 第2部分
62 导电膜

Claims (16)

1.一种半导体装置，包含：
半导体芯片，具有正面及背面且在所述正面具有源极垫、漏极垫及栅极垫；
晶粒垫，配置在所述半导体芯片的下方，且接合着所述半导体芯片的背面；
源极引线，电连接于所述晶粒垫；
漏极引线及栅极引线，配置在所述晶粒垫的周围；以及
密封树脂，将所述半导体芯片、所述晶粒垫及所述各引线密封；
在所述半导体芯片，形成着在俯视时配置在所述半导体芯片的周缘部且连接于所述源极垫的至少1个外部连接用通孔。
2.根据权利要求1所述的半导体装置，其中所述半导体芯片在背面侧包含衬底，
所述外部连接用通孔电连接于所述衬底。
3.根据权利要求2所述的半导体装置，其中所述外部连接用通孔包含形成在所述半导体芯片的导孔、及形成在所述导孔内的导电膜。
4.根据权利要求2或3所述的半导体装置，其中所述晶粒垫与所述源极引线一体地形成。
5.根据权利要求2至4中任一项所述的半导体装置，其中所述漏极垫与所述漏极引线经由第1金属连接部件而连接，
所述栅极垫与所述栅极引线经由第2金属连接部件而连接。
6.根据权利要求2至5中任一项所述的半导体装置，其中所述半导体芯片包含：
所述衬底；
第1氮化物半导体层，形成在所述衬底上，构成电子移行层；
第2氮化物半导体层，形成在所述第1氮化物半导体层上，构成电子供给层；
隆脊形状的栅极部，形成在所述第2氮化物半导体层上；以及
源极电极及漏极电极，在所述第2氮化物半导体层上隔着所述栅极部对向配置；
所述栅极部包含配置在所述第2氮化物半导体层上且包含受体型杂质的氮化物半导体栅极层、及配置在所述氮化物半导体栅极层上的栅极电极，
所述源极电极电连接于所述源极垫，
所述漏极电极电连接于所述漏极垫，
所述栅极电极电连接于所述栅极垫。
7.根据权利要求2至6中任一项所述的半导体装置，其中在俯视时，所述外部连接用通孔与所述源极引线的距离比所述外部连接用通孔与所述漏极引线的距离更短且比所述外部连接用通孔与所述栅极引线的距离更短。
8.根据权利要求2至6中任一项所述的半导体装置，其中所述半导体芯片在俯视时为矩形状，
所述外部连接用通孔包含在俯视时沿着从所述半导体芯片的一个角向2个方向延伸的2条边中的至少1条边配置的外部连接用通孔。
9.根据权利要求8所述的半导体装置，其中所述外部连接用通孔还包含在俯视时沿着从相对于所述角处于对角线上的角向2个方向延伸的2条边中的至少1条边配置的外部连接用通孔。
10.根据权利要求2至9中任一项所述的半导体装置，其还包含配置在所述晶粒垫的周围的驱动源极引线，
所述源极垫与所述驱动源极引线经由第3金属连接部件而连接。
11.根据权利要求6所述的半导体装置，其中所述半导体芯片还包含：
第1层间绝缘膜，形成在所述第2氮化物半导体层及所述栅极部上；
第1源极配线，形成在所述第1层间绝缘膜上且连接于所述源极电极；
第2层间绝缘膜，以覆盖所述第1源极配线的方式形成在所述第1层间绝缘膜上；
第2源极配线，形成在所述第2层间绝缘膜上且连接于所述第1源极配线；以及
第3层间绝缘膜，以覆盖所述第2源极配线的方式形成在所述第2层间绝缘膜上；
所述源极垫形成在所述第3层间绝缘膜上且连接于所述第2源极配线。
12.根据权利要求3所述的半导体装置，其中所述导电膜与所述源极垫同时形成。
13.根据权利要求3所述的半导体装置，其中所述导孔的形成在所述衬底内的部分的至少一部分形成所述导孔的底部，
所述导电膜包括形成在所述导孔中的除底部以外的部分的第1导电膜、及形成在所述导孔中的形成在所述底部的部分的第2导电膜，
所述第1导电膜与所述第2导电膜的材料不同。
14.根据权利要求3所述的半导体装置，其中在所述导孔的侧面形成着绝缘膜。
15.根据权利要求3所述的半导体装置，其中所述导孔内表面具有在所述衬底内通过下侧的导孔直径小于上侧的导孔直径而产生的环状阶部。
16.根据权利要求3所述的半导体装置，其中所述导孔到达至衬底的背面。
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