CN112038339A - 高介电金属栅极mosfet结构及其制造方法 - Google Patents

高介电金属栅极mosfet结构及其制造方法 Download PDF

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CN112038339A
CN112038339A CN202010861216.2A CN202010861216A CN112038339A CN 112038339 A CN112038339 A CN 112038339A CN 202010861216 A CN202010861216 A CN 202010861216A CN 112038339 A CN112038339 A CN 112038339A
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pmos
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白文琦
黄志森
胡展源
张瑜
杨会山
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2

Abstract

本申请提供高介电金属栅极MOSFET结构，在形成P型功函数层之后增加一层中间阻挡层，之后在去除NMOS区域的P型功函数层的同时去除NMOS区域的中间阻挡层，而保留位于PMOS区域的P型功函数层和中间阻挡层，之后形成NMOS区域和PMOS区域的N型功函数层及金属栅，如此PMOS的中间阻挡层可在顶部阻挡层的基础上进一步阻挡金属栅的金属向P型功函数层中扩散，从而防止P型功函数层的功函数的大小产生偏移，另PMOS的中间阻挡层位于其P型功函数层与N型功函数层之间，N型功函数层的材料通常为TiAl，因此本发明更可通过中间阻挡层阻挡PMOS的的N型功函数层的Al成份向P型功函数层中扩散，而进一步防止P型功函数层的功函数的大小产生偏移。

Description

高介电金属栅极MOSFET结构及其制造方法
技术领域
本申请涉及半导体集成电路技术，具体涉及高介电金属栅极MOSFET结构。
背景技术
在半导体集成电路领域，随着技术的发展，CMOS组件特征尺寸不断缩小，栅氧化层的厚度不断微缩。然而栅氧化层厚度过薄会引发载流子隧穿效应明显，导致栅极漏电流迅速增加。
高介电金属栅极结构为包括高介电常数层和金属栅的栅极结构，通常缩写为HKMG，可有效增加栅氧化层的物理厚度，从而大幅降低栅氧化层的漏电流。由于高介电氧化物与半导体衬底如硅衬底之间存在费米钉扎效应等界面问题，栅极材料须选择金属，因此，栅极与硅基底之间的功函数差会受到金属材料功函数的影响。所述金属栅的材料包括Al，Al原子在金属栅极中的扩散会导致MOSFET器件的阈值电压难以控制。
发明内容
本申请一实施例提供一种高介电金属栅极MOSFET结构，包括：半导体衬底，半导体衬底包括NMOS形成区域和PMOS形成区域，在半导体衬底的NMOS形成区域的表面形成有NMOS的高介电金属栅极结构，在半导体衬底的PMOS形成区域的表面形成有PMOS的高介电金属栅极结构，高介电金属栅极结构之间填充有层间介质层，其中NMOS的高介电金属栅极结构包括依次叠加的界面层、高介电常数层和底部阻挡层构成的栅介质层，形成于栅介质层之上的N型功函数层，叠加于N型功函数层之上的顶部阻挡层，形成于顶部阻挡层之上的金属栅；PMOS的高介电金属栅极结构包括依次叠加的界面层、高介电常数层和底部阻挡层构成的栅介质层，形成于栅介质层之上的P型功函数层,叠加于P型功函数层之上的中间阻挡层，叠加于中间阻挡层之上的N型功函数层，叠加于N型功函数层之上的顶部阻挡层，形成于顶部阻挡层之上的金属栅。
根据一些实施例，所述P型功函数层的材料为TiN，所述N型功函数层的材料为TiAl。
根据一些实施例，所述中间阻挡层的材料为金属氮化物。
根据一些实施例，所述中间阻挡层厚度为5埃米至40埃米之间。
根据一些实施例，NMOS的N型功函数层包覆金属栅的底部和侧面，顶部阻挡层叠加于N型功函数层之上。
根据一些实施例，PMOS的P型功函数层包覆金属栅的底部和侧面，中间阻挡层叠加于P型功函数层之上，N型功函数层叠加于中间阻挡层之上，顶部阻挡层叠加于N型功函数层之上。
本申请一实施例还提供一种高介电金属栅极MOSFET结构的形成方法，包括：S1：提供半导体衬底，半导体衬底包括NMOS形成区域和PMOS形成区域，采用伪多晶硅栅的工艺方法在半导体衬底上完成金属栅之前的工艺，而在半导体衬底的NMOS形成区域的表面形成NMOS的多晶硅栅极结构，在半导体衬底的PMOS形成区域的表面形成PMOS的多晶硅栅极结构，多晶硅栅极结构之间填充有层间介质层，其中各多晶硅栅极结构包括依次叠加的界面层、高介电常数层和底部阻挡层构成的栅介质层，形成于栅介质层之上多晶硅栅；S2：去除多晶硅栅；S3：形成第一功函数层，所述第一功函数覆盖在各所述多晶硅栅去除区域的侧面和底部表面并延伸到所述多晶硅栅去除区域之外，在第一功函数层之上叠加形成第一阻挡层；S4：去除部分的所述第一功函数层和所述第一阻挡层，保留位于PMOS的多晶硅栅去除区域的第一功函数层和第一阻挡层，而由第一功函数层形成PMOS的P型功函数层，由第一阻挡层形成PMOS的中间阻挡层，其中PMOS的中间阻挡层可阻挡金属通过中间阻挡层向PMOS的P型功函数层中扩散；S5：形成第二功函数层，并刻蚀保留位于NMOS的多晶硅栅去除区域的底部和侧面的第二功函数层及叠加于中间阻挡层之上的第二功函数层，而形成NMOS的N型功函数层和PMOS的N型功函数层；S6：在NMOS的N型功函数层上叠加形成顶部阻挡层，并同时在PMOS的N型功函数层上叠加形成顶部阻挡层；以及S7：形成金属层，金属层将多晶硅栅去除区域完全填充，并进行平坦化，形成NMOS的金属栅和PMOS的金属栅。
根据一些实施例，所述第一功函数层为P型功函数层。
根据一些实施例，所述第一阻挡层的材料为金属氮化物。
根据一些实施例，所述中间阻挡层厚度为5埃米至40埃米之间。
本申请实施例提供的技术方案，在形成P型功函数层之后增加一层中间阻挡层，之后在去除NMOS区域的P型功函数层的同时去除NMOS区域的中间阻挡层，而保留位于PMOS区域的P型功函数层和中间阻挡层，之后形成NMOS区域和PMOS区域的N型功函数层及金属栅，如此PMOS的中间阻挡层可在顶部阻挡层的基础上进一步阻挡金属栅的金属向P型功函数层中扩散，从而防止P型功函数层的功函数的大小产生偏移，另PMOS的中间阻挡层位于其P型功函数层与N型功函数层之间，N型功函数层的材料通常为TiAl，因此本发明更可通过中间阻挡层阻挡PMOS的的N型功函数层的Al成份向P型功函数层中扩散，而进一步防止P型功函数层的功函数的大小产生偏移，可在维持NMOS组件阈值电压的同时，降低PMOS组件的阈值电压，提高器件性能，且无需增加额外光罩，工艺易于实现。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请一实施例的高介电金属栅极MOSFET结构示意图。
图2a至图2d为本发明一实施例的高介电金属栅极MOSFET结构的形成过程示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
应当理解，本申请的权利要求、说明书及附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。本申请的说明书和权利要求书中使用的术语“包括”和“包含”指示所描述特征、整体、步骤、操作、元素和/或组件的存在，但并不排除一个或多个其它特征、整体、步骤、操作、元素、组件和/或其集合的存在或添加。
本申请一实施例提供一种高介电金属栅极MOSFET结构，具体的请参阅图1，图1为本申请一实施例的高介电金属栅极MOSFET结构示意图，如图1所示，高介电金属栅极MOSFET结构，包括：半导体衬底100，半导体衬底100包括NMOS形成区域101和PMOS形成区域102，如图1中AA线区分的区域，在半导体衬底100的NMOS形成区域101的表面形成有NMOS的高介电金属栅极结构210，在半导体衬底100的PMOS形成区域102的表面形成有PMOS的高介电金属栅极结构220，高介电金属栅极结构之间填充有层间介质层230，其中NMOS的高介电金属栅极结构210包括依次叠加的界面层211、高介电常数层212和底部阻挡层213构成的栅介质层，形成于栅介质层之上的N型功函数层216，叠加于N型功函数层216之上的顶部阻挡层217，形成于顶部阻挡层217之上的金属栅219；PMOS的高介电金属栅极结构220包括依次叠加的界面层221、高介电常数层222和底部阻挡层223构成的栅介质层，形成于栅介质层之上、金属栅形成区域的底部和侧面的P型功函数层224,叠加于P型功函数层224之上的中间阻挡层225，叠加于中间阻挡层225之上的N型功函数层226，叠加于N型功函数层226之上的顶部阻挡层227，形成于顶部阻挡层227之上的金属栅229。
如此相对于现有技术，NMOS的高介电金属栅极结构不变，而PMOS的高介电金属栅极结构在P型功函数层之上增加一层中间阻挡层，该中间阻挡层可进一步阻挡PMOS的高介电金属栅极结构中的所述金属栅的金属(如Al)向P型功函数层中扩散，从而防止P型功函数层的功函数的大小产生偏移，另中间阻挡层位于其P型功函数层与N型功函数层之间，N型功函数层的材料通常为TiAl，因此本发明更可通过中间阻挡层阻挡PMOS的高介电金属栅极结构中的N型功函数层的Al成份向P型功函数层中扩散，而进一步防止P型功函数层的功函数的大小产生偏移，可在维持NMOS组件阈值电压的同时，降低PMOS组件的阈值电压，提高器件性能。
通常，在NMOS形成区域101中形成有P阱，NMOS器件形成在半导体衬底的P阱之上；在PMOS形成区域102中形成由N阱，PMOS器件形成在半导体衬底的N阱之上。
如图1所示，浅沟槽隔离结构103形成于半导体衬底100中，并隔离出所述NMOS形成区域101和所述PMOS形成区域102。
如图1所示，NMOS的N型功函数层216包覆金属栅219的底部和侧面，顶部阻挡层217叠加于N型功函数层216之上。
如图1所示，PMOS的P型功函数层224包覆金属栅229的底部和侧面，中间阻挡层225叠加于P型功函数层224之上，N型功函数层226叠加于中间阻挡层225之上，顶部阻挡层227叠加于N型功函数层226之上。
本发明一实施例中，界面层211和221的材料包括氧化硅。用以增加所述高介电常数层212和222与半导体衬底100之间的附着力。
所述高介电常数层212和222的材料包括二氧化硅(SiO2)，氮化硅(Si3N4)，三氧化二铝(Al2O3)，五氧化二钽(Ta2O5)，氧化钇(Y2O3)，硅酸铪氧化合物(HfSiO4)，二氧化铪(HfO2)，氧化镧(La2O3)，二氧化锆(ZrO2)，钛酸锶(SrTiO3)，硅酸锆氧化合物(ZrSiO4)等。
本发明一实施例中，所述底部阻挡层213和223包括金属氮化物如氮化钛层213a和223a和氮化钽层213b和223b。所述底部阻挡层213和223用于避免高介电常数层212和222和后续的功函数层216或224发生反应从而影响到功函数值。
如图1所示，在所述高介电金属栅极结构的两侧还分别形成有侧墙240和250。
本发明一实施例中，P型功函数层224的材料为TiN，所述N型功函数层226和216的材料为TiAl。
本发明一实施例中，所述顶部阻挡层217和227的材料为TiN。本发明一实施例中，所述顶部阻挡层227还包括叠加于TiN之上的Ti层218和228。
本发明一实施例中，所述中间阻挡层225的材料为金属氮化物，如TaN。本发明一实施例中，所述中间阻挡层225厚度为5埃米至40埃米之间，当然上述数值可有一定的偏差。一实施例中，所述偏差为20％；较优的，所述偏差为10％；更优的，所述偏差为5％。
本发明一实施例中，金属栅的材料通常为Al。
本发明一实施例中，还提供一种高介电金属栅极MOSFET结构的形成方法，可参阅图2a至图2d，图2a至图2d为本发明一实施例的高介电金属栅极MOSFET结构的形成过程示意图，并请参阅图1，高介电金属栅极MOSFET结构的形成方法，包括：
S1：请参阅2a，提供半导体衬底100，半导体衬底100包括NMOS形成区域101和PMOS形成区域102，采用伪多晶硅栅的工艺方法在半导体衬底上完成金属栅之前的工艺，而在半导体衬底100的NMOS形成区域101的表面形成NMOS的多晶硅栅极结构，在半导体衬底100的PMOS形成区域102的表面形成PMOS的多晶硅栅极结构，多晶硅栅极结构之间填充有层间介质层230，其中各多晶硅栅极结构包括依次叠加的界面层211或221、高介电常数层212或222和底部阻挡层213或223构成的栅介质层，形成于栅介质层之上多晶硅栅310或320；
在一实施例中，通常，在NMOS形成区域101中形成有P阱，NMOS器件的多晶硅栅极结构形成在半导体衬底的P阱之上；在PMOS形成区域102中形成有N阱，PMOS器件的多晶硅栅极结构形成在半导体衬底的N阱之上。
如图2a所示，在步骤S1中还在半导体衬底100中形成浅沟槽隔离结构103，浅沟槽隔离结构103隔离出所述NMOS形成区域101和所述PMOS形成区域102。
本发明一实施例中，界面层211和221的材料包括氧化硅。用以增加所述高介电常数层212和222与半导体衬底100之间的附着力。
所述高介电常数层212和222的材料包括二氧化硅(SiO2)，氮化硅(Si3N4)，三氧化二铝(Al2O3)，五氧化二钽(Ta2O5)，氧化钇(Y2O3)，硅酸铪氧化合物(HfSiO4)，二氧化铪(HfO2)，氧化镧(La2O3)，二氧化锆(ZrO2)，钛酸锶(SrTiO3)，硅酸锆氧化合物(ZrSiO4)等。
本发明一实施例中，所述底部阻挡层213和223包括金属氮化物如氮化钛层213a和223a和氮化钽层213b和223b。所述底部阻挡层213和223用于避免高介电常数层212和222和后续的功函数层发生反应从而影响到功函数值。
如图2a所示，在所述多晶硅栅极结构的两侧还分别形成有侧墙240和250。
S2：如图2b所示，去除多晶硅栅310或320；
S3：如图2b所示，形成第一功函数层11，所述第一功函数11覆盖在各所述多晶硅栅310和320去除区域的侧面和底部表面并延伸到所述多晶硅栅310或320去除区域之外，在第一功函数层11之上叠加形成第一阻挡层12；
在一实施例中，所述第一功函数层11为P型功函数层，材料为TiN。
在一实施例中，所述第一阻挡层12的材料为金属氮化物，如TaN。所述第一阻挡层12的形成工艺不受限定，可选任何可形成第一阻挡层12的工艺，如ALD。
S4：如图2c所示，去除部分的所述第一功函数层11和所述第一阻挡层12，保留位于PMOS的多晶硅栅320去除区域的第一功函数层11和第一阻挡层12，而由第一功函数层11形成PMOS的P型功函数层224，由第一阻挡层12形成PMOS的中间阻挡层225，其中PMOS的中间阻挡层225可阻挡金属通过中间阻挡层225向PMOS的P型功函数层224中扩散；
本发明一实施例中，所述中间阻挡层225厚度为5埃米至40埃米之间，当然上述数值可有一定的偏差。一实施例中，所述偏差为20％；较优的，所述偏差为10％；更优的，所述偏差为5％。
S5：如图2d所示，形成第二功函数层，并刻蚀保留位于NMOS的多晶硅栅310去除区域的底部和侧面的第二功函数层及叠加于中间阻挡层225之上的第二功函数层，而形成NMOS的N型功函数层216和PMOS的N型功函数层226；
在一实施例中，所述第二功函数层为N型功函数层，材料为TiAl。
S6：如图2d所示，在NMOS的N型功函数层216上叠加形成顶部阻挡层217，并同时在PMOS的N型功函数层226上叠加形成顶部阻挡层227；
本发明一实施例中，所述顶部阻挡层217和227的材料为TiN。本发明一实施例中，所述顶部阻挡层227还包括叠加于TiN之上的Ti层218和228。
S7：如图1所示，形成金属层，金属层将多晶硅栅310和320去除区域完全填充，并进行平坦化，形成NMOS的金属栅219和PMOS的金属栅229。
本发明一实施例中，金属栅的材料通常为Al。
如此，在形成P型功函数层之后增加一层中间阻挡层，之后在去除NMOS区域的P型功函数层的同时去除NMOS区域的中间阻挡层，而保留位于PMOS区域的P型功函数层和中间阻挡层，之后形成NMOS区域和PMOS区域的N型功函数层及金属栅，如此PMOS的中间阻挡层可在顶部阻挡层的基础上进一步阻挡金属栅的金属向P型功函数层中扩散，从而防止P型功函数层的功函数的大小产生偏移，另PMOS的中间阻挡层位于其P型功函数层与N型功函数层之间，N型功函数层的材料通常为TiAl，因此本发明更可通过中间阻挡层阻挡PMOS的的N型功函数层的Al成份向P型功函数层中扩散，而进一步防止P型功函数层的功函数的大小产生偏移，可在维持NMOS组件阈值电压的同时，降低PMOS组件的阈值电压，提高器件性能，且无需增加额外光罩，工艺易于实现。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明仅用于帮助理解本申请的方法及其核心思想。同时，本领域技术人员依据本申请的思想，基于本申请的具体实施方式及应用范围上做出的改变或变形之处，都属于本申请保护的范围。综上所述，本说明书内容不应理解为对本申请的限制。

Claims (10)

1.一种高介电金属栅极MOSFET结构，其特征在于，包括：
半导体衬底，半导体衬底包括NMOS形成区域和PMOS形成区域，在半导体衬底的NMOS形成区域的表面形成有NMOS的高介电金属栅极结构，在半导体衬底的PMOS形成区域的表面形成有PMOS的高介电金属栅极结构，高介电金属栅极结构之间填充有层间介质层，其中NMOS的高介电金属栅极结构包括依次叠加的界面层、高介电常数层和底部阻挡层构成的栅介质层，形成于栅介质层之上的N型功函数层，叠加于N型功函数层之上的顶部阻挡层，形成于顶部阻挡层之上的金属栅；PMOS的高介电金属栅极结构包括依次叠加的界面层、高介电常数层和底部阻挡层构成的栅介质层，形成于栅介质层之上的P型功函数层,叠加于P型功函数层之上的中间阻挡层，叠加于中间阻挡层之上的N型功函数层，叠加于N型功函数层之上的顶部阻挡层，形成于顶部阻挡层之上的金属栅。
2.如权利要求1所述的高介电金属栅极MOSFET结构，其中：
所述P型功函数层的材料为TiN，所述N型功函数层的材料为TiAl。
3.如权利要求1所述的高介电金属栅极MOSFET结构，其中：
所述中间阻挡层的材料为金属氮化物。
4.如权利要求1或3任一项所述的高介电金属栅极MOSFET结构，其中：
所述中间阻挡层厚度为5埃米至40埃米之间。
5.如权利要求1所述的高介电金属栅极MOSFET结构，其中：
NMOS的N型功函数层包覆金属栅的底部和侧面，顶部阻挡层叠加于N型功函数层之上。
6.如权利要求1所述的高介电金属栅极MOSFET结构，其中：
PMOS的P型功函数层包覆金属栅的底部和侧面，中间阻挡层叠加于P型功函数层之上，N型功函数层叠加于中间阻挡层之上，顶部阻挡层叠加于N型功函数层之上。
7.一种高介电金属栅极MOSFET结构的形成方法，其特征在于，包括：
S1：提供半导体衬底，半导体衬底包括NMOS形成区域和PMOS形成区域，采用伪多晶硅栅的工艺方法在半导体衬底上完成金属栅之前的工艺，而在半导体衬底的NMOS形成区域的表面形成NMOS的多晶硅栅极结构，在半导体衬底的PMOS形成区域的表面形成PMOS的多晶硅栅极结构，多晶硅栅极结构之间填充有层间介质层，其中各多晶硅栅极结构包括依次叠加的界面层、高介电常数层和底部阻挡层构成的栅介质层，形成于栅介质层之上多晶硅栅；
S2：去除多晶硅栅；
S3：形成第一功函数层，所述第一功函数覆盖在各所述多晶硅栅去除区域的侧面和底部表面并延伸到所述多晶硅栅去除区域之外，在第一功函数层之上叠加形成第一阻挡层；
S4：去除部分的所述第一功函数层和所述第一阻挡层，保留位于PMOS的多晶硅栅去除区域的第一功函数层和第一阻挡层，而由第一功函数层形成PMOS的P型功函数层，由第一阻挡层形成PMOS的中间阻挡层，其中PMOS的中间阻挡层可阻挡金属通过中间阻挡层向PMOS的P型功函数层中扩散；
S5：形成第二功函数层，并刻蚀保留位于NMOS的多晶硅栅去除区域的底部和侧面的第二功函数层及叠加于中间阻挡层之上的第二功函数层，而形成NMOS的N型功函数层和PMOS的N型功函数层；
S6：在NMOS的N型功函数层上叠加形成顶部阻挡层，并同时在PMOS的N型功函数层上叠加形成顶部阻挡层；以及
S7：形成金属层，金属层将多晶硅栅去除区域完全填充，并进行平坦化，形成NMOS的金属栅和PMOS的金属栅。
8.如权利要求7所述的高介电金属栅极MOSFET结构的形成方法，其中：
所述第一功函数层为P型功函数层。
9.如权利要求7所述的高介电金属栅极MOSFET结构的形成方法，其中：
所述第一阻挡层的材料为金属氮化物。
10.如权利要求1所述的高介电金属栅极MOSFET结构的形成方法，其中：
所述中间阻挡层厚度为5埃米至40埃米之间。
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