CN111989861A - 高频功率放大器 - Google Patents
高频功率放大器 Download PDFInfo
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Abstract
本发明涉及在相同金属板上,主要将放大用GaN类芯片与形成有其预匹配电路的GaAs类芯片通过导线而连接的高频功率放大器。本发明涉及的高频功率放大器通过将呈现减极性互感的耦合器设置于GaAs类芯片,从而能够抵消相邻的导线间的互感,能够抑制从GaN类芯片的栅极端子观察信号源时的二次谐波阻抗的相对于频率的扩展,能够将所期望的基波频带处的功率放大器的效率保持得高。
Description
技术领域
本发明涉及在同一金属板上,主要将使用了GaN类HEMT的放大用晶体管与形成有其预匹配电路的GaAs类半导体通过导线而连接的高频功率放大器。
背景技术
近年来,发挥宽带隙的优点,使用了与以往的GaAs类晶体管、Si类LDMOS晶体管相比能够在更高的电源电压下进行动作的GaN类HEMT(高电子迁移率晶体管)的高频功率放大器在民用领域也逐渐普及。其主要领域之一是移动电话基站所使用的高频功率放大器。动作频率1~5GHz左右为主流,通常能够在28~50V的高电源电压下进行动作,因此与以往的GaAs类、Si类晶体管相比能够使用小栅极宽度的晶体管而实现相同输出功率。栅极宽度小会带来向标准阻抗即50Ω的阻抗匹配时的损耗降低或功率分配合成损耗的降低。因此,使用了GaN类HEMT的高频功率放大器与使用了GaAs类、Si类晶体管的放大器相比,具有能够实现高增益并且能够高效率地动作这样的优点(例如参照非专利文献1)
专利文献1:日本特开2007-60616号
专利文献2:日本特表2004-523172号
非专利文献1:2016Proceedings of the 46th European MicrowaveConference,pp.572-575,“A 83-W,51%GaN HEMT Doherty Power Amplifier for 3.5-GHz-Band LTE Base Stations”
发明内容
在专利文献1、2以及非专利文献1中,示出了移动电话基站用功率放大器所使用的GaN类HEMT的封装制品的典型例。在图9中示出使用了非专利文献1所记载的GaN类HEMT的1级放大器的封装件内的安装例的仰视图,在图10中示出从侧方观察该安装的图。图11示出包含GaN芯片(T1)以及GaAs芯片(P1)的布局的详细安装图,图12示出图11的一部分的路径的等效电路图。这里,GaN芯片T1由多个GaN类HEMT(High Electron Mobility Transistor)单元构成,GaAs芯片P1担负将GaN类HEMT的低输入阻抗转换为稍高阻抗的预匹配的作用和保证功率放大器整体的稳定性的作用。
在图9中,T1是GaN类HEMT芯片,P1是预匹配用GaAs芯片,10是输入用引线,也兼用作栅极偏置端子。14是输出用引线,也兼用作漏极偏置端子。12是陶瓷封装件的侧壁和散热用金属板。W11~W15是将输入用引线10与GaAs芯片P1连接的导线,W21~W30是将GaAs芯片P1与GaN芯片T1的栅极电极焊盘连接的导线,W31~W35是将GaN芯片T1的漏极电极焊盘与输出用引线14连接的导线。
在图10中,12a是将GaN芯片T1处的发热排至封装件下部,同时还担负接地的作用的金属板,12b是用于将引线10、14与金属板12a电绝缘的绝缘体,12c是封装件的侧壁和上表面的罩体。
在图11中,就将GaAs芯片P1与GaN芯片T1连接的导线、W21A、W21B~W25A、W25B而言,在图8中为了简化,而由W21~W25这5根导线示出,但在实际的布局中,大多如图9所示,各自由A和B这2根导线构成。这是由于,为了使功率放大器高效率地进行动作,在从由F1~F5示出的GaN类HEMT单元的栅极电极焊盘P31~P35观察输入用引线10方向时的阻抗中,不仅优化基波阻抗,还优化二次谐波阻抗是有效的。
就该优化而言,将基波的路径(例如W21A的路径)与二次谐波的路径(例如W21B的路径)分开这一做法在设计上对于优化是有利的,因而在图11中,GaAs芯片P1上的焊盘也与W21A、W21B~W25A、W25B对应地,与焊盘P21A、P21B~P25A、P25B分开。VH11和VH21分别是在GaAs芯片P1上、GaN芯片T1上形成的通路孔,用于将芯片背面的接地电极和芯片表面的接地金属连接。为了避免附图的复杂化,对于所有部位的通路孔都不标记标号,但相同形状的圆点表示通路孔。
此外,PP是GaAs芯片P1的输入焊盘,TT是GaN芯片T1的漏极电极焊盘。另外,IN1~IN5示出各导线W11~W15的与输入用焊盘10之间的连接点,OUT1~OUT5示出各导线W31~W35的与输出用焊盘14之间的连接点。
图12的等效电路示出从图11的连接点IN1至OUT1为止的路径的等效电路。在图12中,Lw11、Lw21A、Lw21B、Lw31分别示出图11的导线W11、W21A、W21B、W31所呈现的电感。电阻R11和电容器C11形成稳定化电路,电感Lw21A和电容器C21形成针对基波的预匹配电路,电感Lw21B和电容器C31形成二次谐波短路电路。与没有二次谐波短路电路的情况相比,通过该二次谐波短路电路,能够提高GaN类HEMT单元F1的功率放大动作时的效率。此外,图12所示的电阻R11、电容器C11~C31对应于图11的芯片布局上示出的标号。
图13示出在将从GaN类HEMT(F1)的栅极电极焊盘P31观察连接点IN1方向时的二次谐波阻抗的反射系数的大小设为大致1(全反射)的状态下,使反射相位发生了变化时,对路径IN1~OUT1的功率放大器的漏极效率进行模拟的例子。在模拟中,使该反射系数的大小和相位在栅极电极焊盘P31处理想地发生变化,因而不包含图12的电感Lw21B和电容器C3。如图13所示,放大器的漏极效率根据前述二次谐波反射相位而变化,通常,在180°附近示出最大值。
图14示出在图12的等效电路中,从栅极电极焊盘P31观察连接点IN1的方向时的阻抗的轨迹的例子。可知基波频带fl~fh(fc是中心频率)的阻抗集中于大致一点,与此相对,二次谐波频带(2fl~2fh,2fc是中心)的阻抗的轨迹显著地扩展。该扩展存在以下课题,即,脱离图13所示的170°~190°这一可以得到最大效率的范围,无法在整个被设为目标的频带内实现高效率动作。
本发明涉及的高频功率放大器具有:场效应晶体管(F1),其具有栅极端子(P31)、源极端子和漏极端子(TT),该场效应晶体管(F1)用于对高频基波信号进行放大;第1半导体芯片(T1),其形成有场效应晶体管(F1);预匹配电路,其具有场效应晶体管(F1)的输入侧基波匹配用的第1输入端子(PP)和第1输出端子(N11);二次谐波短路电容器(C31),其具有场效应晶体管的输入侧二次谐波短路用端子(N12);第1耦合器(CPL1),其具有第2输入端子(与N11相同部位)、第3输入端子(与N12相同部位)、第2输出端子(P21A)以及第3输出端子(P21B),该第2输入端子与第1输出端子(N11)连接,该第3输入端子与输入侧二次谐波短路用端子(N12)连接,该第2输出端子(P21A)输出来自第2输入端子的信号,该第3输出端子(P21B)输出来自第3输入端子的信号,在从第2输入端子和第3输入端子同时输入了信号的情况下,该第1耦合器(CPL1)呈现减极性互感;第2半导体芯片(P1),其形成有预匹配电路、二次谐波短路电容器和耦合器;第1导线(W21A),其将第2输出端子与栅极端子连接;以及第2导线(W21B),其将第3输出端子与栅极端子连接,该第2导线与第1导线之间呈现加极性互感。
发明的效果
本发明涉及的高频功率放大器具有如下效果,即,在相同金属板上,主要将使用了GaN类HEMT的放大用晶体管与形成有其预匹配电路的GaAs类半导体通过导线而连接时,能够抑制从GaN类HEMT的栅极电极焊盘观察输入用引线方向时的二次谐波阻抗的相对于基波频带的扩展,因而能够在基波频带内高效率地动作。
附图说明
图1是实施方式1涉及的高频功率放大器的预匹配部的电路结构。
图2是实施方式1涉及的高频功率放大器的预匹配部和GaN类HEMT部的包含布局和导线的安装图。
图3是实施方式1涉及的高频功率放大器的在预匹配部设置的耦合器部的放大布局图。
图4是实施方式1涉及的流过电感Lw21A的基波和二次谐波的电流成分的模拟结果。
图5是用于与实施方式1进行比较的流过图10的电感Lw21A的基波和二次谐波的电流成分的模拟结果。
图6是实施方式1涉及的高频功率放大器的从GaN类HEMT的栅极电极焊盘观察信号源侧时的阻抗的轨迹。
图7是实施方式2涉及的高频功率放大器的预匹配部的电路结构。
图8是实施方式2涉及的高频功率放大器的预匹配部的放大布局图。
图9是使用了以往的GaN类HEMT而成的1级放大器的封装件内的安装例的仰视图。
图10是从侧方对图9的安装进行观察的图。
图11是以往的高频功率放大器的预匹配部和GaN类HEMT部的包含布局和导线的安装图。
图12是以往的高频功率放大器的预匹配部的电路结构。
图13示出在将图12的从GaN类HEMT(F1)的栅极电极焊盘P31观察连接点IN1方向时的二次谐波阻抗的反射系数的大小设为大致1(全反射)的状态下,使反射相位发生了变化时,对路径IN1~OUT1的功率放大器的漏极效率进行模拟的例子。
图14是图12的高频功率放大器的从GaN类HEMT的栅极电极焊盘观察信号源侧时的阻抗的轨迹。
具体实施方式
参照附图,对本发明的实施方式涉及的高频功率放大器进行说明。连同已经叙述过的附图在内,对相同或者相应的结构要素标注相同的标号,有时省略重复说明。下面,以将使用了GaN类HEMT的放大用晶体管与形成有其预匹配电路的GaAs类半导体通过导线而连接的高频功率放大器为例进行说明。
[实施方式1]
(结构的说明)
图1示出本发明的实施方式1涉及的高频功率放大器的预匹配部的电路结构。与上面所说明的图11之间的较大不同在于,在GaAs芯片P1上,将由彼此呈现减极性互感的电感Lc1A和Lc1B构成的耦合器CPL1设置于电感Lw21A和Lw21B的近端,即,导线W21A和W21B的焊盘P21A和P21B的紧邻左侧。
图2是实施方式1涉及的高频功率放大器的预匹配部和GaN类HEMT部的包含布局和导线的安装图。作为本发明的特征的耦合器CPL1~CPL5分别设置于IN1~OUT1、IN2~OUT2、IN3~OUT3、IN4~OUT4、IN5~OUT5各路径。就耦合器CPL1~CPL5的位置而言,为了将GaAs芯片P1的尺寸增大设为最小限,以与GaAs芯片P1上的焊盘P21A和P21B、P22A和P22B、P23A和P23B、P24A和P24B、P25A和P25B相邻的方式配置。
图3是前述耦合器部CPL1的布局的放大图。耦合器CPL1由平行地配置的传输线路(这里是微带线路)TRL21A和TRL21B构成,为了使得电磁耦合呈现减极性,与焊盘P21A连接的传输线路TRL21B连接至电容器C3,与焊盘P21B连接的传输线路TRL21A连接至电容器C1、C2。
(动作的说明)
首先,对前述的二次谐波频带的阻抗的轨迹扩展这一课题的要因进行说明。如图11的布局图以及图12的等效电路所示,将GaAs芯片P1与GaN芯片T1之间连接的导线(W21A~W25B)是多根相邻并且平行的。由于该相邻并且平行而在相邻导线之间产生电磁耦合。通过标注于图12的电感Lw21A和Lw21B处的点可知,该耦合呈现加极性互感。但是,电感Lw21A与基波的预匹配连接,Lw21B与二次谐波短路连接。因此,乍一看,由于流过的电流的频率不同,因而看上去没有直接影响。这里,所谓短路,理想的是0Ω,但要说明的是,即使是基波的阻抗的1/5以下的二次谐波阻抗,在实际使用上也没有问题。
图4是流过图12的电路的电感Lw21A的基波电流成分和二次谐波电流成分的模拟结果。例如,在将基波中心频率设为2.6GHz的图12的电路中,流过电感Lw21A的基波电流成分为0.7、二次谐波电流成分为0.12,占基波电流成分约17%的较大的二次谐波电流成分流过电感Lw21A。其结果,判断出流过电感Lw21A和Lw21B的二次谐波电流成分彼此以加极性相加,二次谐波阻抗的变化加大。
这样,鉴于二次谐波电流成分也流过基波预匹配路径这一点,在图1中具有减极性的耦合器CPL1与呈现加极性的电感Lw21A和Lw21B连接。通过适当地设定耦合器CPL1的减极性互感,从而能够通过具有减极性互感的耦合器CPL1而有效地抵消由于电感Lw21A和Lw21B的加极性而实效地增大的二次谐波电流的电感,能够抑制流过Lw21A以及Lw21B的二次谐波电流的电感的增加。
图6示出从图1的栅极电极焊盘P31观察连接点IN1的方向时的阻抗的轨迹的例子。可知不仅是基波频带fl~fh(fc是中心频率)的阻抗集中于大致一点,而且二次谐波频带(2fl~2fh,2fc是中心)的阻抗的轨迹的扩展与图14相比也大幅度地得到抑制。
在专利文献2中记载有下述例子,即,为了基波匹配而将导线的电感的增加通过折返的导线而抵消的例子。另一方面,在本发明中,为了抵消针对二次谐波的加极性互感,而将呈现减极性互感的耦合器形成于芯片上,在这一点上不同。具有如下效果,即,通过在芯片上形成耦合器,从而使针对二次谐波的减极性互感的大小不受导线长度这样的制约,能够通过布局适当地进行设定。
(实施方式1的效果)
如上所述,通过将实施方式1涉及的呈现减极性互感的耦合器CPL1设置于GaAs芯片P1上,从而能够抑制二次谐波阻抗的扩展,能够将所期望的基波频带处的功率放大器的效率保持得高。
此外,在图1以及图2所示的例子中,将呈现减极性互感的耦合器形成于GaAs芯片P1上,但只要能够抵消电感Lw21A和Lw21B的加极性的影响即可,因而即使在GaN芯片T1上,即,在Lw21A和Lw21B的右端与栅极电极焊盘P31之间设置耦合器CPL1,也会得到抑制二次谐波阻抗的扩展的效果。并且,也可以将耦合器CPL1分割而设置于GaAs芯片P1上和GaN芯片T1上这两者。
另外,在图2以及图3中,举出并说明了利用微带线路间的边缘耦合的耦合器CPL1的例子,但在能够利用多层配线的情况下,利用上下地配置了线路的宽边耦合、或利用使用了螺旋电感来取代单纯的微带线路的耦合,也会得到与前述相同的效果。
[实施方式2]
图7示出本发明的实施方式2涉及的高频功率放大器的预匹配部的电路结构,是与图2的IN2~OUT2、IN3~OUT3、IN4~OUT4的路径相当的部分的等效电路。图8是实施方式2涉及的预匹配部的放大布局图。在图7、图8中,R12~R14是电阻,C12~C14、C22~C24、C32~C34是电容器,Lw22A、Lw22B、Lw23A、Lw23B、Lw24A、Lw24B是分别与图2或者图8所示的导线W22A、W22B、W23A、W24A、W24B对应的电感。
另外,由电感Lc2A和Lc2B构成的耦合器CPL2,由电感Lc3A和Lc3B构成的耦合器CPL3,由电感Lc4A和Lc4B构成的耦合器CPL4是在实施方式1中说明的呈现减极性互感的耦合器。
在实施方式1中,示出了通过耦合器CPLx对由INx~OUTx(x=1~5)中的1个路径内的基波预匹配用导线W2xA和二次谐波短路用导线W2xB之间的电磁耦合引起的电感的增加进行抑制的例子。
在实施方式2中,是不仅考虑1个路径,而且还考虑与相邻的相邻路径之间的电磁耦合,而抵消电感的增加的例子。图8是其具体的布局例。
在图8中,耦合器CPL3A和CPL3B是由图7的CPL3示出的与实施方式1相同的具有减极性的耦合器。在图8中,除此以外,还具有耦合器CPL32和CPL34。耦合器CPL32是用于抵消图7的电感Lw23A与相邻的路径的电感Lw22B之间的电磁耦合的耦合器。另外,耦合器CPL34是用于抵消图7的电感Lw23B与相邻的路径的电感Lw24A之间的电磁耦合的耦合器。关于如上所述的来自相邻的路径的电磁耦合的存在,能够理解为是因为如图2、图8所示的那样同相的信号经过相邻的导线。
另外,如图8所示的耦合器CPL32、CPL34那样,也能够抵消来自相邻路径的导线的电磁耦合的影响,能够通过芯片上的耦合器的布局设计而适当地设定抵消互感的量,上述两点与专利文献2不同。
(实施方式2的效果)
如上所述,通过将实施方式2涉及的以抵消来自相邻的其它路径的电磁耦合的方式配置的耦合器设置于GaAs芯片P1上,从而与实施方式1相比能够更有效地抑制二次谐波阻抗的扩展,能够将所期望的基波频带处的功率放大器的效率保持得高。
此外,如在实施方式1的说明中也叙述过的那样,将呈现减极性互感的耦合器分割,设置于GaN芯片T1上,或者设置于GaAs芯片P1上和GaN芯片T1上这两者,也会得到相同的效果。
另外,在图8中,举出并说明了利用微带线路间的边缘耦合的例子,但在能够利用多层配线的情况下,利用上下地配置了线路的宽边耦合、或利用使用了螺旋电感来取代单纯的微带线路的耦合,也会得到与前述相同的效果。
此外,如上所述的实施方式使用将GaN类HEMT与形成有其预匹配电路的GaAs芯片之间通过导线而连接的情况下的例子进行了说明,但GaN类HEMT也可以是GaAs类HEMT、GaAs类FET。另外,就预匹配电路的形成而言,只要是能够形成电容器、电阻、耦合线路的半导体工艺,则都能够应用,特别地,如果考虑到高频下的低基板损耗特性,则不仅是能够利用高电阻基板的GaN芯片、GaAs芯片,当然,还能够用于SOI(Silicon-on-Insulator)芯片、SOS(Silicon-on-Sapphire)芯片、在玻璃基板上应用半导体工艺的IPD(Integrated PassiveDevice)芯片。
此外,如果对形成预匹配电路的基板使用SOI,则基板电阻率为大致1kΩcm~10kΩcm的范围,因此,如果与SiC基板上的GaN类HEMT工艺、GaAs基板的电阻率1Mcm相比,则在稍高频带下电路损耗增加,但能够将成本抑制得低。使用玻璃基板的IPD的成本与SOI相同,电阻率也高达1Mcm。但是,导热率低,因此,在预匹配电路的发热高的情况下,与SiC基板、GaAs基板相比,预匹配电路的电路损耗稍微增加。
标号的说明
T1:GaN芯片
P1:GaAs芯片
F1~F5:GaN类HEMT
10:输入用引线
14:输出用引线
12:陶瓷封装件的侧壁和散热用金属板
12a:金属板
12b:用于将引线10、14与金属板12a电绝缘的绝缘体
12c:封装件的侧壁和上表面的罩体
W11~W15:将输入用引线10与GaAs芯片P1连接的导线
W21~W30:将GaAs芯片P1与GaN芯片T1的栅极电极焊盘连接的导线
W31~W35:将GaN芯片T1的漏极电极焊盘与输出用引线14连接的导线
W21A、W21B~W25A、W25B:将GaAs芯片P1与GaN芯片T1连接的导线
P31~P35:栅极电极焊盘
P21A、P21B、P22A、P22B、P23A、P23B、P24A、P24B、P25A、P25B:与GaN芯片连接的导线的GaAs芯片上的焊盘
VH11、VH21:通路孔
PP:GaAs芯片P1的输入焊盘
TT:GaN芯片T1的漏极电极焊盘
IN1~IN5:导线W11~W15的与输入用焊盘10之间的连接点
OUT1~OUT5:导线W31~W35的与输出用焊盘14之间的连接点
R11~R13:电阻
C11~C31、C21~C34、C31~C34、C41~C44:电容器
Lw21A、Lw21B、Lw22A、Lw22B、Lw23A、Lw23B、Lw24A、Lw24B、Lw25A、Lw25A:导线的电感
Lc1A、Lc1B、Lc2A、Lc2B、Lc3A、Lc3B、Lc4A、Lc4B:耦合器的电感
CPL1~CPL5、CPL3A、CPL3B、CPL32、CPL34:呈现减极性互感的在芯片上形成的耦合器
N11:基波预匹配部与耦合器的连接点
N12:二次谐波短路用电容器C31与耦合器的连接点
Claims (10)
1.一种高频功率放大器,其具有:
场效应晶体管,其具有栅极端子、源极端子和漏极端子,该场效应晶体管用于对高频基波信号进行放大;
第1半导体芯片,其形成有所述场效应晶体管;
预匹配电路,其具有所述场效应晶体管的输入侧基波匹配用的第1输入端子和第1输出端子;
二次谐波短路用电容器,其具有所述场效应晶体管的输入侧二次谐波短路用端子;
耦合器,其具有第2输入端子、第3输入端子、第2输出端子、以及第3输出端子,该第2输入端子与所述第1输出端子连接,该第3输入端子与所述输入侧二次谐波短路用端子连接,该第2输出端子输出来自所述第2输入端子的信号,该第3输出端子输出来自所述第3输入端子的信号,在从所述第2输入端子和所述第3输入端子同时输入了信号的情况下,该耦合器呈现减极性互感;
第2半导体芯片,其形成有所述预匹配电路、所述二次谐波短路用电容器和所述耦合器;
第1导线,其将所述第2输出端子与所述栅极端子连接;以及
第2导线,其将所述第3输出端子与所述栅极端子连接,该第2导线与第1导线之间呈现加极性互感。
2.根据权利要求1所述的高频功率放大器,其特征在于,
所述第1半导体芯片是GaN类HEMT芯片,所述第2半导体芯片是GaAs类芯片。
3.根据权利要求1所述的高频功率放大器,其特征在于,
所述第1半导体芯片是GaN类HEMT芯片,所述第2半导体芯片是SOI芯片。
4.根据权利要求1所述的高频功率放大器,其特征在于,
所述第1半导体芯片和所述第2半导体芯片都是GaAs类芯片。
5.根据权利要求1所述的高频功率放大器,其特征在于,
所述第2半导体芯片是IPD芯片。
6.一种高频功率放大器,其具有:
场效应晶体管,其具有栅极端子、源极端子和漏极端子,该场效应晶体管用于对高频基波信号进行放大;
预匹配电路,其具有所述场效应晶体管的输入侧基波匹配用的第1输入端子和第1输出端子;
二次谐波短路电容器,其具有所述场效应晶体管的输入侧二次谐波短路用端子;
耦合器,其具有第2输入端子、第3输入端子、第2输出端子以及第3输出端子,该第2输入端子与所述第1输出端子连接,该第3输入端子与所述输入侧二次谐波短路用端子连接,该第2输出端子输出来自所述第2输入端子的信号,该第3输出端子输出来自所述第3输入端子的信号,在从所述第2输入端子和所述第3输入端子同时输入了信号的情况下,该耦合器呈现减极性互感;
第1半导体芯片,其形成有所述场效应晶体管和所述耦合器;
第2半导体芯片,其形成有所述预匹配电路和所述二次谐波短路电容器;
第1导线,其将所述第2输出端子与所述栅极端子连接;以及
第2导线,其将所述第3输出端子与所述栅极端子连接,该第2导线与第1导线之间呈现加极性互感。
7.根据权利要求6所述的高频功率放大器,其特征在于,
所述第1半导体芯片是GaN类HEMT芯片,所述第2半导体芯片是GaAs类芯片。
8.根据权利要求6所述的高频功率放大器,其特征在于,
所述第1半导体芯片是GaN类HEMT芯片,所述第2半导体芯片是SOI芯片。
9.根据权利要求6所述的高频功率放大器,其特征在于,
所述第1半导体芯片和所述第2半导体芯片都是GaAs类芯片。
10.根据权利要求6所述的高频功率放大器,其特征在于,
所述第2半导体芯片是IPD芯片。
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