CN111725296A - 半导体装置 - Google Patents

半导体装置 Download PDF

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CN111725296A
CN111725296A CN202010186755.0A CN202010186755A CN111725296A CN 111725296 A CN111725296 A CN 111725296A CN 202010186755 A CN202010186755 A CN 202010186755A CN 111725296 A CN111725296 A CN 111725296A
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gate
semiconductor device
source electrode
gate pad
substrate
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CN111725296B (zh
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松野吉德
谷冈寿一
折附泰典
滨野健一
花野尚慎
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Mitsubishi Electric Corp
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Abstract

目的是提供能够增大有效面积相对于芯片面积的比例，并且抑制层间绝缘膜的劣化的半导体装置。具有：层间绝缘膜，其设置于衬底之上；栅极焊盘，其设置于该层间绝缘膜之上；源极电极，其在俯视观察时与栅极焊盘的一部分相对；线状的源极配线，其在俯视观察时与该栅极焊盘的一部分相对而不与该源极电极相对，源极配线与该源极电极连接；以及栅极配线，其设置于该层间绝缘膜之上，与该栅极焊盘电连接，该衬底具有：第1导电型的漂移层；以及高杂质浓度区域，其设置于该栅极配线和该栅极焊盘的正下方，该高杂质浓度区域的第1导电型杂质的浓度比该漂移层的第1导电型杂质的浓度大，在俯视观察时，该源极配线和该栅极配线提供将该源极电极包围的1个框。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
例如，对于SiC-MOSFET(Metal Oxide Semiconductor Field EffectTransistor)，要求低损耗且高速通断。高速通断意味着dV/dt高。通过高速通断而在栅极配线或栅极焊盘正下方产生高电位，层间绝缘膜的劣化风险升高。例如，有时通过与源极成为相同电位的源极配线将栅极配线或栅极焊盘正下方包围而作为该劣化风险的对策。
由于SiC与Si相比绝缘击穿电场高10倍，因此在采用了SiC的情况下，在高dV/dt时，在栅极配线或栅极焊盘正下方与Si相比产生高电位的风险更高。另一方面，就在栅极配线的周围设置源极配线的构造而言，有效面积相对于芯片面积的比例变小。有效面积是指电流通电面积。由于SiC与Si相比材料成本高，因此需要对构造及布局进行最佳设计。越是小芯片，设计对成本的影响就越显著。
在专利文献1的第0042段中记载了“在使碳化硅MOSFET 100以从接通状态向断开状态进行切换的方式而变化的情况下，在外周阱区域9产生的位移电流如在图3中由箭头VC所示的那样，也流入源极配线13的下方的外周接触区域8，由此位移电流的路径变短，能够减小由于在通断时所产生的位移电流而在栅极焊盘之下产生的电位差(抑制电位梯度)。由此，能够抑制栅极焊盘之下的绝缘膜的绝缘击穿”。
专利文献1：国际公开第2018/055719号
就上述的在栅极配线的周围设置源极配线的构造而言，有效面积相对于芯片面积的比例变小。期望一种半导体装置，其能够使有效面积相对于芯片面积的比例变大，并且抑制层间绝缘膜的劣化。
发明内容
本发明就是为了解决上述这样的课题而提出的，其目的在于提供能够增大有效面积相对于芯片面积的比例，并且抑制层间绝缘膜的劣化的半导体装置。
本发明涉及的半导体装置的特征在于，具有：衬底；层间绝缘膜，其设置于该衬底之上；栅极焊盘，其设置于该层间绝缘膜之上；源极电极，其设置于该层间绝缘膜之上，在俯视观察时与栅极焊盘的一部分相对；线状的源极配线，其设置于该层间绝缘膜之上，在俯视观察时与该栅极焊盘的一部分相对而不与该源极电极相对，该源极配线与该源极电极连接；以及栅极配线，其设置于该层间绝缘膜之上，与该栅极焊盘电连接，该衬底具有：第1导电型的漂移层；第2导电型的阱层，其设置于该漂移层之上；以及高杂质浓度区域，其在该阱层之上，设置于该栅极配线和该栅极焊盘的正下方，该高杂质浓度区域的第1导电型杂质的浓度比该漂移层的第1导电型杂质的浓度大，在俯视观察时，该源极配线和该栅极配线提供将该源极电极包围的1个框。
本发明的其它特征在以下得以明确。
发明的效果
根据本发明，无需增大源极配线，通过在栅极焊盘等的正下方的衬底表面形成与漂移层相比杂质浓度高的高杂质浓度区域，从而能够增大有效面积相对于芯片面积的比例，并且抑制栅极焊盘等的正下方的层间绝缘膜的劣化。
附图说明
图1是实施方式1涉及的半导体装置的俯视图。
图2是图1的I-II线处的剖面图。
图3是图1的III-IV线处的剖面图。
图4是实施方式2涉及的半导体装置的俯视图。
图5是实施方式3涉及的半导体装置的俯视图。
图6是图5的V-VI线处的剖面图。
图7是对实施方式1、3的半导体装置的通断损耗进行比较的表。
图8是对实施方式1、3的半导体装置的通断损耗进行比较的表。
图9是实施方式4涉及的半导体装置的俯视图。
图10是实施方式5涉及的半导体装置的俯视图。
图11是变形例涉及的半导体装置的俯视图。
图12是实施方式6涉及的半导体装置的俯视图。
图13是变形例涉及的半导体装置的俯视图。
图14是实施方式7涉及的半导体装置的俯视图。
标号的说明
12源极电极，14源极配线，16栅极焊盘，18栅极配线，19衬底，28高杂质浓度区域。
具体实施方式
参照附图，对本发明的实施方式涉及的半导体装置进行说明。对相同或相应的结构要素标注相同的标号，有时省略重复说明。
实施方式1.
图1是实施方式1涉及的半导体装置的俯视图。该半导体装置例如是形成了MOSFET(Metal Oxide Semiconductor Field Effect Transistor)或IGBT(Insulated GateBipolar Transistor)的矩形芯片。最外侧的四边形表示芯片的外缘。该半导体装置具有源极电极12和与源极电极12连接的源极配线14。源极配线14细长地形成为线状。在俯视观察时，源极配线14的两端与源极电极12相接。
在被源极电极12和源极配线14包围的位置设置有栅极焊盘16。在栅极焊盘16电连接有栅极配线18。栅极配线18例如是Al。栅极焊盘16与栅极配线18不直接连接，这一情况在图1中表现出来。在栅极焊盘16连接有导线或引线，从该导线或引线接收栅极电压。施加于栅极焊盘16的栅极电压经由栅极配线18而向位于源极电极12之下的多个栅极电极施加。
在俯视观察时，源极配线14和栅极配线18提供将源极电极12包围的1个框。换言之，在栅极焊盘16与芯片外缘之间存在源极配线14，在源极电极12与芯片外缘之间存在栅极配线18。源极电极12和源极配线14包围栅极焊盘16，不包围栅极配线18。源极电极12在俯视观察时与栅极焊盘16的一部分相对，源极配线14在俯视观察时与栅极焊盘16的一部分相对而不与源极电极12相对。
图2是图1的I-II线处的剖面图。衬底19例如是硅或宽带隙半导体。宽带隙半导体是碳化硅、氮化镓类材料或金刚石。衬底19具有n型衬底20。在n型衬底20之下设置有n+型的漏极层50，在n型衬底20之上设置有n-型的漂移层22。在漂移层22之上设置有p型的阱层24和终端构造26。终端构造26是保护环或场限制板等电场缓和构造。
在阱层24之上，在栅极配线18的正下方设置有n++型的高杂质浓度区域28。高杂质浓度区域28的n型杂质的浓度比漂移层22的n型杂质的浓度大。根据一个例子，可在栅极配线18的整个正下方形成高杂质浓度区域28。例如，在使衬底19为碳化硅的情况下，可提供包含氮、磷或它们两者作为n型杂质的高杂质浓度区域28。高杂质浓度区域28的杂质浓度例如为1×1018cm-3～1×1021cm-3。根据一个例子，能够使高杂质浓度区域28的n型杂质浓度比阱层24的p型杂质浓度高。在阱层24中形成有n+型的源极30。与前述的高杂质浓度区域28和源极30相接地在衬底19的上表面侧形成有p型的接触部32。
在衬底19的上表面设置有层间绝缘膜40。层间绝缘膜40例如是氧化膜或氮化膜。根据另一个例子，能够使层间绝缘膜40为SiON或Al2O3。源极电极12设置于层间绝缘膜40之上。源极电极12穿过层间绝缘膜40的贯穿孔而与接触部32相接。栅极配线18也设置于层间绝缘膜40之上。栅极配线18与在层间绝缘膜40中设置的多晶硅42相接。
图3是图1的III-IV线处的剖面图。栅极焊盘16设置于层间绝缘膜40之上。栅极焊盘16与在层间绝缘膜40中设置的多晶硅42相接。因此，栅极焊盘16与栅极配线18通过多晶硅42电连接。
源极配线14设置于层间绝缘膜40之上。源极配线14穿过层间绝缘膜40的贯穿孔而与接触部32相接。在阱层24之上，在栅极焊盘16的正下方设置有高杂质浓度区域28。根据一个例子，可以在栅极焊盘16的整个正下方形成高杂质浓度区域28。
就实施方式1涉及的半导体装置而言，在栅极配线18和栅极焊盘16的正下方设置了薄层电阻值低的高杂质浓度区域28，因而能够抑制这些区域的所产生的电压。因此，即使是产生高dV/dt的高速通断，也能够减少装置的损伤。另外，源极配线14仅设置于与栅极焊盘16相对的部分，因而与将源极配线设置于栅极配线的周围的情况相比，能够增大相对于芯片面积的有效面积，实现低接通电阻化。
实施方式1的半导体装置在不丧失其特征的范围能够进行各种变形。在将n型设为第1导电型，将p型设为第2导电型时，也可以使第1导电型和第2导电型反转。在通过这样的导电型的反转而将高杂质浓度区域28设为p型的区域时，可以提供包含铝、硼或它们两者作为p型杂质的高杂质浓度区域28。以下的实施方式涉及的半导体装置与实施方式1之间的共通点多，因而以与实施方式1之间的不同点为中心进行说明。
实施方式2.
图4是实施方式2涉及的半导体装置的俯视图。栅极焊盘16设置于源极电极12的角部。如果将栅极焊盘16设置于源极电极12的角部，则与不这样设置的情况相比，能够增大相对于芯片面积的有效面积。
实施方式3.
图5是实施方式3涉及的半导体装置的俯视图。栅极配线18a的一端与栅极焊盘16相接。栅极配线18a的另一端部不与栅极焊盘16相接。形成为线状的源极配线14a的一端与源极电极12相接，另一端部不与源极电极12相接。在源极配线14a的另一端部与源极电极12之间的间隙，栅极焊盘16与栅极配线18a连接。根据一个例子，栅极配线18a与栅极焊盘16的端部相接。由此，能够增大源极配线14a与栅极焊盘16的相对部分。
通过源极配线14a和源极电极12而包围栅极焊盘16的大部分，但由于存在前述的源极配线14a与源极电极12的间隙，因此源极配线14a和源极电极12未将栅极焊盘16的一部分包围。图5中的I-II线处的剖面图与图2相同，图5中的III-IV线处的剖面图与图3相同。
图6是图5的V-VI线处的剖面图。在栅极配线18a和栅极焊盘16的正下方的衬底存在高杂质浓度区域28。由此，能够抑制栅极配线18a和栅极焊盘16的正下方的所产生的电压，并且降低栅极电阻。即，能够以低通断损耗而高速通断。
图7、8是将实施方式1、3的半导体装置的通断损耗进行比较的表。形态A示出由实施方式1的半导体装置得到的结果，形态B示出由实施方式3的半导体装置得到的结果。接通时的VGS是18V，断开时的VGS是0V。结温Tj是150℃。漏极源极电流Ids是30A。从图7、8可知，在将栅极配线18a与栅极焊盘16直接相连的形态B中，能够降低通断损耗。
实施方式4.
图9是实施方式4涉及的半导体装置的俯视图。该半导体装置与实施方式3的结构类似，但在栅极焊盘16设置于源极电极12的角部这一点上与实施方式3不同。将栅极焊盘16设置于源极电极12的角部这一做法与不这样设置的情况相比，能够增大相对于芯片面积的有效面积。
实施方式5.
图10是实施方式5涉及的半导体装置的俯视图。该半导体装置具有电流感测焊盘60。电流感测焊盘60是隔着层间绝缘膜而设置在衬底19之上，供衬底19的主电流的一部分流过的焊盘。在源极电极12连接有线状的源极延长部14b。源极延长部14b与源极电极12同样地设置于衬底之上。能够在源极延长部14b的正下方设置前述的高杂质浓度区域。源极延长部14b在俯视观察时与电流感测焊盘60的一部分相对而不与源极电极12相对。由此，电流感测焊盘60被源极电极12和源极延长部14b包围。
根据上述结构，在产生高dV/dt的高速通断时，能够减少电流感测焊盘60的正下方的层间绝缘膜40劣化的风险。此外，栅极配线18b是为了向与其接近的栅极电极施加电压而设置的。
图11是变形例涉及的半导体装置的俯视图。在该例中，栅极焊盘16设置于源极电极12的非角部，电流感测焊盘60设置于源极电极12的角部，因此栅极焊盘16与电流感测焊盘60的距离近。因此，如图11所示的这样，使源极配线14a和源极延长部14b连续一体地形成。
也可以在半导体装置设置温度感测焊盘而代替电流感测焊盘60。温度感测焊盘隔着层间绝缘膜而设置在衬底之上。在该情况下，在衬底形成温度感测二极管，将温度感测焊盘与该温度感测二极管连接。具有上述这样的温度感测焊盘的结构的俯视图只要将图10、11的电流感测焊盘60替换成温度感测焊盘即可得到。在该情况下，源极延长部14b在俯视观察时与温度感测焊盘的一部分相对而不与源极电极12相对，能够减少层间绝缘膜劣化的风险。
实施方式6.
图12是实施方式6涉及的半导体装置的俯视图。在栅极焊盘16连接有栅极衬里(liner)70。栅极衬里70与在衬底中平行地设置了多个的栅极电极电连接。栅极衬里70的材料例如是Al。在栅极衬里70的正下方隔着层间绝缘膜而设置有前述的高杂质浓度区域。因此，在栅极焊盘16、栅极配线18a以及栅极衬里70的正下方提供有高杂质浓度区域。由此，能够抑制栅极焊盘16、栅极配线18a以及栅极衬里70的正下方的所产生的电压，并且降低栅极电阻。
图13是变形例涉及的半导体装置的俯视图。图13的半导体装置具有在实施方式5中所说明的电流感测焊盘60和源极延长部14b。在该情况下，除了上述的电压抑制效果以外，还能够减少电流感测焊盘60正下方的层间绝缘膜劣化的风险。
实施方式7.
图14是实施方式7涉及的半导体装置的俯视图。栅极焊盘16为一边小于或等于400μm的四边形。源极电极12在俯视观察时与栅极焊盘的一部分相对。栅极配线18c在俯视观察时将源极电极12的整体包围，与栅极焊盘16相接。具体地说，栅极配线18c的一端与栅极焊盘16的右上部分相接，栅极配线18c的另一端部与栅极焊盘16的左下部分相接。在阱层之上，在栅极焊盘16的正下方设置有高杂质浓度区域。
在实施方式7涉及的半导体装置没有源极配线。在一边小于或等于400μm的小的栅极焊盘16的情况下，即使不使源极配线与栅极焊盘相对，也能够抑制栅极焊盘正下方处的层间绝缘膜的劣化。具体地说，在dV/dt≤150kV/μs程度的高速通断条件下，不需要使源极配线与栅极焊盘相对。因此，在实施方式7中，能够通过将栅极配线18c与栅极焊盘16直接连接，从而减小栅极电阻，通过废除源极配线，从而增大相对于芯片面积的有效面积。此外，也可以组合使用在到此为止的实施方式中所说明的半导体装置的特征。

Claims (14)

1.一种半导体装置，其特征在于，具有：
衬底；
层间绝缘膜，其设置于所述衬底之上；
栅极焊盘，其设置于所述层间绝缘膜之上；
源极电极，其设置于所述层间绝缘膜之上，在俯视观察时与栅极焊盘的一部分相对；
线状的源极配线，其设置于所述层间绝缘膜之上，在俯视观察时与所述栅极焊盘的一部分相对而不与所述源极电极相对，该源极配线与所述源极电极连接；以及
栅极配线，其设置于所述层间绝缘膜之上，与所述栅极焊盘电连接，
所述衬底具有：第1导电型的漂移层；第2导电型的阱层，其设置于所述漂移层之上；以及高杂质浓度区域，其在所述阱层之上，设置于所述栅极配线和所述栅极焊盘的正下方，
所述高杂质浓度区域的第1导电型杂质的浓度比所述漂移层的第1导电型杂质的浓度大，
在俯视观察时，所述源极配线和所述栅极配线提供将所述源极电极包围的1个框。
2.根据权利要求1所述的半导体装置，其特征在于，具有：
多晶硅，其设置于所述层间绝缘膜中，将所述栅极配线与所述栅极焊盘连接，
在俯视观察时，所述源极配线的两端与所述源极电极相接。
3.根据权利要求1或2所述的半导体装置，其特征在于，
所述栅极焊盘设置于所述源极电极的角部。
4.根据权利要求1所述的半导体装置，其特征在于，
所述栅极配线的一端与所述栅极焊盘相接。
5.根据权利要求4所述的半导体装置，其特征在于，
所述栅极配线与所述栅极焊盘的端部相接。
6.根据权利要求4或5所述的半导体装置，其特征在于，
所述栅极焊盘设置于所述源极电极的角部。
7.根据权利要求1至6中任一项所述的半导体装置，其特征在于，具有：
电流感测焊盘，其设置于所述衬底之上，供所述衬底的主电流的一部分流过；以及
线状的源极延长部，其设置于所述衬底之上，在俯视观察时与所述电流感测焊盘的一部分相对而不与所述源极电极相对，该源极延长部与所述源极电极连接。
8.根据权利要求1至6中任一项所述的半导体装置，其特征在于，具有：
温度感测二极管，其形成于所述衬底；
温度感测焊盘，其设置于所述衬底之上，与所述温度感测二极管相接；以及
线状的源极延长部，其设置于所述衬底之上，在俯视观察时与所述温度感测焊盘的一部分相对而不与所述源极电极相对，该源极延长部与所述源极电极连接。
9.根据权利要求1至8中任一项所述的半导体装置，其特征在于，
具有与所述栅极焊盘连接的栅极衬里，所述高杂质浓度区域设置于所述栅极衬里的正下方。
10.根据权利要求1至9中任一项所述的半导体装置，其特征在于，
所述衬底由宽带隙半导体形成。
11.根据权利要求10所述的半导体装置，其特征在于，
所述宽带隙半导体是碳化硅、氮化镓类材料或金刚石。
12.一种半导体装置，其特征在于，具有：
衬底；
层间绝缘膜，其设置于所述衬底之上；
四边形的栅极焊盘，其设置于所述层间绝缘膜之上，一边小于或等于400μm；
源极电极，其设置于所述层间绝缘膜之上，在俯视观察时与栅极焊盘的一部分相对；以及
栅极配线，其设置于所述层间绝缘膜之上，在俯视观察时将所述源极电极的整体包围，该栅极配线与所述栅极焊盘相接，
所述衬底具有：第1导电型的漂移层；第2导电型的阱层，其设置于所述漂移层之上；以及高杂质浓度区域，其在所述阱层之上，设置于所述栅极焊盘的正下方，
所述高杂质浓度区域的第1导电型杂质的浓度比所述漂移层的第1导电型杂质的浓度大。
13.根据权利要求12所述的半导体装置，其特征在于，
所述衬底由宽带隙半导体形成。
14.根据权利要求13所述的半导体装置，其特征在于，
所述宽带隙半导体是碳化硅、氮化镓类材料或金刚石。
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