CN111725239B - 显示面板驱动电路、阵列基板及其制造方法 - Google Patents

显示面板驱动电路、阵列基板及其制造方法 Download PDF

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CN111725239B
CN111725239B CN202010518517.5A CN202010518517A CN111725239B CN 111725239 B CN111725239 B CN 111725239B CN 202010518517 A CN202010518517 A CN 202010518517A CN 111725239 B CN111725239 B CN 111725239B
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CN111725239A (zh
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张乐
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Abstract

本申请提供一种显示面板驱动电路、阵列基板及其制造方法。显示面板驱动电路包括多个晶体管，所述多个晶体管中包括低漏电流薄膜晶体管，所述低漏电流薄膜晶体管包括半导体层，所述半导体层包括第一半导体层和设置于所述第一半导体层上的第二半导体层，所述第一半导体层与所述第二半导体中的一个的材料为低温多晶硅，另一个的材料的载流子迁移率小于所述低温多晶硅的载流子迁移率。

Description

显示面板驱动电路、阵列基板及其制造方法
技术领域
本申请涉及显示领域，尤其涉及一种显示面板驱动电路、阵列基板及其制造方法。
背景技术
主动矩阵有机发光二极管(Active-matrix organic light-emitting diode,AMOLED)显示器因其独特的优势，得到快速发展。AMOLED所搭配的阵列基板，主流为低温多晶硅(Low Temperature Poly-silicon，LTPS)p沟道金属氧化物半导体场效应(positivechannel MeTLl Oxide Semiconductor，PMOS)阵列基板。LTPS PMOS阵列基板在制作过程中，难以确保所形成的大面积的多晶硅半导体的均一性，而导致阈值电压漂移。
为解决AMOLED LTPS多晶硅均一性差的问题，AMOLED LTPS阵列基板亚像素驱动电路需采用像素补偿电路，以此抵消阈值电压漂移带来的影响。现主流像素补偿电路为7T1C设计，7T1C电路分为3个工作阶段：1)初始还原阶段；2)电路补偿阶段；3)像素发光阶段。由于像素发光阶段时间很长，补偿电路内电容电位会由于长时间漏电作用逐渐失真，造成像素发光异常。LTPS PMOS TFT(Thin Film Transistor，薄膜晶体管)在截止区的翘尾效应加剧了TFT的漏电流，为降低漏电流，现行方案为对TFT栅极和源极加载大偏压，即薄膜晶体管老化(TFT-Aging)。TFT-Aging对主动矩阵(Active-matrix，AA)区以外的如阵列基板行驱动(Gate Driver on Array，GOA)区域TFT无法Aging。
发明内容
有鉴于此，本申请目的在于提供一种能够防止由于薄膜晶体管漏电导致的像素发光异常且无需进行老化的显示面板驱动电路、阵列基板以及制造方法。
本申请提供一种显示面板驱动电路，其包括多个晶体管，所述多个晶体管中包括低漏电流薄膜晶体管，所述低漏电流薄膜晶体管包括半导体层，所述半导体层包括第一半导体层和设置于所述第一半导体层上的第二半导体层，所述第一半导体层与所述第二半导体中的一个的材料为低温多晶硅，另一个的材料的载流子迁移率小于所述低温多晶硅的载流子迁移率。
在一种实施方式中，所述低漏电流薄膜晶体管设置在所述像素补偿电路中的第一位置处，以降低所述第一位置处的漏电流对所述像素补偿电路的影响。
在一种实施方式中，所述载流子迁移率小于低温多晶硅的载流子迁移率的材料包括金属氧化物半导体、金属氮化物半导体、金属氮氧化物半导体和非晶硅中的至少一种。
在一种实施方式中，所述第一半导体层的材料为低温多晶硅，所述第二半导体层的材料的载流子迁移率小于所述低温多晶硅的载流子迁移率；其中，所述第一半导体层包括沟道区及分别位于所述沟道区两侧的掺杂区；所述第二半导体层在所述沟道区上的正投影位于所述沟道区内。
在一种实施方式中，所述第一掺杂区和所述第二掺杂区为P型掺杂区。
在一种实施方式中，所述多个晶体管中还包括低温多晶硅薄膜晶体管，所述低温多晶硅薄膜晶体管与所述低漏电流薄膜晶体管同时形成在基板上。
在一种实施方式中，所述低漏电流薄膜晶体管和所述低温多晶硅薄膜晶体管均为N型晶体管或P型晶体管。
在一种实施方式中，所述低温多晶硅薄膜晶体管设置在所述像素驱动电路中的第二位置处，所述第二位置为在所述像素补偿电路中除所述第一位置以外的位置。
本申请提供一种阵列基板，其特征在于，所述阵列基板包括如上任一项所述的显示面板驱动电路。
本申请提供一种阵列基板的制造方法，其特征在于，包括以下步骤：
提供一衬底，在所述衬底上依次层叠形成第一半导体材料层、第二半导体材料层以及光刻胶层，其中所述第一半导体材料层和所述第二半导体材料层中的一个的材料为低温多晶硅，另一个的材料的载流子迁移率小于所述低温多晶硅的载流子迁移率；
利用半色调掩模对所述光刻胶层进行曝光，显影，形成第一保护层，第二保护层和第三保护层；所述第二保护层连接于所述第一保护层两侧，所述第一保护层的厚度大于所述第二保护层，所述第三保护层与所述第一保护层和所述第二保护层间隔设置，
进行第一次刻蚀，除去未被所述第一保护层、所述第二保护层和所述第三保护层覆盖的所述第一半导体材料层和所述第二半导体材料层，得到第一半导体层；
灰化并除去所述第二保护层和所述第三保护层，减薄所述第一保护层；
进行第二次刻蚀，除去未被所述第一保护层的所述第二半导体材料层，除去所述第一保护层，得到第二半导体层和第三半导体层。
本申请通过使用低漏电流薄膜晶体管代替现有技术中的低温多晶硅薄膜晶体管，能够降低显示面板驱动电路中的TFT漏电流。从而，防止由于TFT漏电导致的像素发光异常。且在制备过程中，省略老化的步骤。
附图说明
为了更清楚地说明本申请中的技术方案，下面将对实施方式描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施方式，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请第一实施方式的阵列基板平面示意图。
图2是图1的阵列基板沿A-A线的剖面示意图。
图3是图1的阵列基板上的像素补偿电路的等价电路图。
图4(a)～图4(h)是本申请第二实施方式的阵列基板的制造方法的流程图。
具体实施方式
下面将结合本申请实施方式中的附图，对本申请中的技术方案进行清楚、完整地描述。显然，所描述的实施方式仅仅是本申请一部分实施方式，而不是全部的实施方式。基于本申请中的实施方式，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施方式，都属于本申请保护的范围。
本申请所有实施例中采用的晶体管可以为薄膜晶体管或场效应管或其他特性相同的器件，由于这里采用的晶体管的源极、漏极是对称的，所以其源极、漏极是可以互换的。在本申请实施例中，为区分晶体管除栅极之外的两极，将其中一极称为源极，另一极称为漏极。按附图中的形态规定开关晶体管的中间端为栅极、信号输入端为源极、输出端为漏极。此外本申请实施例所采用的晶体管可以包括P型晶体管和/或N型晶体管两种，其中，P型晶体管在栅极为低电平时导通，在栅极为高电平时截止，N型晶体管为在栅极为高电平时导通，在栅极为低电平时截止。
请参考图1和图2，本申请提供一种阵列基板1000。该阵列基板1000可以用于OLED，例如AMOLED。阵列基板1000包括基板10和设置于基板10上的显示驱动电路100。显示驱动电路100包括多个晶体管。多个晶体管中包括低漏电流薄膜晶体管TP。低漏电流薄膜晶体管TL设置在显示驱动电路100中的第一位置P1处，以降低所述第一位置P1处的漏电流对显示驱动电路100的影响。多个晶体管中还可以包括低温多晶硅薄膜晶体管TP。低温多晶硅薄膜晶体管TP设置在显示驱动电路100中的第二位置P2处。第二位置P2为在显示驱动电路100中除所述第一位置P1以外的位置。低漏电流薄膜晶体管TL和低温多晶硅薄膜晶体管TP均为N型晶体管或P型晶体管。且，低漏电流薄膜晶体管TL和低温多晶硅薄膜晶体管TP同时形成在基板上。
低漏电流薄膜晶体管TL包括半导体层20、设置于半导体层20上的栅极绝缘层30、设置于栅极绝缘层30上的第一栅极41、设置于第一栅极41上的层间绝缘层和设置于层间绝缘层上的源极和漏极。
半导体层20包括第一半导体层21和设置于第一半导体层21上的第二半导体层22。第一半导体层21和第二半导体层22中的一个的材料为低温多晶硅，另一个的材料的载流子迁移率小于低温多晶硅的载流子迁移率。载流子迁移率小于低温多晶硅的载流子迁移率的材料包括金属氧化物半导体、金属氮化物半导体、金属氮氧化物半导体和非晶硅中的至少一种。具体地，包括铟镓锌氧化物、铟锡锌氧化物、铟锌氧化物、铟锡氧化物、氧化锌、氧化锡、镓锌氧化物、锌的氮氧化物、锡的氮氧化物等中的至少一种。
在本实施方式中，第一半导体层21的材料为低温多晶硅。
现有技术中的低温多晶硅薄膜晶体管的半导体层仅由低温多晶硅形成，这就造成无论薄膜晶体管处于开态还是关态，电子均会从低温多晶硅中通过，由低温多晶硅的载流子迁移率较高，因此导致在关态时电流的载流子迁移率高、浓度高，即漏电流较大。而本实施例所提供的薄膜晶体管的处于开态时，由于第一半导体层21的载流子迁移率高于第二半导体层22，第一半导体层21会对电子产生吸引作用，因此电子从第一半导体层21中通过，第一半导体层21的载流子迁移率较高，从而能够获得载流子迁移率高、浓度高的开态电流；当薄膜晶体管处于关态时，由于此时第一半导体层21内几乎没有电子，成为耗尽层，会对电子产生排斥作用，因此电子会从第二半导体层22中通过，第二半导体层22的载流子迁移率较低，从而获得载流子迁移率低、浓度低的漏电流，即减小了漏电流。
在本实施方式中，第二半导体层22位于第一半导体层的上方21。即先形成第一半导体层21，再形成第二半导体层22，使得低温多晶硅材料能够形成在一个平坦的表面，不会产生段差，保证了第一半导体层21具有良好的电性能。当然，第二半导体层22也可设置于第一半导体层21的下方，本实施例对此并不限定。
在本实施方式中，第一半导体层21包括：沟道区21a及分别位于沟道区21a两侧的掺杂区21b。掺杂区21b为P型掺杂区。第二半导体层22在沟道区21a上的正投影位于沟道区21a内。第一栅极41与沟道区21a对应设置。源极和漏极与掺杂21a区电接触。
低温多晶硅薄膜晶体管TP包括第三半导体层23和设置于第三半导体层23上的栅极绝缘层30、设置于栅极绝缘层30上并且与第三半导体层23对应设置的第二栅极42以及与第三半导体层23电接触的源极和漏极。第三半导体层23上也形成有掺杂区。
显示驱动电路100可以包括像素补偿电路100a和阵列基板行驱动电路100b。
该像素补偿电路100a可以为4T1C、5T1C、7T1C等现有技术中的像素补偿电路。
以下，举例说明像素补偿电路100a为7T1C补偿电路时的情况。
请参考图3，像素补偿电路100a包括第一晶体管T1、第二晶体管T22、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第一电容C1以及发光器件D。
第一晶体管T1的栅极电性连接于第一节点a1，第一晶体管T1的源极电性连接于第二节点a2，第一晶体管T1的漏极电性连接于第三节点a3。
第二晶体管T22的栅极电性连接于第一扫描信号，第二晶体管T22的源极电性连接于第一节点a1，第二晶体管T22的漏极电性连接于第三节点a3。
第三晶体管T3的栅极电性连接于第一扫描信号，第三晶体管T3的源极电性连接于数据信号DATL，第三晶体管T3的漏极电性连接于第二节点a2。第一扫描信号由本级栅极线Gn提供。数据信号由数据线提供。
第四晶体管T4的栅极电性连接于第二扫描信号，第四晶体管T4的源极电性连接于低电平，第四晶体管T4的漏极电性连接于第一节点a1。第二扫描信号由上一级栅极线Gn-1提供。
第五晶体管T5的栅极电性连接于发光信号EM，第五晶体管T5的源极电性连接于第三节点a3，第五晶体管T5的漏极电性连接于第四节点a4。
第六晶体管T6的栅极电性连接于发光信号EM，第六晶体管T6的源极电性连接于第一电源信号VDD，第六晶体管T6的漏极电性连接于第二节点a2。第一电源信号VDD由电源电压提供。
第七晶体管T7的栅极电性连接于第二扫描信号，第七晶体管T7的源极电性连接于低电平Vi，第七晶体管T7的漏极电性连接于第四节点a4。第二扫描信号由上一级栅极线Gn-1提供。
第一电容C1的第一端电性连接于第一节点a1，第一电容的第二端电性连接于第一电源信号。
发光器件D的阳极端电性连接于第四节点a4，发光器件D的阴极端电性连接于第二电源信号。第二电源信号为接地信号。
第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7中可以包括低漏电流薄膜晶体管TL和低温多晶硅薄膜晶体管TP。在一种实施方式中，由于7T1C结构中，第二薄膜晶体管T2与第四薄膜晶体管T4对漏电流高度敏感，可以将第二薄膜晶体管T2与第四薄膜晶体管T4设为低漏电流薄膜晶体管TL。第一晶体管T1、第三晶体管T3、第五晶体管T5、第六晶体管T6和第七晶体管T7设为低温多晶硅薄膜晶体管TP。使用低漏电流薄膜晶体管TL代替现有技术中的低温多晶硅薄膜晶体管TP能够大大降低LTPS基板TFT漏电流，防止像素发光异常。且在制备过程中，省略老化的步骤。
相似地，阵列基板行驱动电路100b也可以包括低漏电流薄膜晶体管TL。例如，阵列基板行驱动电路100b全部采用低漏电流薄膜晶体管TL，或者一部分采用低漏电流薄膜晶体管TL，一部分采用普通薄膜晶体管，例如低温多晶硅薄膜晶体管TP。
请参考图4(a)至图4(h)，本申请第二实施方式还提供一种阵列基板的制造方法，用于制造本申请第一实施方式的阵列基板。其包括以下步骤：
S1:提供一衬底10，在衬底10上依次层叠形成第一半导体材料层2、第二半导体材料层3以及光刻胶层200。
衬底10上可以形成有遮光层、缓冲层等膜层。
其中，第一半导体材料层2和第二半导体材料层3中的一个的材料为低温多晶硅，另一个的材料的载流子迁移率小于低温多晶硅的载流子迁移率。载流子迁移率小于低温多晶硅的载流子迁移率的材料包括金属氧化物沟道、金属氮化物沟道、金属氮氧化物沟道和非晶硅中的至少一种。具体地，包括铟镓锌氧化物、铟锡锌氧化物、铟锌氧化物、铟锡氧化物、氧化锌、氧化锡、镓锌氧化物、锌的氮氧化物、锡的氮氧化物等中的至少一种。
在本实施方式中，第一半导体材料层2为低温多晶硅。
S2:利用半色调掩模300对光刻胶层200进行曝光，显影，形成第一保护层201，第二保护层202和第三保护层203。第二保护层202连接于第一保护层201两侧，第一保护层201的厚度大于第二保护层202，第三保护层203与第一保护层201和第二保护层202间隔设置。
半色调掩模300具有不透光区301、半透光区302和透光区303。在使用正型光阻的情况下，不透光区301用于形成第一区域201，半透光区302用于形成第二区域202和第三区域203。透光区303对应于光刻胶层200的其他部分。
S3:进行第一次刻蚀，除去未被第一保护层201，第二保护层202和第三保护层203覆盖的第一半导体材料层2和第二半导体材料层3，得到第一半导体层21。
S4:灰化(ash)并除去(strip)第二保护层202和第三保护层203，减薄第一保护层201。
S5:进行第二次刻蚀，除去未被第一保护层201的第二半导体材料层3，除去第一保护层201，得到第二半导体层22和第三半导体层23。
S6:在第二半导体层22和第三半导体层23上层叠形成栅极绝缘层30和第一栅极41以及第二栅极42。以第一栅极41为遮蔽层对第一半导体层21进行掺杂，形成沟道区21a和位于沟道区21a两侧的掺杂区21b。在此步骤中，第一半导体层21中的低温多晶硅被注入三价元素，形成导电率较好的P型掺杂半导体。同时，第一栅极41两端区域PN结形成，形成TFT。掺杂后的第一半导体层21与第二半导体层22共同形成低漏电流薄膜晶体管TL的半导体层。
同时，以第二栅极42为遮蔽层对第三半导体层23进行掺杂。掺杂后的第三半导体层23作为低温多晶硅薄膜晶体管TP的半导体层。
在本实施方式中，举例示出像素补偿电路100a中的薄膜晶体管为顶栅型薄膜晶体管的情况。在底栅型薄膜晶体管中，也可以对第一半导体层21和第三半导体层23进行掺杂。掺杂的方法可以利用现有技术中的方法，在此不再赘述。
本实施方式的像素补偿电路的制造方法还包括在第一栅极41和第二栅极42上形成层间绝缘层和源漏极从而得到低漏电流薄膜晶体管TL和低温多晶硅薄膜晶体管TP的步骤。
通过上述制造方法可以制造本申请第一实施方式中的阵列基板1000的像素补偿电路100a和阵列基板行驱动电路100b造。
本申请的阵列基板的制造方法通过使用低漏电流薄膜晶体管代替现有技术中的低温多晶硅薄膜晶体管，能够降低像素补偿电路中的TFT漏电流。从而，防止由于TFT漏电导致的像素发光异常。在制备过程中，阵列基板上的像素补偿电路和阵列基板行驱动电路均能够省略老化的步骤。
以上对本申请实施方式提供了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施方式的说明只是用于帮助理解本申请。同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上，本说明书内容不应理解为对本申请的限制。

Claims (1)

1.一种阵列基板的制造方法，其特征在于，包括以下步骤：
提供一衬底，在所述衬底上依次层叠形成第一半导体材料层、第二半导体材料层以及光刻胶层，其中所述第一半导体材料层和所述第二半导体材料层中的一个的材料为低温多晶硅，另一个的材料的载流子迁移率小于所述低温多晶硅的载流子迁移率；
利用半色调掩模对所述光刻胶层进行曝光，显影，形成第一保护层，第二保护层和第三保护层；所述第二保护层连接于所述第一保护层两侧，所述第一保护层的厚度大于所述第二保护层，所述第三保护层与所述第一保护层和所述第二保护层间隔设置，
进行第一次刻蚀，除去未被所述第一保护层、所述第二保护层和所述第三保护层覆盖的所述第一半导体材料层和所述第二半导体材料层，得到第一半导体层；
灰化并除去所述第二保护层和所述第三保护层，减薄所述第一保护层；
进行第二次刻蚀，除去未被所述第一保护层的所述第二半导体材料层，除去所述第一保护层，得到第二半导体层和第三半导体层。
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