CN111566610A - 命令选择策略 - Google Patents

命令选择策略 Download PDF

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CN111566610A
CN111566610A CN201880067106.XA CN201880067106A CN111566610A CN 111566610 A CN111566610 A CN 111566610A CN 201880067106 A CN201880067106 A CN 201880067106A CN 111566610 A CN111566610 A CN 111566610A
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P·A·拉弗拉塔
R·M·沃克
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Micron Technology Inc
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    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659Command handling arrangements, e.g. command buffers, queues, command scheduling
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/06Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0638Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1673Details of memory controller using buffers
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668Details of memory controller
    • G06F13/1689Synchronisation and timing concerns
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/16Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18Handling requests for interconnection or transfer for access to memory bus based on priority control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604Improving or facilitating administration, e.g. storage management
    • G06F3/0607Improving or facilitating administration, e.g. storage management by facilitating the process of upgrading existing storage systems, e.g. for improving compatibility between host and storage device
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0602Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061Improving I/O performance
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0628Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658Controller construction arrangements
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
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    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0673Single storage device
    • G06F3/0679Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601Interfaces specially adapted for storage systems
    • G06F3/0668Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671In-line storage system
    • G06F3/0683Plurality of storage devices
    • G06F3/0685Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/20Employing a main memory using a specific memory technology
    • G06F2212/205Hybrid memory, e.g. using both volatile and non-volatile memory

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Abstract

描述与用于电子存储器或存储装置的命令选择策略有关的设备及方法。可基于命令的类型、相对于另一命令接收一个命令的时序、准备向存储器装置发出一个命令的时序,或此类因素的某一组合来对到存储器控制器的命令进行优先级排序。举例来说,存储器控制器可采用先备先来先服务FRFCFS策略,其中使某些类型的命令(例如,读取命令)优先于其它类型的命令(例如,写入命令)。基于命令当中或之间的相依性或关系,所述策略可采用此FRFCFS策略的例外情况。实例可包含:基于对应于相应命令的类别,将命令插入优先级队列,以及以优先级顺序迭代通过多个优先级队列以选择待发布的命令。

Description

命令选择策略
技术领域
本发明大体上涉及存储器,并且更特定来说,涉及与命令选择策略相关联的设备及方法。
背景技术
存储器装置通常作为计算机或其它电子装置中的内部半导体集成电路提供。存在许多不同类型的存储器,其包含易失性及非易失性存储器。易失性存储器可能需要电力来维持其数据,并且包含随机存取存储器(RAM)、动态随机存取存储器(DRAM)及同步动态随机存取存储器(SDRAM)等。非易失性存储器可通过在不通电时保留存储数据来提供持久数据,并且可包含NAND快闪存储器、NOR快闪存储器、只读存储器(ROM)、电可擦除可编程ROM(EEPROM)、可擦除可编程ROM(EPROM)及电阻可变存储器,例如相变随机存取存储器(PCRAM)、电阻式随机存取存储器(RRAM)及磁阻式随机存取存储器(MRAM)等。
存储器还被用作用于广泛的电子应用的易失性及非易失性数据存储装置。非易失性存储器可用在例如个人计算机、便携式记忆棒、数码相机、蜂窝电话、例如MP3播放器的便携式音乐播放器、电影播放器以及其它电子装置中。可将存储器单元布置成阵列,其中所述阵列用于存储器装置中。
各种计算系统包含耦合到存储器(例如,存储器系统)的处理资源,所述存储器与执行一组指令(例如,程序、应用程序等)相关联地被存取。存储器系统可实施调度策略,其用于确定由存储器系统执行从处理资源接收的命令(例如,读取及写入)的顺序。举例来说,此类调度策略可能会影响计算系统性能,这是由于在计算系统上执行的程序的执行时间受到与对存储器的存取请求相关联的执行时间的影响。
附图说明
图1是根据本发明的数个实施例的呈包含存储系统并且能够实施命令选择策略的计算系统形式的设备的框图。
图2是根据本发明的数个实施例的能够实施命令选择策略的控制器的框图。
图3A及3B说明根据本发明的数个实施例的与实施命令选择策略相关联的流程图。
图4说明根据本发明的数个实施例的与实施命令选择策略相关联的命令的实例。
具体实施方式
本发明包含与命令选择策略有关的设备及方法。实例方法可包含:接收到存储器控制器的多个命令;基于相应命令的类别,将多个命令中的每一命令插入多个优先级队列中的一者中;以及基于队列的优先级及多个命令中的至少一个命令的类别从优先级队列中的一者选择所述至少一个命令以将其发布到存储器控制器。
与先前方法相比,本发明的数个实施例可提供改进的命令选择策略。例如,某些现有命令选择策略包含FCFS(先到先服务)及FRFCFS(先备先到先服务)。FCFS策略可包含基于由存储器控制器接收(例如,解码)接收到所述控制器的命令的顺序来调度所述命令以由存储器装置(例如,例如DRAM装置的主存储器)执行。因此,将首先执行最旧命令。然而,各种存储器系统包含时序约束,其可能会影响是否可发布命令(例如,从存储器控制器发布到存储器装置)。举例来说,与存储器阵列相关联的各种支持电路(例如,行解码电路、列解码电路、感测放大器电路、预充电电路、刷新电路等)可包含确定特定命令何时/是否准备由存储器装置执行的时序约束。因此,FCFS策略可增加执行等待时间,这是因为较新命令可准备发布到存储器装置(例如,基于时序约束),但是在执行较旧命令之前,所述命令不能发送到存储器装置。
与FCFS策略相比,FRFCFS策略可减少等待时间。举例来说,在FRFCFS策略中,存储器控制器可迭代通过命令队列并选择其遇到的准备发布的第一个命令。因此,可能会跳过尚未准备就绪的较旧命令,而倾向于准备就绪的较新挂起命令。
作为实例,FRFCFS策略可包含使列命令优先于行命令,使得所述策略包含在命令队列中搜索准备发布的最旧列命令,并且如果未找到可发布列命令,那么选择准备发布的命令以发布到存储器装置。如所属领域的技术人员所了解,存储器及存储阵列可逻辑地或物理地或既逻辑又物理地组织成列及行。因此,如本文所使用,“列”命令是指针对对应于存储器装置的阵列的开放(例如,激活的)行(例如,页面)的地址的命令,并且“行”命令是指针对对应于阵列的封闭(例如,去激活)行的地址的命令。
FCFS策略及FRFCFS策略均不优先化读取命令(例如,优先于写入命令)。由于由处理资源(例如,中央处理单元)执行的各种指令可取决于其它指令的执行,因此优先化读取命令可改进系统性能。举例来说,待由CPU执行的各种指令可取决于发布到存储系统的读取命令。因此,在将对应于读取命令的数据返回到CPU之前,CPU不能执行从属指令。因而,发送到存储系统的读取命令的执行的延迟可导致程序执行的延迟。
本发明的数个实施例可实施命令选择策略,其使读取命令优先于写入命令,这可提供例如减少与对存储器的读取存取请求相关联的等待时间的益处以及其它益处。如本文进一步描述,数个实施例包含实施具有与FRFCFS策略的相似性以及严格读取优先级的命令选择策略。可经由执行存储在机器可读媒体上的指令来实施数个实施例,所述媒体可包含各种非暂时性媒体,其包含(但不限于)易失性及/或非易失性存储器,例如固态存储器、相变存储器、铁电存储器、光学媒体及/或磁性媒体等其它类型的机器可读媒体。
在本发明的以下详细描述中,参考形成本发明的一部分的附图,并且在附图中通过说明的方式展示可如何实践本发明的数个实施例。对这些实施例进行足够详细的描述,以使所属领域的一般技术人员能够实践本发明的实施例,并且应理解,可利用其它实施例,并且在不脱离本发明的范围的情况下可进行工艺改变、电气改变及/或结构改变。如本文所使用,指定符“N”指示如此指定的数个特定特征可包含在本发明的数个实施例中。
如本文所使用,“数个”某物可指代此类事物中的一或多者。举例来说,数个存储器装置可指代存储器装置中的一或多者。“多个”某物意指两个或更多个。另外,本文使用的例如“N”的指示符(尤其是关于图式中的参考数字)指示如此指示的数个特定特征可包含在本发明的数个实施例中。
本文中的图式遵循编号惯例,其中第一个或前几个数字对应于图式图号,并且其余数字标识图式中的元件或组件。可通过使用类似数字来标识不同图式之间的类似元件或组件。将了解,在本文的各种实施例中展示的元件可被添加、交换及/或消除,以便于提供本发明的数个额外实施例。另外,在图式中提供的元件的比例及相对尺度希望说明本发明的各种实施例,并且不以限制性意义使用。
图1是根据本发明的数个实施例的呈包含存储器系统120并且能够实施命令选择策略的计算系统形式的设备的框图。如本文所使用,“设备”可指代(但不限于)各种结构或结构的组合,例如电路或若干电路、裸片或若干裸片、模块或若干模块、装置或若干装置或者系统或若干系统。举例来说,控制器104、主机102、系统120及/或装置110-1到110-N可单独地被称为“设备”。
在此实例中,计算系统包含主机102,其耦合到控制器104(例如,经由接口103),控制器104耦合到存储器系统120(例如,经由接口105)。计算系统可为膝上型计算机、个人计算机、数码相机、数字记录及回放装置、移动电话、PDA、存储卡读取器、接口集线器、传感器、支持物联网(IoT)的装置以及其它系统,并且主机102可包含能够(例如,经由控制器104)存取存储器120的数个处理资源(例如,一或多个处理器)。主机102可负责执行操作系统(OS)及/或可加载到其的各种应用程序(例如,经由控制器104从存储器系统120加载)。
控制器104可从主机102接收存储器事务请求(例如,以读取及写入命令的形式,其分别可被称为加载及存储命令)。控制器104可通过接口103及105在主机102与存储器系统120之间传送命令及/或数据,接口103及105可包括例如采用合适协议的物理接口,例如总线。此协议可为定制的或专用的,或者接口103及105中的一者或两者可采用标准化协议,例如外围组件互连快速(PCIe)、Gen-Z、CCIX或类似者。控制器104可包括以硬件、固件或软件或这三者的任何形式的控制电路。作为实例,控制器104可包括状态机、定序器及/或某种其它类型的控制电路,其可以耦合到印刷电路板的专用集成电路(ASIC)的形式实施。在数个实施例中,控制器104可与主机102位于同一位置(例如,在芯片上系统(SOC)配置中)。并且,控制器104可与存储器系统120位于同一位置。控制器104可为例如控制器(例如结合图2描述的控制器204)并且可经配置以实施根据如下文进一步描述的本发明的数个实施例的命令选择策略。
如图1所展示,存储器系统120包含数个存储器装置110-1、110-2、...、110-N,其可统称为存储器110。存储器110可包括数个物理存储器“芯片”或裸片,其可各自包含数个存储器单元阵列(例如,库)以及与存取阵列相关联的对应支持电路(例如,地址电路、I/O电路、控制电路、读取/写入电路等)(例如,以从阵列读取数据并将数据写入阵列)。作为实例,存储器装置110-1到110-N可包含数个DRAM装置、SRAM装置、PCRAM装置、RRAM装置、FeRAM、相变存储器、3DXpoint及/或快闪存储器装置。在数个实施例中,存储器系统110可充当计算系统的主存储器。
图2是根据本发明的数个实施例的能够实施命令选择策略的控制器204的框图。控制器204可为例如图1所展示的控制器104的控制器的一部分。举例来说,控制器204可表示用于实施特定命令选择策略的控制器104的命令选择子系统。如本文所使用,命令选择策略可被称为命令调度策略,并且可指代选择命令及/或调度(例如,优先化)命令以发布到存储器装置。结合图3中所展示的流程图进一步描述可由控制器204实施的命令选择策略的实例。
控制器204包含命令队列230以存储与从例如主机(例如,102)的装置接收的对存储器系统(例如,120)的传入存取请求相关联的命令232-0、232-1、232-2、...、232-(i-1)(统称为命令232)。控制器204可对传入存取请求进行解码并且根据期望命令选择策略对对应命令232进行分类。作为实例,可基于各种因素对所接收命令232进行分类,所述因素包含(但不限于)命令类型(例如,读取或写入)、命令地址(例如,命令是否以存储器装置的开放或封闭行为目标)及/或命令龄期(例如,自被接收以来的时间)以及包含一个命令与另一个命令之间的关系(例如,写入后读取相依性)的各种其它因素。
如图2中所展示,控制器204可包含用于实施期望命令选择策略的命令选择逻辑240。在此实例中,命令选择逻辑240包含多个优先化队列248-0(Q0)、248-1(Q1)、248-2(Q2)、...、248-(k-1)(Qk-1)(其可统称为优先化队列248)以及用于实施期望命令选择策略的时序参数逻辑242及优先化逻辑244。
时序参数逻辑242可负责跟踪与存取将向其发布命令的存储器装置相关联的各种时序约束。此类时序约束可包含例如各种控制信号(例如,读取/写入启用信号)及/或地址信号(例如,行/列地址信号)以及各种其它信号的时序的约束。举例来说,如果存储器装置是DRAM装置,那么此类时序参数可包含激活命令与列命令之间所需的最少时间(例如tRCD)、列命令之间所需的最少时间(例如tCCD)、预充电命令与激活命令(例如tRP)之间的最少时间以及各种其它时序参数(例如,tRAS、tCAS、tCP、tASR、tASC、tCAH等)。逻辑242可例如用于确定优先化队列248中的命令是否准备发布(例如,是否可在不违反装置时序参数的情况下将命令发送到存储器装置以执行)。如本文所使用,术语“队列”不希望限于特定数据结构实施方案,而是术语队列可指代以各种方式组织的元素的集合,并且其可具有一或多种不同类型的队列及/或列表(例如,列表、链接列表等)等的特性。
优先化逻辑244可负责迭代通过队列230中的命令232,确定针对所接收命令232的指定优先级类别,插入优先级队列248中的选定者的命令232,以及迭代通过多个队列248(以优先级顺序)以选择待发布到存储器装置的特定命令。在图2中,箭头247表示发送到存储器装置的选定命令,并且箭头249表示来自存储器装置的响应(例如,对应于选定命令)。箭头233表示提供到命令选择逻辑240以基于其指定类别及对应优先级层级插入优先级队列248中的一者中的命令232。箭头235表示与例如命令选择逻辑240相关联的控制信号,命令选择逻辑240迭代通过命令232并且一旦将命令232发布到存储器装置就将其从队列230中移除。
在数个实施例中,以优先级顺序对优先化队列248进行索引,使得队列248-0具有最高优先级,且队列248-(k-1)具有最低优先级。具有不同优先级的队列可被称为具有第一优先级、第二优先级、第三优先级及类似者。一个队列的优先级差异是相对于另一队列的。因此,“较高”优先级队列经给定或具有优先于另一队列的优先级。因此,最高优先级队列具有优先化队列248中的最高优先级,且最低优先级队列具有优先化队列248中的最低优先级。
命令232在相应优先级队列248内的优先级顺序可基于命令的龄期,使得相应队列248中最旧的命令具有最高优先级,并且在迭代通过相应队列时将首先被遇到。作为实例,迭代通过至少一些优先级队列248可包含使用FRFCFS策略,其中选择遇到的准备发布的第一命令(例如,基于装置时序参数)来发布。然而,如下文进一步描述,在数个实施例中,迭代通过队列248可包含在某些情况下忽略较低优先级队列,这可防止发布具有低于最高优先级队列(例如,248-0)的优先级的至少一个队列中的可发布命令(例如,响应于确定最高优先级队列不为空)。此外,与其中列命令(例如,列读取命令及列写入命令两者)都优先于行命令(例如,行读取命令及行写入命令两者)的FRFCFS策略不同,本发明的数个实施例实施经修改FRFCFS选择策略,其中读取命令(例如,列读取命令及行读取命令两者)都优先于写入命令(例如,列写入命令及行写入命令两者),与各种其它选择策略相比,这可提供改进系统性能(例如,经由减少的等待时间)。
每一命令232可接收多个优先级类别指定中的一者。优先级类别指定可对应于相应不同优先级队列248。例如,将接收对应于最高优先级的指定的命令插入最高优先级队列248-0中,将接收对应于第二高优先级的指定的命令插入第二高优先级队列248-1中等等。可基于各种因素来确定针对每一命令232的指定优先级类别,所述因素例如所述命令是读取命令还是写入命令、读取/写入命令的类型(例如,所述命令是列读取/写入命令还是行读取/写入入命令)以及命令的龄期以及其它因素。
在数个实施例中,使读取命令优先于写入命令,使得如果优先级队列248中的任一者含有读取命令,那么将不选择写入命令用于发布。然而,在包含优先化读取命令的数个实施例中,写入命令的优先级类别指定可取决于例如控制器204是否检测到与写入命令相关联的写入后读取相依性(例如,归因于确定写入命令针对与所接收读取命令232相同的页面)。与写入命令相关联的写入后读取相依性可导致将写入命令指定为与写入命令未与写入后读取相依性相关联的情况相比更高的优先级类别,使得将写入命令插入与其原本将被插入的相比更高的优先级队列248中,并且因此可在队列248中含有的一或多个读取命令之前发布。
如本文所使用,写入后读取相依性是指这样一种情形,其中:如果针对特定地址(例如,存储器的页面)的读取命令在将目标数据存储在目标页面处之前执行,那么可能导致错误(例如,因为尚未执行将目标数据写入目标页面的命令)。因而,在本发明的数个实施例中,如果优先级队列248包含任何读取命令,那么仅当检测到写入后读取相依性时,才选择写入命令来发布(例如,除非存在依赖于写入的读取,否则将不发布写入命令)。将写入命令插入与其原本将被插入的相比更高的优先级队列(例如,由于检测到的写入后读取相依性)可提供例如防止“死锁”情形的益处,在“死锁”情形中,不允许发布写入命令(例如,因为使读取命令优先于写入命令),但是由于写入后读取相依性,不允许发布对应读取命令。
如下文结合图3A及3B进一步描述,在其中使读取命令优先于写入命令的数个实施例中,可使列读取命令优先于行读取命令。例如,可将所接收列读取命令插入最高优先级队列248-0中,并且可将所接收行读取命令插入第二高优先级队列248-1中。在一些实例中,除非针对所接收写入命令检测到写入后读取相依性,否则可将所接收列写入命令插入较低优先级队列(例如,248-2到248-(k-1))。在数个实施例中,可使列写入命令优先于行写入命令,使得所接收行写入命令被插入与所接收列写入命令相比更低的优先级队列中。例如,可将所接收列写入命令插入第三高优先级队列248-2中,并且可将所接收行写入命令插入第四高优先级队列248-3中。如上所述,归因于检测到的写入后读取相依性,所以可将所接收写入命令指定为与读取命令相同的优先级类别,这可导致将写入命令插入较高优先级队列中的一者(例如,在写入命令到开放页面的情况下为248-0,且在写入命令到封闭页面的情况下为248-1)。
在操作中,一旦控制器204已根据命令选择策略将所接收命令232插入适当优先化队列248中,就从最高优先级队列248-0中的命令开始依序迭代通过队列248内的命令,并且选择遇到的确定为准备发布的第一命令。在一些实例中,响应于确定最高优先级队列248-0不含有可发布命令,控制器204搜索第二高优先级队列248-1并选择遇到的确定为可发布的第一命令。在数个实施例中,如果最高优先级队列248-0或第二高优先级队列248-1中的任一者当前含有命令,那么控制器204可经配置以防止从较低优先级队列选择任何命令。例如,在命令选择期间,优先级低于队列248-0及248-1的队列248在迭代通过队列248时可被忽略(例如,使得不会到达队列248-2及其以下的队列)。
在其中第一及第二高优先级队列248-0及248-1分别含有列读取命令及行读取命令的上文实例中,除非例如归因于确定写入后读取相依性(例如,因为将不到达队列248-2)而将写入命令插入队列248-0级248-1中的一者,否则将不选择任何写入命令用于发布。因此,在数个实施例中,如果最高优先级队列(例如,248-0及248-1)仅包含不可发布命令,那么甚至较低优先级队列(例如,248-2到248-(k-1))中的可发布命令也将不发布(例如,因为较低优先级队列将在迭代通过其以进行命令选择时被忽略)。
图3A及3B说明根据本发明的数个实施例的与实施命令选择策略相关联的流程图。图3A及3B中描述的方法可例如由例如上文描述的控制器104及/或204的控制器执行。结合图3A及3B描述的实例假设命令选择策略利用四个优先级队列(例如,图2中描述的优先化队列248),并且一般来说,其中使列读取命令优先于行读取命令,使行读取命令优先于列写入命令,并且使列写入命令优先于行写入命令。可设想优先级队列的其它数量并将其作为其它实例及实施方案。优先级队列可被称为“列表”或“目的地列表”。在图3A及3B中,指定符“i”用作参考命令队列中的所接收命令(例如,图2中所展示的令队列命230中的所接收命令232)的索引。指定符“DL”用作参考四个优先化队列的索引(例如,目的地列表DL=0至DL=-3)。指定符“k”是索引并且在迭代通过四个目的地列表时参考所述四个目的地列表。指定符“k”被用作索引并且在使用特定目的地列表迭代通过命令时参考特定目的地列表“k”内的命令。
图3A是与对所接收命令进行分类并基于所述分类将所接收命令插入优先化队列中的适当一者相关联,且图3B是与迭代通过优先化队列(及其中的命令),确定命令是否为可发布(例如,准备发布),选择用于发布的命令以及将选定命令发布到存储器装置相关联。
在360处,命令选择操作开始。在362处,将索引“i”初始化为“0”,并且在364处,确定命令队列(例如,230)是否包含待插入优先化列表中的一者的任何更多命令(例如,满足条件i=0指示命令队列为空)。如果没有更多所接收命令待排队,那么流程移动到图3B。然而,如果存在待添加到优先级队列的所接收命令,那么在366处,将索引“DL”初始化为“0”,并在368处,确定所接收命令队列中的“第i个”命令所针对的行是否以开放行为目标(例如,“第i个”命令是否为列命令)。响应于以封闭行为目标的“第i个”命令(例如,所述命令是行读取命令或行写入命令),在372处确定“第i个”命令是否为读取命令之前,在370处使索引“DL”递减(达1)。响应于“第i个”命令是读取命令,在376处将所述命令排队到列表“DL”。因此,如果“第i个”命令是列读取命令,其将被插入对应于DL=0的优先化队列(例如,最高优先级队列),且如果“第i个”命令是行读取命令,其将被插入对应于DL=-1的优先化队列(例如,第二高优先级队列)。在数个实施例中,对应于优先化队列的索引可从“0”开始并且减小,使得可将较低优先级队列附加到优先级队列列表的末尾,这通过提高在不对比较操作结果进行求反的情况下确定两个不同优先级队列的相对优先级的能力而可为有益的(例如,当且仅当m<n时,与具有索引“n”的队列相比,具有索引“m”的队列具有较低优先级)。如在380处所展示,在将“第i个”命令插入适当优先化队列中之后,使索引“i”递增(达1),使得评估所接收命令队列中的下一个命令,并且如果“第i个”命令以开放行为目标,那么在372处确定“第i个”命令是否为读取命令。
如果在372处确定“第i个”命令不是读取命令(例如,所述命令是写入命令),那么在374处,确定是否存在针对与当前写入命令相同的行的任何较新(例如,最近接收的)读取命令(例如,是否存在与当前写入命令相关联的写入后读取相依性)。如果存在到与当前写入命令相同的行的较新读取命令,那么在376处,将当前写入命令插入对应于DL=0的最高优先级队列中或插入对应于DL=-1的第二高优先级队列中。然而,如果当前写入命令所针对的行与较新读取命令不同,那么在378处,使索引“DL”递减(达2),然后在376处将所述写入命令插入适当优先级队列(376)。因此,如果写入命令所针对的行与较新读取命令不同,那么在其为列读取命令的情况下将其插入对应于DL=-2的优先级队列(例如,第三高优先级队列)中,并且在其为行读取命令的情况下将其插入对应于DL=-3的优先级队列(例如,在此实例中为最低优先级队列)中。
一旦在364处满足条件(例如,在所接收命令队列中没有更多的所接收命令要插入优先化队列中),那么在382处将索引“k”初始化为“0”。方框384表示用于确定是否已迭代通过所有四个优先化队列的检查。在此实例中,当在384处满足条件k=-4时,则完成命令选择操作,如在398处所展示。在385处,将索引“j”初始化为“0”,并且在386处,将索引“j”的当前值与对应于索引“k”的优先化队列中的命令数量进行比较。如果索引“j”的值不等于对应于索引“k”的优先化队列中的命令数量(例如,对应于索引“k”的队列包含尚待评估的命令),那么在387处,确定对应于索引“k”的优先化队列中的“第j个”命令是否是针对与较旧写入命令所针对的行相同的行的读取命令。
响应于确定“第j个”命令未指向与较旧写入命令相同的行,在389处确定“第j个”命令是否准备发布。如上所述,举例来说,控制器确定特定命令是否可发布可取决于与存储器装置相关联的各种时序参数。如果确定“第j个”命令准备就绪,那么在396处将所述命令发布到存储器装置,并且选择操作结束。如果在389处确定“第j个”命令尚未准备发布,那么在388处使索引“j”递增(达1),并再次执行在386处的比较。
响应于在387处确定“第j个”命令指向与较旧写入命令相同的行,在388处使索引“j”递增(达1),并再次执行在386处的比较。以此方式,在387处的检查确保在较旧写入发布之前,指向与所述较旧写入相同的行的读取命令将不会被发布。
如在386处所展示,一旦评估对应于索引“k”的优先化队列中所有命令,就在390处使索引“k”递减(达1)。在392处,执行是否k=-2的检查。如果“k”不等于-2,那么在384处执行是否k=-4的检查。
如果在392处k=-2,那么在394处确定最高优先级队列(例如,被指定为优先级“0”且对应于索引k=0的队列)及第二高优先级队列(例如,指定为优先级“-1”且对应于索引k=-1的队列)是否为空。如果两个最高优先级队列为空,那么命令选择过程在384处继续。然而,如果在394处将两个最高优先级队列确定为不为空,那么命令选择操作在398处结束,而不发布命令。以此类方式,如果两个最高优先级队列中的任一者含有任何命令,那么跳过具有与两个最高优先级队列相比更低的优先级的优先化队列。因此,在此实例中,其中将列读取命令插入最高优先级队列(例如,优先级队列“0”)并且将行读取命令插入第二高优先级队列(例如,优先级队列“-1”),如果在两个较高优先级队列中的任一者含有任何命令,那么将不选择两个较低优先级队列(例如,优先级队列“-2”及“-3”)中的任一者中的命令(例如,写入命令)来发布到存储器装置,即使其准备发布。防止较低优先级队列中的可发布写入命令在不可发布的读取命令之前发布可避免与在读取之前发布写入相关联地招致的等待时间损失。
与现有命令调度策略相比,根据本文描述的实施例使读取命令优先于写入命令可通过在考虑到写入后读取相依性的同时在写入之前调度读取来提供例如改进系统等待时间的益处以及各种其它益处。
图4说明根据本发明的数个实施例的与实施命令选择策略相关联的命令432的实例。在此实例中,命令432包含数个字段441(地址)、443(数据)、445(读取/写入)及447(状态)。实施例不限于特定命令结构、字段的数量等。在此实例中,字段441可包含命令的行及列地址,字段443可包含对应于命令的数据(例如,待存储在其中的数据或从存储器读取的数据),字段445可指示命令类型(例如,命令是读取还是写入),且字段447可指示可由命令选择策略使用的额外状态信息,例如命令的龄期以及命令是否针对当前开放行以及其它状态信息。
尽管本文已经说明及描述特定的实施例,但是所属领域的一般技术人员将了解,经计算以实现相同结果的布置可代替所展示的特定实施例。本发明希望覆盖本发明的各种实施例的改编或变型。应理解,上文描述是以说明性方式而不是限制性方式进行的。通过回顾上文描述,上文实施例的组合以及本文中未特定描述的其它实施例对于所属领域的技术人员将是显而易见的。本发明的各种实施例的范围包含使用上文结构及方法的其它应用。因此,本发明的各种实施例的范围应参考所附权利要求书以及此权利要求书所享有的等效物的全部范围来确定。
在前述具体实施方式中,出于简化本发明的目的,在单个实施例中将各种特征群组在一起。本发明的此方法不应被解释为反映以下意图:本发明的揭示实施例必须使用比每一权利要求中明确叙述的特征更多的特征。而是,如所附权利要求书所反映,发明标的物在于少于单个揭示实施例的所有特征。因此,所附权利要求书特此并入具体实施方式中,其中每一权利要求独立地作为单独实施例。

Claims (21)

1.一种用于命令选择的方法,其包括:
接收到存储器控制器的多个命令;
基于相应命令的类别,将所述多个命令中的每一命令插入多个优先级队列中的一者;以及
基于所述队列的优先级及所述至少一个命令的类别从所述优先级队列中的一者选择所述多个命令中的至少一个命令以将其发布到所述存储器控制器。
2.根据权利要求1所述的方法,其中将所述多个命令中的每一命令插入所述多个优先级队列中的一者中包括:使列读取命令及行读取命令优先于列写入命令及行写入命令。
3.根据权利要求1所述的方法,其进一步包括以优先级顺序迭代通过所述多个优先级队列,其中所述至少一个命令是至少部分基于所述迭代而选择。
4.根据权利要求3所述的方法,其中以优先级顺序迭代通过所述多个优先级队列包括:
通过迭代通过最高优先级队列中的所述命令来确定所述最高优先级队列是否含有可发布命令,其中所述多个优先级队列中的每一相应一者内的所述命令按由所述存储器控制器接收的顺序来进行优先化;以及
基于确定所述最高优先级队列含有可发布命令,向所述存储器装置发布所述可发布命令;或
通过基于确定所述最高优先级队列不含有可发布命令来迭代通过第二高优先级队列中的所述命令来确定第二高优先级队列是否含有可发布命令。
5.根据权利要求1到4中任一权利要求所述的方法,其中选择待发布到所述存储器装置的所述至少一个命令包括:阻止发布具有低于最高优先级队列的优先级的至少一个队列中的可发布命令。
6.根据权利要求1到4中任一权利要求所述的方法,其中将所述多个命令中的每一命令插入所述多个优先级队列中的一者中包括:
将列读取命令插入第一优先级队列中;
将行读取命令插入第二优先级队列中;以及
将写入命令插入第三优先级队列或第四优先级队列。
7.根据权利要求5所述的方法,其进一步包括:
确定对应于所述写入命令的写入后读取相依性;
将所述写入命令分类为另一列读取命令或另一行读取命令;以及
基于所述分类,将所述写入命令插入所述第一优先级队列或所述第二优先级队列中的一者。
8.根据权利要求5所述的方法,其进一步包括:将所述写入命令分类为列写入命令或行写入命令,其中基于所述分类将所述写入命令插入所述第三优先级队列或所述第四优先级队列中。
9.一种设备,其包括:
存储器装置;及
控制器,其耦合到所述存储器装置并且经配置以:
确定针对相应所接收命令的优先级类别;
基于每一所接收命令的经确定优先级类别,将每一所接收命令插入多个优先级队列中的选定一者中;以及
通过以优先级顺序迭代通过所述多个优先化队列来选择待发布到所述存储器装置的命令。
10.根据权利要求9所述的设备,其中所述控制器经配置以将第一类型的接收读取命令指定为第一优先级类别,并将其插入所述多个优先化队列中的第一优先级队列中。
11.根据权利要求10所述的设备,其中所述控制器经配置以将第二类型的接收读取命令指定为第二优先级类别,并将其插入所述多个优先化队列中的第二优先级队列中。
12.根据权利要求11所述的设备,其中所述第一类型的读取命令是列读取命令,且其中所述第二类型的读取命令是行读取命令。
13.根据权利要求11所述的设备,其中所述控制器经配置以:
维持至少第三优先级队列;
将所接收写入命令指定为第一类型或第二类型中的一者;
响应于确定所述所接收写入命令指向与先前读取命令不同的所述存储器装置的页面,将所述所接收写入命令插入所述至少第三优先级队列中;以及
响应于确定所述写入命令指向与至少一个先前读取命令相同的页面,将所述所接收写入命令插入所述第一优先级队列或所述第二优先级队列。
14.根据权利要求11所述的设备,其中所述控制器经配置以:
确定所述优先化队列中的命令是否可发布;
选择包含在所述第一优先级队列中并且经确定为可发布的第一命令来发布到所述存储器装置;
基于确定所述第一优先级队列不含有可发布命令,选择包含在所述第二优先级队列中并且经确定为可发布的第一命令来发布到所述存储器装置;以及
基于确定所述第一优先级队列或第二优先级队列中的任一者或两者当前都含有命令,防止从所述至少第三优先级队列中选择命令来发布到所述存储器装置。
15.根据权利要求11所述的设备,其中所述第一优先级队列是所述多个优先化队列中的最高优先级队列,且其中所述第二优先级队列是所述多个优先化队列中的第二高优先级队列。
16.根据权利要求9到15中任一权利要求所述的设备,其中所述控制器经配置以基于命令选择策略来选择待发布到所述存储器装置的命令,在所述命令选择策略中,如果所述优先化队列含有任何读取命令,那么不选择写入命令来发布到所述存储器装置,除非存在经确定为具有写入后读取相依性的读取命令。
17.一种控制器,其包括:
命令队列,其经配置以存储待发布到存储器装置的所接收命令;
多个优先化队列;及
逻辑,其用以:
确定相应所接收命令的优先级类别;
基于每一所接收命令的优先级类别将每一所接收命令插入所述多个优先化队列中的一者中,其中其优先级类别是基于:
对应于所述命令的命令类型;
所述命令是指向开放行还是封闭行;或
写入后读取相依性是否与所述命令相关联;
或任何其组合;及
通过以从最高优先级队列到最低优先级队列的优先级顺序迭代通过所述多个优先化队列,从所述多个优先化队列选择命令来发布到所述存储器装置。
18.根据权利要求17所述的控制器,其中迭代通过所述多个优先化队列包含:响应于确定较高优先级队列不含有可发布命令及含有至少一个不可发布命令而结束所述迭代。
19.根据权利要求11到18中任一权利要求所述的控制器,其中所述逻辑经配置以基于先备先到先服务FRFCFS策略来选择用于发布到所述存储器装置的命令,在所述策略中,使读取命令优先于写入命令,使得如果所述优先化队列含有任何读取命令,那么仅在确定写入命令与具有写入后读取相依性的读取命令相关联时,才选择所述写入命令用于发布到所述存储器装置。
20.一种方法,其包括:
将优先级类别指定到待发布到存储器装置的相应所接收命令;
基于每一所接收命令的指定优先级类别,将每一所接收命令插入多个优先化队列中的选定一者中,其中其指定优先级类别是基于:
对应于所述命令的命令类型;
所述命令是否指向开放行;或写入后读取相依性是否与所述命令相关联;或
任何其组合;以及
通过以从最高优先级队列到最低优先级队列的优先级顺序迭代通过所述多个优先化队列,从所述多个优先化队列选择命令来发布到所述存储器装置。
21.根据权利要求20所述的方法,其中仅在确定所接收写入命令具有对应写入后读取相依性时,才将所述所接收写入命令指定为与接收读取命令相同的优先级类别。
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