CN111527595A - 具有沿着半导体材料支柱的导电结构的组件以及形成集成电路的方法 - Google Patents

具有沿着半导体材料支柱的导电结构的组件以及形成集成电路的方法 Download PDF

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CN111527595A
CN111527595A CN201880083074.2A CN201880083074A CN111527595A CN 111527595 A CN111527595 A CN 111527595A CN 201880083074 A CN201880083074 A CN 201880083074A CN 111527595 A CN111527595 A CN 111527595A
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pillars
pillar
protective covering
linear
semiconductor material
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CN201880083074.2A
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山·D·唐
李宏
艾瑞卡·L·珀尔斯特拉
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Micron Technology Inc
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Micron Technology Inc
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Abstract

一些实施例包含一种组件，所述组件具有半导体材料支柱，所述半导体材料支柱布置成沿着第一方向延伸的行。所述行包含所述支柱之间的间隔区。所述行由间隙区彼此间隔开。两个导电结构处于所述间隙区中的每一个内且由分隔区彼此间隔开。所述分隔区具有底部区段，所述底部区段具有跨半导体段和绝缘段延伸的波状表面。所述半导体段具有在所述绝缘段的上表面之上的上表面；晶体管包含处于所述半导体材料支柱内的沟道区且包含处于所述导电结构内的栅极。一些实施例包含用于形成集成电路的方法。

Description

具有沿着半导体材料支柱的导电结构的组件以及形成集成电 路的方法
技术领域
具有沿着半导体材料支柱的导电结构的组件以及形成集成电路的方法。
背景技术
集成电路可包含竖直延伸的半导体材料支柱。这些支柱可以布置在阵列中。可认为所述阵列包括行和列；其中列与行交叉。
支柱可并入到晶体管中。晶体管可包括沿着所述支柱的导电栅极。导电字线可沿着阵列的行延伸，且可与晶体管的导电栅极电耦合。
晶体管可并入到存储器/存储装置、逻辑、感测器和/或任何其它合适的应用中。
集成电路制造的一个持续目标是增大整合密度，且一个相关目标是将装置缩放到越来越小的尺寸。将期望研发用于制造上文所描述的晶体管的改进方法，且期望研发包括这些晶体管的新架构。
附图说明
图1是处于实例过程阶段的组件的概略三维图。
图2是图1的组件的俯视图，且图2A是沿着图2的线A-A的横截面概略侧视图。
图3到11展示处于用于制造实例组件的实例方法的实例过程阶段的图1和2的构造。在一些实施例中，图6的组件可等同于图5的组件；其中图6之后的视图使用图6的说明方式而非图5的说明方式，以便简化图式。图3到11是组件的俯视图。图3A到11A是沿着图3到11的线A-A的视图，图7B到11B是沿着图7到11的线B-B的视图，图7C到11C是沿着图7到11的线C-C的视图，且图7D到11D是沿着图7到11的线D-D的视图。
图12是实例存储器阵列的概略示意图。
图13到16展示另一实例方法的实例过程阶段。图13的过程阶段可以跟随图6的过程阶段。图13A到16A是沿着图13到16的线A-A的视图，图13B到16B是沿着图13到16的线B-B的视图，图13C到16C是沿着图13到16的线C-C的视图，且图13D到16D是沿着图13到16的线D-D的视图。
图17和18展示另一实例方法的实例过程阶段。图17的过程阶段可以跟随图3的过程阶段。图17A和18A是沿着图17和18的线A-A的视图。
具体实施方式
一些实施例包含用于制造晶体管的方法。晶体管可具有处于竖直延伸的半导体材料支柱内的沟道区，且可具有沿着所述支柱的栅极。半导体材料支柱可形成于阵列内，其中这些阵列具有沿着第一方向延伸的行和沿着第二方向延伸的列，所述第二方向与所述第一方向相交。行最初可能包括与绝缘材料交替的半导体材料支柱。随后，绝缘材料可能凹陷，或甚至完全从半导体材料支柱之间移除，且接着导电线可形成为沿着半导体材料支柱的行延伸。导电线可包含对应于晶体管的栅极的区，且这些区可能部分地或甚至完全地环绕半导体材料支柱。半导体材料支柱可包括晶体管的沟道区，且晶体管栅极环绕半导体材料支柱可能有利地实现晶体管的操作期间的栅极与沟道区之间的强耦合。
根据本文中所描述的方法制造的晶体管可用于任何合适的应用；包括例如存储器/存储装置、逻辑、感测器等。
参考图1到18描述实例实施例。
参考图1到11描述用于制造实例集成电路的第一实例方法。
参考图1，组件(即，构造)10包括由基底12支撑的结构14。基底12可包括半导体材料；并且可能例如包括单晶硅、基本上由单晶硅组成或由单晶硅组成。可将基底12称作半导体衬底。术语“半导体衬底”意指包括半导体材料的任何构造，包含但不限于块体半导体材料，例如(单独或在包括其它材料的组件中的)半导体晶片，以及(单独或在包括其它材料的组件中的)半导体材料层。术语“衬底”是指任何支撑结构，包含但不限于上文所描述的半导体衬底。在一些应用中，基底12可对应于容纳与集成电路制造相关联的一或多种材料的半导体衬底。这类材料可包含例如耐火金属材料、阻隔材料、扩散材料、绝缘体材料等中的一或多个。间隙设置于衬底12与结构14之间，以指示基底12与结构14之间可能存在其它材料、电路等。举例来说，绝缘材料可设置于结构14与基底12之间。
结构14包括沿着第一方向延伸的多个导电线16，其中利用轴线5概略地指示第一方向。导电线16可对应于与存储器阵列相关联的数字线，且/或可对应于与逻辑、感测器等相关联的电路。
导电线16可包括任何合适的导电组合物；且在一些实施例中，可能例如包含以下中的一或多个：各种金属(例如钛、钨、钴、镍、钌、铂等)、含金属组合物(例如金属硅化物、金属氮化物、金属碳化物等)，和/或导电掺杂半导体材料(例如导电掺杂硅、导电掺杂锗等)。
第一轨道18位于导电线16正上方，且沿着轴线5的第一方向延伸。第二轨道20位于第一轨道18之间。第一轨道18和第二轨道20沿着第二方向彼此交替，其中利用轴线7概略地示出第二方向。由轴线7表示的第二方向与由轴线5表示的第一方向交叉。在一些实施例中，由轴线7表示的第二方向可基本上与由轴线5表示的第一方向正交，其中术语“基本上正交”意指在制造和测量的合理公差内正交。
第一轨道18包括半导体材料22，且第二轨道20包括绝缘材料24。
半导体材料22可包括任何合适的组合物或组合物组合；且在一些实施例中，可包括硅、锗、III/V材料、半导体氧化物等中的一或多个。
绝缘材料24可包括任何合适的组合物或组合物组合；且在一些实施例中，可包括二氧化硅、基本上由二氧化硅组成或由二氧化硅组成。
用保护性覆盖材料26覆盖第一轨道18。保护性覆盖材料26可包括任何合适的组合物或组合物组合；且在一些实施例中，可包括氮化硅、基本上由氮化硅组成或由氮化硅组成。
在一些实施例中，可将材料24和26分别称作第一材料和第二材料；其中可相对于第二材料26选择性地蚀刻第一材料24。
可利用任何合适的工艺制造图1的组件10。所属领域的一般技术人员将认识到用于制造这些组件的合适方法。
图1的三维图有助于解释轨道18与20之间的关系和结构14与下伏基底12之间的关系。然而，使用二维图(而非三维图)可以更容易地描述本发明的方法。因此，提供图2和2A以利用二维图说明构造10。图2展示构造10的俯视图，且图2A展示沿着图2的线A-A的横截面图。图2A中并不展示下伏基底12以便简化图式，但应理解，可设置适当的基底以支撑图2和2A的所说明结构。
参考图3和3A，第二轨道20相对于第一轨道18凹陷；且具体地说，第二轨道18的绝缘材料24相对于第一轨道18的保护性覆盖材料26和半导体材料22凹陷。可以利用一或多种适当的蚀刻来实现这种凹陷。凹陷形成沟槽28，其中这些沟槽沿着轴线5的第一方向延伸。在一些实施例中，可将沟槽28称作第一沟槽，以将所述沟槽28与后续过程期间形成的其它沟槽区分开来。
第二轨道20凹陷到深度D。这一深度可以是任何合适的深度，且在一些实施例中，处于从约20纳米(nm)到约100nm的范围内。在所展示的实施例中，第二轨道20凹陷到保护性覆盖材料26的底表面27下方的深度。
参考图4和4A，材料30形成在保护性覆盖材料26上方以及沟槽28内。在一些实施例中，可将材料26和30分别称作第一保护性覆盖材料和第二保护性覆盖材料。第二保护性覆盖材料30可包括与第一保护性覆盖材料26相同的组合物。举例来说，在一些实施例中，第一保护性覆盖材料26和第二保护性覆盖材料30均可包括氮化硅、基本上由氮化硅组成或由氮化硅组成。替代地，第二保护性覆盖材料30可包括相对于第一保护性覆盖材料26不同的组合物。举例来说，在一些实施例中，第二保护性覆盖材料30可包括碳掺杂二氧化硅、基本上由碳掺杂二氧化硅组成或由碳掺杂二氧化硅组成；而第一保护性覆盖材料26包括氮化硅、基本上由氮化硅组成或由氮化硅组成。尽管材料26和30展示为均质材料，但在一些实施例中，所述材料26和30中的一个或两个可包含两种或更多种不同的组合物。举例来说，(下文所描述的)图17和18说明第二保护性覆盖材料30包括氮化硅和二氧化硅两者的实施例。
在一些实施例中，保护性覆盖材料26和30为牺牲材料；且在这类实施例中，保护性材料26和30可包括具有合适的蚀刻性质的任何材料，包含金属、氧化物、氮化物、碳化物、硅化物等。
在一些实施例中，保护性材料26和30中的至少一个保留在最终构造中，且在这类实施例中，可能期望保留的保护性材料具有适合于其在集成电路中的保留位置的物理性质。举例来说，可能期望保留在最终构造中的保护性材料26和30的任何部分为电绝缘的。
参考图5和5A，对组件10进行合适的平坦化工艺(例如化学机械抛光)，以形成跨组件10的上表面延伸的平坦化表面29。在所说明实施例中，抛光从第一保护性覆盖材料26上方移除第二保护性覆盖材料30，同时留下沟槽28内的第二保护性覆盖材料30。
图5和5A将材料26和30展示为可彼此区分开的单独材料。然而，在一些实施例中，材料可以是彼此共同的组合物，且因此可合并以形成跨轨道18和20延伸的单个组合物。这种情况在图6和6A中予以说明，其中材料26和30合并以形成单个材料26/30。将简化之后的图式以仅展示单个保护性材料26/30，而非单独材料26和30。然而，应理解，即使图6之后的图式展示合并为单个材料26/30的材料26和30，但在一些实施例中，材料26和30可包括彼此不同的组合物而非包括共同的组合物。
参考图7到7D，沟槽32形成为沿着轴线7的第二方向延伸。沟槽32延伸穿过保护性覆盖材料26/30，且延伸到第一轨道18和第二轨道20中。沟槽32由中介区34(在一些实施例中，可将其称作中介线性结构)彼此间隔开。中介区34包括交替的第一支柱36和第二支柱38(如图7A中所展示)；其中第一支柱36包括半导体材料22，且第二支柱38包括绝缘材料24。在一些实施例中，可将沟槽32称作第二沟槽，以将其与上文参考图3所描述的第一沟槽28区分开来。
可认为半导体材料22的第一支柱36在沟槽32的形成之后图案化为行40，其中每一行沿着中介区34且沿着轴线7的第二方向延伸(在图7A的横截面图中可见行40中的一个)。可认为行40中的每一个内的第一支柱36(即，半导体材料支柱)由第二支柱38的绝缘材料24彼此间隔开。
沟槽32具有(图7、7C和7D中所展示的)侧壁边缘31和(图7B到7D中所展示的)底部边缘33。半导体支柱36具有沿着沟槽32的侧壁边缘31的侧壁37，且绝缘支柱38具有沿着侧壁边缘31的侧壁39。
沟槽32可由任何合适的工艺形成。举例来说，图案化掩模(未展示)可设置在组件10上方以定义沟槽32的位置，且可接着利用一或多个合适的蚀刻而将沟槽32蚀刻到材料22、24和26/30中。随后，可移除图案化掩模以留下图7到7D的构造。
在用以形成沟槽32的蚀刻期间可能出现的一个问题是可能以与绝缘材料24不同的方式蚀刻半导体材料22。举例来说，可能发现沿着绝缘材料支柱38的侧壁39的竖直度小于沿着半导体材料支柱36的侧壁边缘的侧壁37。理想地，侧壁应基本上为竖直的(其中术语“基本上竖直”意指在制造和测量的合理公差内竖直)。举例来说，可期望沟槽32的侧壁31相对于基底12(图1)的上表面正交(即，处于90°角的定向)，其中这些正交方向在图7C和7D中由轴线9表示。如果侧壁偏离竖直轴线9大于1.5°，那么沿着侧壁的锥度可能会干扰后续过程。在所说明应用中，沿着导电材料支柱36的侧壁37展示为基本上竖直(图7C)，但沿着绝缘材料支柱38的侧壁展示为非竖直的(图7D)。
参考图8到8D，绝缘材料支柱38(即，第二支柱)的侧壁39相对于半导体支柱36(即，第一支柱)的侧壁37凹陷。可以利用任何合适的蚀刻或蚀刻组合来实现这种凹陷，所述蚀刻或蚀刻组合包含例如相对于半导体材料22(例如硅)和保护性覆盖材料26/30(例如氮化硅)对氧化物材料24(例如二氧化硅)进行的选择性的湿式蚀刻。在一些实施例中，用以选择性地使绝缘材料38的侧壁39凹陷的蚀刻可利用氢氟酸、等离子体蚀刻和/或反应性离子蚀刻。
在所说明实施例中，蚀刻侧壁38直到所述侧壁基本上竖直为止且直到所述侧壁凹陷为相对于沿着中介区34的保护性覆盖材料26/30的侧壁边缘嵌入(如图8D中所展示)为止，其中这种嵌入在绝缘材料支柱38的上方留下保护性材料26/30的突出边缘42。
在绝缘材料支柱38的侧壁39凹陷之后，可认为沟槽32转换成沿着轴线7的第二方向延伸的线性导引件44。这些线性导引件具有侧壁区31，所述侧壁区31包括半导体支柱36的行40。线性导引件44具有沿着侧壁区31的侧壁段，其中这些侧壁段包括半导体支柱36的侧壁37且包括绝缘材料支柱38的侧壁39。在其它实施例(如下文参考图13到16所论述)中，使绝缘材料支柱38凹陷可从沿着行40的第二材料支柱36之间完全移除绝缘材料支柱38，且因此，线性导引件44的侧壁区31可包括半导体支柱36的侧壁37且并不包括绝缘材料支柱38的侧壁39。这样可有利地构造栅极环绕的组件，如下文参考图13到16更详细地论述。
参考图9到9D，沿着导引件区44的底部设置绝缘材料间隔件48(在图9B到9D中展示)。绝缘材料间隔件48可包括任何合适材料，例如二氧化硅、氮化硅等中的一或多个。绝缘材料间隔件最终用以相对于半导体支柱36偏置晶体管栅极的底部。所属领域的一般技术人员可确定绝缘材料间隔件48的适当厚度以实现所需偏置。
栅极介电材料46沿着半导体材料支柱36的侧壁37形成。在所展示的实施例中，栅极介电材料46在支柱36和38上方且沿着绝缘材料支柱38的侧壁39以及沿着半导体支柱36的侧壁37延伸。在栅极介电材料均匀地沉积在构造10的所有表面上的应用中可能会出现这种情况。在其它实施例中，栅极介电材料46可从支柱36的半导体材料22生长(例如，如果半导体材料22包括硅，那么栅极介电材料46可包括沿着硅的表面生长的二氧化硅)，且在这类实施例中，栅极介电材料46可仅沿着半导体材料支柱36的侧壁37形成。
导电材料50形成在栅极介电材料46上方。导电材料50可包括任何合适的组合物，例如以下中的一或多个：各种金属(例如钛、钨、钴、镍、钌、铂等)、含金属组合物(例如金属硅化物、金属氮化物、金属碳化物等)，和/或导电掺杂半导体材料(例如导电掺杂硅、导电掺杂锗等)。在一些实施例中，导电材料50可包括金属；且可包含例如钛、钽钨、钌、氮化钛、氮化钽、氮化钨等中的一或多个。
参考图10到10D，蚀刻导电材料50和栅极介电材料46。这种蚀刻使导电材料50形成为线性导电结构52。线性导电结构52沿着轴线7的第二方向延伸，且由栅极介电材料46与半导体材料支柱36间隔开。
在一些实施例中，线性导电结构52可并入到字线中。举例来说，在所展示实施例中，导电结构并入到字线55到59中。值得注意的是，每一字线包括一对线性导电结构52；其中每一字线的成对线性导电结构包含在一行半导体材料支柱36的一个侧面上的一个线性导电结构和在所述行半导体材料支柱36的相对侧上的另一线性导电结构。每一字线的成对线性导电结构彼此电耦合，如将由所属领域的一般技术人员所理解。这种耦合可出现在任何合适的位置处。
值得注意的是，导引件区44中的每一个内具有两个单独的线性导电结构52；其中单个导引件区内的线性导电结构中的每一个对应于不同字线的部分。举例来说，导引件区中的一个在图10C中标记为44a，且这一导引件区中具有两个线性结构52；其中线性结构中的一个对应于字线56的一部分，且另一个对应于字线57的一部分。
本文中所描述的过程有利地提供沿着绝缘柱38的基本上竖直侧壁(在图10D中展示)，这可以沿着导引件区44的整个跨度保持线性导电结构52之间的适当间隔。这样可消除相邻线性结构52之间的可能发生的不合需要的短路。另外，本文中所描述的过程有利地在绝缘材料支柱38上方形成保护性材料26/30的突出边缘42(在图10D中展示)。在一些应用中，这些突出区可定义线性导电结构52的顶表面的位置，如所展示。这可使得线性导电结构52易于图案化为适合于并入到晶体管中的配置(其中下文参考图11到11D描述实例晶体管)。
参考图11到11D，说明根据一种应用的组件10，在所述应用中，线性导电结构52并入到与存储器阵列60相关联的字线55到59中。字线55到59沿着半导体材料支柱36的行40的相对侧延伸。个别支柱36并入到晶体管62中；其中每一晶体管具有上部源极/漏极区64、下部源极/漏极区66以及上部源极/漏极区与下部源极/漏极区之间的沟道区68。用虚线指示上部源极/漏极区的近似下部边界，且同样用虚线指示下部源极/漏极区的近似上部边界。源极/漏极区64和66可掺杂有任何合适的导电性增强掺杂剂，且可为n型掺杂或p型掺杂。另外，沟道区62可掺杂有任何合适的掺杂剂，以达成所需阈值电压。掺杂剂可以在任何合适的过程阶段设置于源极/漏极区64和66以及沟道区62内。这一过程阶段可以是例如在图1的所说明过程阶段之前(针对掺杂剂中的至少一些)，且可以是在图10的过程阶段之后(针对所述掺杂剂中的其它掺杂剂)。
底部源极/漏极区66与数字线16耦合。
晶体管62由与字线55到59的邻近于半导体材料支柱36的且由栅极介电材料46与这些支柱间隔开的区相对应的栅极70进行门控。
在图11到11D的过程阶段移除保护性覆盖材料26/30。在其它实施例中，在晶体管62形成之后，可保留保护性覆盖材料中的至少一些。
存储器单元72与晶体管62的源极/漏极区64耦合。存储器单元72可包括任何合适的配置，且在一些实施例中，可以是电容器、相变存储器单元、电阻式随机存取存储器单元、导电桥接存储器单元等。
在操作中，存储器单元72中的每一个可由数字线16和字线55到59中的一个唯一地寻址。举例来说，图12示意性地说明包括存取晶体管62以及存储器单元72的实例存储器阵列60。存储器阵列还包括字线WL1、WL2和WL3以及数字线DL1、DL2、DL3和DL4。字线可对应于图11到11D中展示为字线55到59的类型的字线，且数字线可对应于图11到11D中展示为数字线16的类型的数字线。
图12的存取晶体管62包括与字线耦合的栅极、与数字线耦合的源极/漏极区以及与存储器单元耦合的其它源极/漏极区。在操作中，存储器单元72中的每一个可经由字线中的一个和数字线中的一个的组合唯一地寻址。
图12的字线WL1、WL2和WL3展示为延伸到电路74，且数字线DL1、DL2、DL3和DL4展示为延伸到电路76。在一些应用中，电路74可对应于驱动电路，且电路76可对应于感测电路。
尽管图11和12展示并入到存储器/存储装置中的晶体管构造，但应理解，本文中所描述的晶体管构造可替代地或另外地并入到逻辑、感测器或任何其它合适的电路中。
图11到11D的实施例形成仅部分地环绕半导体材料支柱36的字线55到59。在其它实施例中，字线可形成为完全环绕半导体材料支柱。参考图13到15描述这些其它实施例的实例。
参考图13到13D，说明处于可能在图7到7D的过程阶段之后的并可替代上文参考图8到8D描述的过程阶段的过程阶段的组件10。已从沿着行40的半导体材料支柱36之间完全移除绝缘材料24，从而在沿着行40的支柱36之间留下空隙(例如气隙)78(在图13A中展示)。
参考图14到14D，展示处于在图13到13D的过程阶段之后的并替代图9到9D的过程阶段的过程阶段的组件10。形成绝缘材料间隔件48。栅极介电材料46沿着半导体材料支柱36的侧壁形成，且在图14到14D的实施例中，所述栅极介电材料46选择性地形成在这些支柱的侧壁上。这类选择性形成可能在半导体材料22包括硅(或可被氧化以形成合适的栅极介电材料的其它材料)的应用中通过例如氧化柱侧壁而进行。导电材料50形成在栅极介电材料46上方且形成在支柱36上方。值得注意的是，导电材料50完全填充空隙区78，且由此填充沿着行40的半导体支柱36之间的空间(如图14A中所展示)。
参考图15到15D，展示处于在图14到14D的过程阶段之后的并替代图10到10D的过程阶段的过程阶段的组件10。蚀刻导电材料50以形成线性导电结构52。栅极介电材料46展示为沿着由导电材料50的蚀刻暴露的支柱36的区被移除(图15C)。在其它实施例中，可能并不沿着这些区移除栅极介电材料。
参考图16到16D，展示处于图15到15D的过程阶段之后的并替代图11到11D的过程阶段的过程阶段的组件10。有利的是，线性结构52完全环绕第二材料支柱36(如在图16中可见)。
晶体管62在图16到16D的过程阶段形成，且字线55到59沿着晶体管延伸。然而，相比于图11到11D的实施例，图16到16D的实施例具有完全环绕半导体材料支柱36的字线。因此，晶体管栅极可完全环绕半导体材料支柱36，这可改进栅极70与沟道区68之间的耦合。
如上文参考图4的过程阶段所提及，在一些应用中，保护性覆盖材料30可包括多种材料。图17和17A展示处于与图4和4A的过程阶段类似但其中保护性覆盖材料30包括两种组合物80和82的过程阶段的组件10。在一些应用中，组合物80可以是氧化物内衬；且可例如包括二氧化硅、基本上由二氧化硅组成或由二氧化硅组成。组合物82可例如包括氮化硅、基本上由氮化硅组成或由氮化硅组成。氧化物内衬80可减轻在含氮组合物82直接沉积在下伏材料中的一些上的情况下可能出现的不合需要的应力。另外或替代地，氧化物内衬可用作用以阻止电荷迁移到氮化硅组合物中的阻隔件，且因此缓解可能与含氮组合物82的电荷俘获特性相关联的问题。
参考图18和18A，展示处于在图17和17A的过程阶段之后(且确切地说，在用以形成平坦化上表面29的平坦化(例如抛光)之后)的过程阶段的构造10。随后，可对图18和18A的组件进行上文针对晶体管的制造所描述的过程。
一些实施例包含上文参考图11到11D和16到16D描述的类型的结构。可认为这些结构包括半导体材料22的支柱36，其中这些支柱布置在沿着轴线7的方向(在一些实施例中，可将所述方向称作第一方向)延伸的行40中。行包括支柱36之间的中介间隔区90(其中区90在图11A和16A中标记)。支柱具有处于第一高度H1的上表面，且中介间隔区包括间隔结构92，所述间隔结构92具有处于第二高度H2的上表面，所述第二高度H2小于所述第一高度。图11A的实施例展示间隔结构92(其为绝缘的)，且图16A的实施例展示间隔结构92(其为导电的)。
行40由间隙区94(图11和16)彼此间隔开，且线性导电结构52处于行40之间并在间隙区内沿着轴线7的第一方向延伸。线性结构52中的两个处于间隙区94中的每一个内，且由分隔区96(在图11B、11C、16B和16C中展示)彼此间隔开。分隔区96具有底部区段98(在图11B和16B中展示)，其中这些底部区段具有跨半导体段100和绝缘段102延伸的波状表面99。由于绝缘材料24已在图8到8D的过程阶段凹陷，因此半导体段100高于绝缘段102。半导体段100可比绝缘段102高出任何合适的量，且在一些实施例中，可至少高出约
Figure BDA0002550325650000101
至少高出约
Figure BDA0002550325650000102
至少高出约5nm等。在最终构造中，底部区段可由其它材料覆盖，且图16B展示底部区段上方的间隔材料48。
图11B和16B的实施例展示沿着轴线7(其中相对于图11和16的俯视图展示轴线7；且在图11B和16B中展示所述轴线7)的方向彼此交替的半导体段100和绝缘段102。在一些实施例中，可将轴线5和7的方向分别称作第一和第二方向；且在其它实施例中，可将轴线5和7的方向分别替代地称作第二和第一方向。
上文所论述的结构可并入到电子系统中。这类电子系统可用于例如存储器模块、装置驱动器、功率模块、通信调制解调器、处理器模块和应用专用模块中，且可包含多层、多芯片模块。电子系统可以是以下广泛范围的系统中的任一个：例如摄像机、无线装置、显示器、芯片组、机顶盒、游戏、照明、交通工具、时钟、电视、蜂窝电话、个人计算机、汽车、工业控制系统、飞机等。
除非另外指定，否则本文中所描述的各种材料、物质、组合物等可通过现在已知或待开发的任何合适的方法形成，所述方法包含例如原子层沉积(ALD)、化学气相沉积(CVD)、物理气相沉积(PVD)等。
术语“介电”和“绝缘”可用于描述具有绝缘电性质的材料。所述术语在本公开中被视为是同义的。在一些情况下术语“介电”和在其它情况下术语“绝缘”(或“电绝缘”)可用于在本公开内提供语言变化以简化以下权利要求书内的前提基础，而非用于指示任何显著化学或电学差异。
图式中的各种实施例的特定定向仅出于说明的目的，且在一些应用中，实施例可相对于所展示的定向旋转。本文所提供的描述和所附权利要求书涉及各种特征之间具有所描述关系的任何结构，不管结构是处于各图的特定定向还是相对于这类定向旋转。
除非另外规定，否则随附说明的横截面图仅展示横截面平面内的特征而不展示横截面平面后方的材料，以便简化图式。
当上述结构被称作“在另一结构上”或“抵靠另一结构”时，所述结构可直接在另一结构上或还可能存在中介结构。相比之下，当结构被称为“直接在另一结构上”或“直接抵靠”另一结构时，不存在中介结构。
结构(例如层、材料等)可称为“竖直地延伸”，以指示结构通常从下伏基底(例如衬底)朝上延伸。竖直延伸的结构可相对于或可不相对于基底的上表面基本上正交延伸。
一些实施例包含一种用于制造集成电路的方法。形成包括与第二轨道交替的第一轨道的组件。第一轨道包括半导体材料，且第二轨道包括绝缘材料。第一和第二轨道沿着第一方向延伸。用第一保护性覆盖材料覆盖第一轨道。第二轨道相对于第一轨道凹陷，其中第二轨道凹陷到第一保护性覆盖材料的底表面下方的深度。在凹陷的第二轨道上方形成第二保护性覆盖材料。形成沿着第二方向延伸的沟槽。第二方向与第一方向交叉。沟槽延伸穿过第一和第二保护性覆盖材料，且延伸到第一和第二轨道中。沟槽由包括交替的第一和第二支柱的中介线性结构彼此间隔开。第一支柱包括半导体材料，且第二支柱包括绝缘材料。中介线性结构中的每一个内的第一支柱配置为一行第一支柱。第二支柱的侧壁相对于第一支柱的侧壁凹陷。所述凹陷将沟槽转换到线性导引件中，所述线性导引件沿着第二方向延伸且具有包括所述行第一支柱的侧壁区。线性导引件具有沿着侧壁区的侧壁段，其中侧壁段包括第一支柱的侧壁。在使第二支柱的侧壁凹陷之后，沿着线性导引件的侧壁段形成栅极介电材料，且在线性导引件内并沿着栅极介电材料形成线性导电结构。线性导电结构沿着第二方向延伸。
一些实施例包含一种用于制造集成电路的方法。形成包括与第二轨道交替的第一轨道的组件。第一轨道包括半导体材料，且第二轨道包括绝缘材料。第一和第二轨道沿着第一方向延伸。用第一保护性覆盖材料覆盖第一轨道。第二轨道相对于第一轨道凹陷以形成沿着第一方向延伸的第一沟槽，其中第二轨道凹陷到第一保护性覆盖材料的底表面下方的深度。在第一沟槽内且在第一保护性覆盖材料上方形成第二保护性覆盖材料。使用平坦化工艺来从第一保护性覆盖材料上方移除第二保护性覆盖材料，同时留下第一沟槽内的第二保护性覆盖材料。形成沿着第二方向延伸的第二沟槽，其中第二方向与第一方向交叉。第二沟槽延伸穿过第一和第二保护性覆盖材料，且延伸到第一和第二轨道中。第二沟槽由包括交替的第一和第二支柱的中介区彼此间隔开。第一支柱包括半导体材料，且第二支柱包括绝缘材料。第二支柱的侧壁相对于第一支柱的侧壁凹陷。在使第二支柱的侧壁凹陷之后，沿着第一支柱形成栅极介电材料，且沿着栅极介电材料形成线性导电结构。线性导电结构沿着第二方向延伸。
一些实施例包含一种包含半导体材料支柱的组件。支柱布置成沿着第一方向延伸的行。所述行包括半导体材料支柱之间的中介间隔区。半导体材料支柱具有处于第一高度的上表面，且中介间隔区具有间隔结构，所述间隔结构具有处于低于第一高度的第二高度的上表面。行由间隙区彼此间隔开。线性导电结构处于行之间在间隙区内且沿着第一方向延伸。线性导电结构中的两个处于间隙区中的每一个内且由分隔区彼此间隔开。分隔区具有底部区段，所述底部区段具有跨半导体段和绝缘段延伸的波状表面。半导体段高于绝缘段。晶体管包括半导体材料支柱内的沟道区，且包括导电结构内的栅极。

Claims (26)

1.一种用于制造集成电路的方法，其包括：
形成包括与第二轨道交替的第一轨道的组件；所述第一轨道包括半导体材料，且所述第二轨道包括绝缘材料；所述第一轨道和所述第二轨道沿着第一方向延伸；用第一保护性覆盖材料覆盖所述第一轨道；
相对于所述第一轨道使所述第二轨道凹陷；所述第二轨道凹陷到所述第一保护性覆盖材料的底表面下方的深度；
在所述凹陷的第二轨道上方形成第二保护性覆盖材料；
形成沿着第二方向延伸的沟槽；所述第二方向与所述第一方向交叉；所述沟槽延伸穿过所述第一保护性覆盖材料和所述第二保护性覆盖材料，且延伸到所述第一轨道和所述第二轨道中；所述沟槽由包括交替的第一支柱和第二支柱的中介线性结构彼此间隔开；所述第一支柱包括所述半导体材料，且所述第二支柱包括所述绝缘材料；所述中介线性结构中的每一个内的所述第一支柱配置为一行所述第一支柱；
相对于所述第一支柱的侧壁使所述第二支柱的侧壁凹陷；所述凹陷将所述沟槽转换到线性导引件中，所述线性导引件沿着所述第二方向延伸且具有包括所述行所述第一支柱的侧壁区；所述线性导引件具有沿着所述侧壁区的侧壁段，其中所述侧壁段包括所述第一支柱的侧壁；以及
在所述使所述第二支柱的所述侧壁凹陷之后，沿着所述线性导引件的所述侧壁段形成栅极介电材料，且在所述线性导引件内并沿着所述栅极介电材料形成线性导电结构；所述线性导电结构沿着所述第二方向延伸。
2.根据权利要求1所述的方法，其中所述使所述第二支柱的所述侧壁凹陷从所述第一支柱之间移除所述第二支柱，且其中所述线性导电结构完全环绕所述第一支柱。
3.根据权利要求1所述的方法，其中所述使所述第二支柱的所述侧壁凹陷留下所述第二支柱的处于所述第一支柱之间的区，且其中所述线性导电结构并不完全环绕所述第一支柱。
4.根据权利要求1所述的方法，其中所述第一保护性覆盖材料和所述第二保护性覆盖材料彼此具有相同的组成。
5.根据权利要求4所述的方法，其中所述第一保护性覆盖材料和所述第二保护性覆盖材料包括氮化硅。
6.根据权利要求5所述的方法，其中所述绝缘材料包括二氧化硅。
7.根据权利要求1所述的方法，其中所述第二保护性覆盖材料相对于所述第一保护性覆盖材料具有不同组成。
8.根据权利要求1所述的方法，其中所述第二保护性覆盖材料包括碳掺杂二氧化硅。
9.根据权利要求1所述的方法，其中形成为沿着所述第二方向延伸的所述沟槽为第二沟槽；其中所述使所述第二轨道凹陷形成沿着所述第一方向延伸的第一沟槽；且其中所述形成所述第二保护性覆盖材料包括在所述第一沟槽内形成氧化物内衬以及接着利用氮化硅填充所述第一沟槽。
10.根据权利要求1所述的方法，其中所述线性导电结构中的两个形成于所述线性导引件中的每一个内，其中所述线性导引件中的每一个内的两个线性导电结构彼此间隔开。
11.根据权利要求10所述的方法，其中所述线性导电结构由字线包括；其中形成于所述线性导引件中的每一个内的所述两个线性导电结构由相对于彼此不同的字线包括；且其中同一行所述第一支柱的相对侧上的所述线性导电结构是共用字线的一部分。
12.根据权利要求1所述的方法，其中所述半导体材料包括硅。
13.根据权利要求1所述的方法，其中晶体管形成为包含所述线性导电结构的邻近于所述第一支柱的区和所述半导体材料的处于所述第一支柱内的区。
14.根据权利要求1所述的方法，其中所述线性导电结构由字线包括；其中晶体管形成为包含所述字线的邻近于所述第一支柱的区和所述半导体材料的处于所述第一支柱内的区；且进一步包括形成与所述晶体管耦合的存储器单元。
15.一种用于制造集成电路的方法，其包括：
形成包括与第二轨道交替的第一轨道的组件；所述第一轨道包括半导体材料，且所述第二轨道包括绝缘材料；所述第一轨道和所述第二轨道沿着第一方向延伸；用第一保护性覆盖材料覆盖所述第一轨道；
相对于所述第一轨道使所述第二轨道凹陷以形成沿着所述第一方向延伸的第一沟槽；所述第二轨道凹陷到所述第一保护性覆盖材料的底表面下方的深度；
在所述第一沟槽内以及在所述第一保护性覆盖材料上方形成第二保护性覆盖材料；
利用平坦化工艺来从所述第一保护性覆盖材料上方移除所述第二保护性覆盖材料，同时留下所述第一沟槽内的所述第二保护性覆盖材料；
形成沿着第二方向延伸的第二沟槽；所述第二方向与所述第一方向交叉；所述第二沟槽延伸穿过所述第一保护性覆盖材料和所述第二保护性覆盖材料，且延伸到所述第一轨道和所述第二轨道中；所述第二沟槽由包括交替的第一支柱和第二支柱的中介区彼此间隔开；所述第一支柱包括所述半导体材料，且所述第二支柱包括所述绝缘材料；
相对于所述第一支柱的侧壁使所述第二支柱的侧壁凹陷；以及
在所述使所述第二支柱的所述侧壁凹陷之后，沿着所述第一支柱形成栅极介电材料，且沿着所述栅极介电材料形成线性导电结构；所述线性导电结构沿着所述第二方向延伸。
16.根据权利要求15所述的方法，其中所述使所述第二支柱的所述侧壁凹陷从所述第一支柱之间移除所述第二支柱，且其中所述线性导电结构完全环绕所述第一支柱。
17.根据权利要求15所述的方法，其中所述使所述第二支柱的所述侧壁凹陷留下所述第二支柱的处于所述第一支柱之间的区，且其中所述线性导电结构并不完全环绕所述第一支柱。
18.根据权利要求15所述的方法，其中所述第一保护性覆盖材料和所述第二保护性覆盖材料彼此具有相同的组成。
19.根据权利要求15所述的方法，其中所述第一保护性覆盖材料和所述第二保护性覆盖材料包括氮化硅。
20.根据权利要求15所述的方法，其中晶体管形成为包含所述线性导电结构的邻近于所述第一支柱的区和所述半导体材料的处于所述第一支柱内的区。
21.根据权利要求15所述的方法，其中所述线性导电结构由字线包括；其中晶体管形成为包含所述字线的邻近于所述第一支柱的区和所述半导体材料的处于所述第一支柱内的区；且所述方法进一步包括形成与所述晶体管耦合的存储器单元。
22.一种组件，其包括：
半导体材料支柱，其中所述半导体材料支柱布置成沿着第一方向延伸的行；所述行包括所述半导体材料支柱之间的中介间隔区；所述半导体材料支柱具有处于第一高度的上表面，且所述中介间隔区包括间隔结构，所述间隔结构具有处于低于所述第一高度的第二高度的上表面；所述行由间隙区彼此间隔开；
线性导电结构，其处于所述行之间在所述间隙区内且沿着所述第一方向延伸；所述线性导电结构中的两个处于所述间隙区中的每一个内且由分隔区彼此间隔开；所述分隔区具有底部区段，所述底部区段具有跨半导体段和绝缘段延伸的波状表面；
所述半导体段高于所述绝缘段；
沟道区，其处于所述半导体材料支柱内；
栅极，其处于所述线性导电结构内；以及
晶体管，其包括所述沟道区和所述栅极。
23.根据权利要求22所述的组件，其中所述半导体段和所述绝缘段沿着所述第一方向彼此交替。
24.根据权利要求22所述的组件，其中所述间隔结构为绝缘的。
25.根据权利要求22所述的组件，其中所述间隔结构为导电的。
26.根据权利要求22所述的组件，其中所述线性导电结构由字线包括；且所述组件进一步包括：
数字线，其处于所述半导体材料支柱下方且沿着与所述第一方向相交的第二方向延伸；
存储器单元，其与所述晶体管耦合，其中所述存储器单元中的每一个由所述字线中的一个以及所述数字线中的一个唯一地寻址。
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US20200052113A1 (en) 2020-02-13
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US10461185B2 (en) 2019-10-29
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US11024735B2 (en) 2021-06-01
US20190198668A1 (en) 2019-06-27

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