CN111489977A - 半导体模块的制造方法 - Google Patents
半导体模块的制造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 125
- 238000000034 method Methods 0.000 title claims abstract description 43
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 229920005989 resin Polymers 0.000 claims abstract description 37
- 239000011347 resin Substances 0.000 claims abstract description 37
- 229920001187 thermosetting polymer Polymers 0.000 claims abstract description 12
- 239000007788 liquid Substances 0.000 claims abstract description 9
- 238000010438 heat treatment Methods 0.000 claims abstract description 4
- 239000011810 insulating material Substances 0.000 claims description 12
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 description 19
- 229910000679 solder Inorganic materials 0.000 description 14
- 239000000654 additive Substances 0.000 description 11
- 230000000996 additive effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 5
- 239000011256 inorganic filler Substances 0.000 description 5
- 229910003475 inorganic filler Inorganic materials 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000001816 cooling Methods 0.000 description 3
- 230000017525 heat dissipation Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 239000012766 organic filler Substances 0.000 description 2
- 230000001737 promoting effect Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000805 composite resin Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- ORQBXQOJMQIAOY-UHFFFAOYSA-N nobelium Chemical compound [No] ORQBXQOJMQIAOY-UHFFFAOYSA-N 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
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- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
本发明提供一种能够向由配置在半导体元件的两面的一对引线框架夹着的区域恰当地填充热固化性树脂并缩短填充所需时间的半导体模块的制造方法。具备半导体元件、在半导体元件的两面互相对置地配置的一对引线框架、以及从一对引线框架突出的引线端子的半导体模块的制造方法具备:在一对引线框架的一方的至少一个部位形成通孔的步骤;以夹着半导体元件的两面的方式配置一对引线框架的步骤;从通孔注入液体状的热固化性树脂,而将树脂填充到由一对引线框架夹着的区域的步骤;以及将填充到上述区域的树脂加热并固化的步骤。
Description
背景技术
本发明涉及一种半导体模块的制造方法。
已知在内置半导体元件(半导体芯片)的半导体模块中,向半导体模块的间隙填充液体状的热固化性树脂(底层填料)的技术。在日本特开2013-138177号公报中记载了在将多个半导体芯片堆叠安装的半导体模块的制造方法中,通过分配器向半导体芯片间的间隙滴下底层填料的技术。
发明内容
在半导体模块中,半导体元件伴随着高速化、高功能化而放出大量的热。因此,需要用于冷却半导体元件的冷却机构。一般使用引线框架作为半导体元件的冷却机构。发明者们研究了如下的方法:在结构为在由对置的一对引线框架夹着的区域中配置有半导体元件的半导体模块中,以底层填料填充由一对引线框架夹着的区域。
图14是发明者们预先研究过的、以底层填料7填充由一对引线框架531、532夹着的区域的方法。如图14所示,在由一对引线框架531、532夹着的区域中配置有半导体元件502、将热量从半导体元件502传导到引线框架531的间隔件506。半导体元件502、间隔件506、一对引线框架531、532由焊料505结合。由分配器21从一对引线框架531、532的外缘向由一对引线框架531、532夹着的区域注入底层填料7。然而,已知在从一对引线框架的外缘注入底层填料的情况下,填充的底层填料的构成成分的浓度在半导体元件附近的区域与其他的区域不同。此外,已知在上述方法中,不易注入底层填料7,为了用于量产,需要缩短向由一对引线框架531、532夹着的区域填充底层填料7所需的时间。
本发明是鉴于以上的背景而做出的,目的在于提供一种能够向由配置在半导体元件的两面的一对引线框架夹着的区域恰当地填充液体状的热固化性树脂并缩短填充所需时间的半导体模块的制造方法。
本发明是半导体模块的制造方法,该半导体模块具备半导体元件、在所述半导体元件的两面互相对置地配置的一对引线框架、以及从所述一对引线框架突出的引线端子,所述半导体模块的制造方法具备:在所述一对引线框架的一方的至少一个部位形成通孔的步骤;以夹着所述半导体元件的两面的方式配置所述一对引线框架的步骤;从所述通孔注入液体状的热固化性树脂,而将所述树脂填充到由所述一对引线框架夹着的区域的步骤;以及将填充到所述区域的所述树脂加热并固化的步骤。
在半导体模块中填充的树脂除了作为基材的主成分和固化剂之外,一般还添加有无机填料、有机填料等添加物,其中,该无机填料为二氧化硅、氧化铝等。在引线框架的一方的至少一个部位形成通孔,当从该通孔注入树脂时,易于向由一对引线框架夹着的区域注入树脂。因此,能够以添加物的含量更均匀的方式恰当地向该区域填充树脂。此外,还能够缩短填充所需的时间。
进而,可以在所述半导体模块中存在多个所述半导体元件,以位于在所述半导体模块中存在的多个所述半导体元件之中发热量最多的半导体元件附近的方式,形成所述通孔。
在半导体模块中填充的树脂中一般添加有氧化铝等促进热传导的成分。在从通孔注入了树脂时,在由一对引线框架夹着的区域中,与远离通孔的位置相比,靠近通孔的位置处的树脂中的添加物的含量比例更接近注入前的树脂中的添加物的含量比例。即,与远离通孔的位置相比,靠近通孔的位置处的树脂中包含的添加物的含量比例更高。因此,在半导体模块中,以位于发热量多的半导体元件的附近的方式形成通孔,从而能够高效地进行该半导体元件的散热。
进而,还可以具备以绝缘性材料涂覆所述引线端子的与所述一对引线框架连接的一侧的端部的步骤。
在半导体模块中,需要将半导体元件与引线端子合适地绝缘。引线端子的与一对引线框架连接的一侧的端部距半导体元件的距离近。以绝缘性材料涂覆该端部,从而能够将半导体元件与引线端子更加良好地绝缘。
根据本发明,能够向由在半导体元件的两面配置的一对引线框架夹着的区域恰当地填充热固化性树脂并缩短填充所需的时间。
根据下文给出的详细描述和附图,本公开的上述和其他目的、特征和优点将更加被充分地理解,详细描述和附图仅以示例方式给出,因此不应视为限制本公开。
附图说明
图1为示出适用实施方式1所涉及的半导体模块的制造方法的半导体模块的结构的一个示例的示意图。
图2为具体地说明实施方式1所涉及的半导体模块的制造方法的各工序的示意图。
图3为具体地说明实施方式1所涉及的半导体模块的制造方法的各工序的示意图。
图4为具体地说明实施方式1所涉及的半导体模块的制造方法的各工序的示意图。
图5为具体地说明实施方式1所涉及的半导体模块的制造方法的各工序的示意图。
图6为示出实施方式1所涉及的半导体模块的制造方法的处理流程的流程图。
图7为示出适用实施方式2所涉及的半导体模块的制造方法的半导体模块的外观的立体图。
图8为示出从图7所示的半导体模块移除了以底层填料封装的部分后的状态的立体图。
图9为沿着图8的VIII-VIII线的剖视图。
图10为图9的区域B的放大图。
图11为图9的区域C的放大图。
图12为图11的区域D的放大图。
图13为示出实施方式2所涉及的半导体模块的制造方法的处理流程的流程图。
图14是发明者们预先研究过的、以底层填料填充由一对引线框架夹着的区域的方法。
具体实施方式
以下,通过发明的实施方式来说明本发明,但权利要求书所涉及的发明不限于以下的实施方式。此外,在实施方式中说明的结构并非全部都是为了解决课题而必需的手段。此外,为了使说明明确化,以下的记载及附图被适当地省略以及简化。在各个附图中,对相同的要素赋予相同的附图标记,并根据需要省略了重复说明。
[实施方式1]
以下,参照附图对本发明的实施方式1进行说明。
首先,参照图1,对适用实施方式1所涉及的半导体模块的制造方法的半导体模块的结构进行说明。图1为示出适用实施方式1所涉及的半导体模块的制造方法的半导体模块1的结构的一个示例的示意图。如图1所示,半导体模块1具备半导体元件2、作为一对引线框架3的上部引线框架31以及下部引线框架32、和引线端子4。
半导体元件2例如为二极管、绝缘栅双极型晶体管(IGBT:Insulted Gate BipolarTrasistor)。作为一对引线框架3的上部引线框架31以及下部引线框架32在半导体元件2的两面互相对置地配置。上部引线框架31以及下部引线框架32是半导体模块1中作为内部布线使用的薄板形的金属板,由导电性高的金属——例如铜——来形成。此外,上部引线框架31以及下部引线框架32位于作为发热体的半导体元件2与散热器之间,承担作为用于提高散热器的散热效率的缓冲体即散热件的作用。
引线端子4分别从上部引线框架31和下部引线框架32突出。半导体元件2与上部引线框架31夹着间隔件6而结合。从上部引线框架31突出的引线端子4的与上部引线框架31连接的一侧的端部以绝缘性材料9涂覆。从下部引线框架32突出的引线端子4的与下部引线框架32连接的一侧的端部以绝缘性材料9涂覆。
间隔件6由与上部引线框架31相同种类的金属形成。上部引线框架31与间隔件6、间隔件6与半导体元件2、半导体元件2与下部引线框架32分别由焊料5结合。焊料5为回流焊料。由一对引线框架夹着的区域中填充有热固化性树脂即底层填料7。
接下来,对实施方式1所涉及的半导体模块的制造方法进行说明。
图2至图5为具体地说明实施方式1所涉及的半导体模块的制造方法的各工序的示意图。首先,如图2所示,在上部引线框架31形成通孔8(通孔形成工序)。另外,图2是从图1的箭头A的方向观察上部引线框架31。
接下来,如图3的上半部分所示,在下部引线框架32之上配置半导体元件2,在半导体元件2之上配置间隔件6,在间隔件6之上配置上部引线框架31(配置工序)。另外,在下部引线框架32与半导体元件2之间、半导体元件2与间隔件6之间、间隔件6与上部引线框架31之间配置有焊料5。接下来,如图3的下半部分所示,以加热器20加热而熔化焊料5,将一对引线框架3与半导体元件2结合(回流焊工序)。
接下来,如图4的上半部分所示,以氟树脂等绝缘性材料9涂覆从上部引线框架31突出的引线端子4的与上部引线框架31连接的一侧的端部(涂敷工序)。同样地,以绝缘性材料9涂覆从下部引线框架32突出的引线端子4的与下部引线框架32连接的一侧的端部(涂敷工序)。在半导体模块1中,需要将半导体元件2与引线端子4合适地绝缘。引线端子4的与一对引线框架3连接的一侧的端部距半导体元件2的距离近。以绝缘性材料9涂覆该端部,从而能够将半导体元件2与引线端子4更加良好地绝缘。
接下来,如图4的下半部分所示,由分配器21从通孔8注入液体状的热固化性树脂即底层填料7,而向由一对引线框架3夹着的区域填充底层填料7
(树脂填充工序)。在此,底层填料7例如是以环氧树脂为主成分的复合树脂。
在底层填料7中,除了作为基材的主成分和固化剂之外,还添加有用于降低热膨胀系数、提高树脂强度的二氧化硅、氧化铝等无机填料,用于缓和应力、提高粘合力的有机填料等添加物。无机填料中的氧化铝具有促进从作为发热体的半导体元件2到作为散热件的上部引线框架31以及下部引线框架32的热传导并提高散热效率的效果。当从上部引线框架31的通孔8注入底层填料7时,树脂易于进入由上部引线框架31与下部引线框架32夹着的区域。因此,能够以使无机填料等添加物的含量更均匀的方式恰当地向该区域填充底层填料7。此外,通过发明者们所做的实验,确认了当从上部引线框架31的通孔8注入底层填料7时,能够缩短填充所需时间。
接下来,如图5的上半部分所示,通过加热器20以规定的温度(例如140℃)将填充的底层填料7加热而固化(树脂固化工序)。接下来,如图5的下半部分所示,对完成的半导体模块1进行电性检查(检查工序)。
图6为示出实施方式1所涉及的半导体模块1的制造方法的处理流程的流程图。另外,在以下的说明中也酌情参照图1。如图6所示,首先,在一对引线框架3的一方的至少一个部位形成通孔8(步骤S101)。接下来,以夹着半导体元件2的两面的方式配置一对引线框架3(步骤S102)。另外,在一对引线框架3与半导体元件2之间配置焊料5。接下来,将配置的焊料5加热而熔化,将一对引线框架3与半导体元件2结合(步骤S103)。
接着步骤S103,以绝缘性材料9涂覆引线端子4的与一对引线框架3连接的一侧的端部(步骤S104)。接下来,从通孔8注入液体状的热固化性树脂即底层填料7,而向由一对引线框架3夹着的区域填充底层填料7(步骤S105)。接下来,将填充到由一对引线框架3夹着的区域的底层填料7加热而固化(步骤S106)。
如以上那样,在实施方式1所涉及的半导体模块的制造方法中,由分配器21从在上部引线框架31形成的通孔8将液体状的固化性树脂即底层填料7注入到由上部引线框架31与下部引线框架32夹着的区域。当像这样从上部引线框架31的通孔8注入树脂时,树脂易于进入由上部引线框架31与下部引线框架32夹着的区域,能够将树脂恰当地填充到该区域。此外,能够缩短填充所需的时间。
[实施方式2]
以下,参照附图对本发明的实施方式2进行说明。
首先,参照图7至图12,对适用实施方式2所涉及的半导体模块的制造方法的半导体模块的结构进行说明。图7为示出适用实施方式2所涉及的半导体模块的制造方法的半导体模块101的外观的立体图。图8为示出从图7所示的半导体模块101移除了以底层填料107封装的部分后的状态的立体图。图9为沿着图8的VIII-VIII线的剖视图。图10为图9的区域B的放大图。图11为图9的区域C的放大图。图12为图11的区域D的放大图。
如图7所示,半导体模块101的外侧被底层填料107封装。此外,如图8所示,半导体模块101具备作为半导体元件的IGBT 102a以及二极管102b、作为一对引线框架103的上部引线框架131以及下部引线框架132、和小电流侧引线端子104a以及大电流侧引线端子104b。
如图8以及图9所示,作为一对引线框架103的上部引线框架131以及下部引线框架132在IGBT 102a以及二极管102b的两面互相对置地配置。上部引线框架131以及下部引线框架132是半导体模块101中作为内部布线使用的薄板形的金属板,由导电性高的金属——例如铜——来形成。此外,上部引线框架131以及下部引线框架132位于作为发热体的半导体元件102与散热器之间,承担作为用于提高散热器的散热效率的缓冲体即散热件的作用。
在上部引线框架131形成有通孔108。以位于在半导体模块101中存在的多个半导体元件之中发热量最多的半导体元件的附近的方式,形成通孔108。半导体模块101具备作为半导体元件的IGBT 102a以及二极管102b,就发热量而言,二极管102b的更大。因此,以位于二极管102b附近的方式形成通孔108。在由上部引线框架131以及下部引线框架132夹着的区域中,填充有热固化性树脂即底层填料107(参照图7)。
如图9以及图10所示,二极管102b与上部引线框架131夹着间隔件106而结合。间隔件106由与上部引线框架131相同种类的金属形成。上部引线框架131与间隔件106、间隔件106与二极管102b、二极管102b与下部引线框架132分别由焊料105结合。焊料105为回流焊料。
如图9以及图11所示,IGBT 102a与上部引线框架131夹着间隔件106而结合。上部引线框架131与间隔件106、间隔件106与IGBT 102a、IGBT 102a与下部引线框架132分别由焊料105结合。
如图8、图9以及图10所示,大电流侧引线端子104b从下部引线框架132突出。大电流侧引线端子104b的与下部引线框架132连接的一侧的端部被氟树脂等绝缘性材料109涂覆。
如图8、图11以及图12所示,小电流侧引线端子104a经由铝线110与IGBT 102a连接。小电流侧引线端子104a的与IGBT 102a连接的一侧的端部以绝缘性材料109涂覆。
接下来,对实施方式2所涉及的半导体模块101的制造方法的处理流程进行说明。另外,在以下的说明中也酌情参照图8以及图9。
图13为示出实施方式2所涉及的半导体模块101的制造方法的处理流程的流程图。如图13所示,首先,在上部引线框架131形成通孔108(步骤S201)。接下来,以由作为一对引线框架103的上部引线框架131和下部引线框架132夹着作为半导体元件的IGBT 102a以及二极管102b的两面的方式,来配置一对引线框架103(步骤S202)。另外,在上部引线框架131与间隔件106之间、间隔件106与IGBT 102a以及二极管102b之间、IGBT 102a以及二极管102b与下部引线框架132之间,分别配置焊料105。接下来,将配置的焊料105加热而熔化,将一对引线框架3与IGBT 102a以及二极管102b结合(步骤S203)。
接着步骤S203,分别以绝缘性材料109涂覆小电流侧引线端子104a的与IGBT 102a连接的一侧的端部、大电流侧引线端子104b的与下部引线框架132连接的一侧的端部(步骤S204)。接下来,从通孔108注入液体状的热固化性树脂即底层填料107,而向由一对引线框架103夹着的区域填充底层填料107(步骤S205)。接下来,将填充到由一对引线框架103夹着的区域的底层填料107加热而固化(步骤S206)。
如以上那样,在实施方式2所涉及的半导体模块的制造方法中,以位于在半导体模块101中存在的多个半导体元件之中发热量最多的半导体元件、即二极管102b的附近的方式,形成通孔108。在半导体模块101中填充的底层填料107中一般添加有氧化铝等促进热传导的添加物。在从通孔108注入了底层填料107时,在由一对引线框架103夹着的区域中,与远离通孔108的位置相比,靠近通孔108的位置处的底层填料107中的添加物的含量比例更接近注入前的底层填料107中的添加物的含量比例。即,与远离通孔108的位置相比,靠近通孔108的位置处的底层填料107中包含的添加物的含量比例更高。因此,在半导体模块101中,以位于作为发热量多的半导体元件的二极管102b的附近的方式形成通孔108,从而能够高效地进行二极管102b的散热。
此外,本发明并不限定于上述实施方式,能够在不脱离主旨的范围内适当变更。
根据如此描述的公开,显而易见的是,可以以各种方式变更本公开的实施例。这些变更不应被认为脱离了本公开的主旨和范围,并且对于本领域普通技术人员而言显而易见的所有这种变更都包括在所附的权利要求书的范围内。
Claims (3)
1.一种半导体模块的制造方法,该半导体模块具备半导体元件、在所述半导体元件的两面互相对置地配置的一对引线框架、以及从所述一对引线框架突出的引线端子,所述半导体模块的制造方法具备:
在所述一对引线框架的一方的至少一个部位形成通孔的步骤;
以夹着所述半导体元件的两面的方式配置所述一对引线框架的步骤;
从所述通孔注入液体状的热固化性树脂,而将所述树脂填充到由所述一对引线框架夹着的区域的步骤;以及
将填充到所述区域的所述树脂加热并固化的步骤。
2.根据权利要求1所述的半导体模块的制造方法,其中,在所述半导体模块中存在多个所述半导体元件,
以位于在所述半导体模块中存在的多个所述半导体元件之中发热量最多的半导体元件附近的方式,形成所述通孔。
3.根据权利要求1或者2所述的半导体模块的制造方法,其中,还具备以绝缘性材料涂覆所述引线端子的与所述一对引线框架连接的一侧的端部的步骤。
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