CN111430449A - MOSFET device and preparation process thereof - Google Patents

MOSFET device and preparation process thereof Download PDF

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Publication number
CN111430449A
CN111430449A CN202010252825.8A CN202010252825A CN111430449A CN 111430449 A CN111430449 A CN 111430449A CN 202010252825 A CN202010252825 A CN 202010252825A CN 111430449 A CN111430449 A CN 111430449A
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region
layer
regions
conductivity type
well
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CN111430449B (en
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不公告发明人
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Sizhen Zhicheng Semiconductor Technology Shanghai Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The MOSFET device and the preparation method thereof provided by the invention have the advantages that the drift layer is provided with a plurality of well regions, the JFET regions are arranged between the adjacent well regions, and the depth L of the well regions1Is the depth L of the channel region2At least 3 times higher; the depth of the well region is increased to form a super junction structure with the JFET region, so that the resistance of the JFET region and the resistance of the drift region are obviously reduced, the resistance temperature coefficient of the device is improved, and the chip area of the device is reduced; meanwhile, the deeper well region is beneficial to reducing the surface electric field, so that stronger protection is provided for the gate oxide layer, and the characteristics and the reliability of the device are improved.

Description

MOSFET device and preparation process thereof
Technical Field
The invention relates to the field of semiconductor devices, in particular to a MOSFET device and a preparation process thereof.
Background
A power metal oxide semiconductor field effect transistor ("MOSFET") is a well-known type of semiconductor transistor that can be used as a switching device in high power applications, and can be turned on or off by applying a gate bias to the gate electrode of the device. When the power MOSFET is turned on (i.e., it is in its "on state"), current is conducted through the channel of the MOSFET. When the bias is removed from the gate electrode (or lowered below a threshold level), current stops conducting through the channel. For example, an n-type MOSFET is turned on when a gate bias sufficient to form a conductive n-type inversion layer in the p-type channel region of the device is applied. The n-type inversion layer electrically connects the n-type source and drain regions of the MOSFET, thereby allowing for majority carrier conduction therebetween.
Most semiconductor devices are formed of silicon ("Si"), and other semiconductor materials are also used. Silicon carbide ("SiC") is one of these materials. Silicon carbide has many excellent properties such as a suitable wide bandgap, high electric field breakdown strength, high thermal conductivity, high electron mobility, high melting point, and high saturated electron drift velocity. Therefore, SiC can break through the bottleneck of silicon materials, so that the power, temperature, frequency and radiation resistance of a power electronic system are multiplied, and the performances in the aspects of efficiency, reliability, volume and weight are also greatly improved. From system application, the system using the SiC device has obvious advantages, the conversion efficiency of a photovoltaic inverter in new energy power generation is improved to 98% from 96%, the overall efficiency of a charger, a boost converter and a driving inverter of an electric automobile is improved by 20%, the volume and the weight of a traction inverter of rail transit are reduced by 80%, the volume of a circuit breaker and a transformer of a power transmission and transformation system is reduced by 95%, and the loss is reduced by 80%. The application of SiC power devices in the fields of new energy automobiles, rail transit, industrial control, photovoltaic inversion, smart power grids, white appliances, big data/cloud computing centers and the like is continuously expanded, and the market status of SiC is continuously promoted.
Since the silicon carbide MOSFET is a unipolar device, the chip area for high current levels is larger for the same current density. In consideration of the high defect concentration of the existing SiC epitaxial material, the yield of large-size chips is remarkably reduced, so that the price disadvantage of SiC devices is more serious, and the large-scale application of the SiC devices in a power system is greatly restricted. Meanwhile, the existing MOSFET device has yet to be improved in terms of the characteristics and reliability of the device.
Disclosure of Invention
Therefore, the technical problem to be solved by the present invention is to provide a MOSFET device and a manufacturing process thereof, in which the characteristics and reliability of the existing MOSFET device are still subject to improvement.
According to an embodiment of the present invention, a MOSFET device is provided, comprising:
a drift layer having a first conductivity type;
the plurality of well regions are arranged on the drift layer, have a second conduction type and are arranged adjacent to the well regions at intervals;
the JFET area is arranged between the adjacent well areas and has a first conduction type; and the number of the first and second groups,
a channel region of the second conductivity type disposed in or over the well region having a depth L1Is the depth L of the channel region2At least 3 times higher; preferably 3 to 15 times.
In some embodiments, the charge balance of the well region and the JFET region, or both, is no more than 20% charge unbalanced; specifically, the doping concentration of the well region is 1x1016cm-3-5x1017cm-3The doping concentration of the JFET region is 1x1016cm-3-5x1017cm-3。
In some embodiments, the distance d between adjacent channel regions1Not less than the distance d of adjacent well regions2(ii) a Wherein the distance d between adjacent channel regions10.5-5 μm, the distance d between adjacent well regions2Is 0.2-5 μm.
In some embodiments, the MOSFET device further comprises a current spreading layer disposed on the drift layer and having a first conductivity type, wherein the JFET region is part of the current spreading layer, and the current spreading layer has a doping concentration of 1x1016cm-3-5x1017cm-3。
In some embodiments, the MOSFET device further comprises:
a source junction disposed in or on the well region;
the gate oxide layer is arranged on the JFET area and has a partial overlapping area with the source junction;
the gate electrode is arranged on the gate oxide layer;
the source electrode is arranged on the source electrode junction;
the substrate is arranged on one side, away from the well region, of the drift layer, and the drain electrode is arranged on one side, away from the drift layer, of the substrate.
In some embodiments, the substrate is made of silicon carbide.
In addition, the embodiment of the invention also provides a preparation process of the MOSFET device, which comprises the following steps:
forming a drift layer having a first conductivity type on a substrate;
forming a plurality of well regions having a second conductivity type and JFET regions having a first conductivity type on the drift layer, the JFET regions being formed between adjacent well regions;
forming a channel region of the second conductivity type in or over the well region to a depth L of the well region1Is the depth L of the channel region2At least 3 times higher; preferably 3 to 15 times.
In some embodiments, the process for manufacturing a MOSFET device further comprises: forming a current spreading layer having a first conductivity type on the drift layer, wherein the JFET region is part of the current spreading layer; the doping concentration of the current spreading layer is 1x1016cm-3-5x1017cm-3。
In some embodiments, the process for manufacturing a MOSFET device further comprises:
forming a source junction in or on the well region;
forming a gate oxide layer on the JFET area and a partial area on the source junction;
forming a gate electrode on the gate oxide layer;
forming a source electrode on the source electrode junction;
and forming a drain electrode on one side of the substrate, which faces away from the drift layer.
The technical scheme of the invention has the following advantages:
in the MOSFET device provided by the invention, a plurality of well regions are arranged on the drift layer, a JFET region is arranged between every two adjacent well regions, wherein the depth L of each well region1Is the depth L of the channel region2At least 3 times higher; by increasing the depth of the well region to form a super junction structure with the JFET region, the resistance of the JFET region and the drift region is remarkably reduced, and the resistance of the JFET region and the drift region is improvedThe resistance temperature coefficient of the device is reduced, so that the chip area of the device is reduced; meanwhile, the deeper well region is beneficial to reducing the surface electric field, so that stronger protection is provided for the gate oxide layer, and the characteristics and the reliability of the device are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a first schematic cross-sectional view of a MOSFET device provided in embodiment 1 of the present invention;
fig. 2 is a second schematic cross-sectional view of a MOSFET device provided in embodiment 2 of the present invention;
fig. 3 is a third schematic cross-sectional view of a MOSFET device provided in embodiment 3 of the invention;
fig. 4 is a fourth schematic cross-sectional view of a MOSFET device provided in embodiment 4 of the present invention;
fig. 5 is a fifth schematic cross-sectional view of a MOSFET device provided in embodiment 5 of the present invention;
fig. 6 is a sixth schematic cross-sectional view of a MOSFET device provided in embodiment 6 of the invention;
fig. 7 is a schematic cross-sectional view of a MOSFET device provided by comparative example 1 of the present invention;
fig. 8 is a graph showing the vertical electric field intensity distribution of the MOSFET devices shown in example 1 and comparative example 1;
fig. 9 is a graph comparing the magnitude of the resistances at room temperature of the MOSFET devices shown in example 1 and comparative example 1;
fig. 10 is a graph comparing the magnitude of the resistances at 150 ℃ of the MOSFET devices shown in example 1 and comparative example 1;
FIG. 11 is a graph illustrating an ion implantation profile of a JFET region and a well region according to an embodiment;
reference numerals:
1-a substrate; 2-a drift layer; 3-a well region; a 4-source junction; 41-a first conductive area; 42-a second conductive region; 5-a JFET region; 6-current spreading layer; 7-a channel region; 8-gate oxide layer; 9-a gate electrode; 10-a source electrode; 11-drain electrode.
Detailed Description
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. It will be understood that when an element or layer is referred to as being "on," "connected to" or "coupled with" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to" or "directly coupled with" another element or layer, there are no intervening elements or layers present. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Like numbers refer to like elements throughout.
It will be understood that, although the terms first and second are used herein to describe various regions, layers and/or elements, these regions, layers and/or elements should not be limited by these terms. These terms are only used to distinguish one region, layer or element from another region, layer or element. Thus, a first region, layer or element discussed below could be termed a second region, layer or element, and similarly, a second region, layer or element may be termed a first region, layer or element without departing from the scope of the present invention.
Relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can encompass both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, if the device on one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, elements, and/or components, but do not preclude the presence or addition of one or more other features, elements, components, and/or groups thereof.
Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations. Variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an implanted region shown as a rectangle will typically have rounded or curved features and/or an implant concentration gradient at its edges rather than a binary change from implanted to non-implanted region. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the present invention.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the present disclosure and relevant art and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The MOSFET device includes a plurality of "unit cells", wherein each unit cell includes two adjacent well regions, a source independent of each well region, a gate electrode and a drain common to both. Embodiments of the present invention are described herein with reference to cross-sectional views of a single unit cell of a MOSFET device. However, it should be understood that the present invention is not limited to MOSFET devices, and other power switching devices having at least one unit cell or at least one MOSFET transistor are also within the scope of the present application.
Under certain packaging techniques and conditions of maximum junction temperature, the chip area depends on the specific resistance value of the device. The characteristic resistance of the silicon carbide MOSFET device mainly comprises a channel resistance, a JFET area resistance, a substrate resistance and a drift layer resistance. The channel resistance is low voltage<650V) silicon carbide device, and the reduction of channel resistance lies in the development of novel SiC/SiO with low interface state2A gate oxidation and passivation process; the JFET resistance depends on the optimized design of the unit cell; the substrate resistance can be reduced by a substrate thinning process; the drift layer resistance is the main component of the high-voltage device, the higher the breakdown voltage is, the thicker the required drift layer is, the lower the doping concentration is, and the higher the resistance is. Particularly, the resistance value of the drift layer is increased by more than 3 times compared with the room temperature in high-temperature application, and the high-temperature current transport capacity of the silicon carbide MOSFET device is seriously reduced.
An embodiment of the present invention provides a MOSFET device, including:
a drift layer having a first conductivity type, for example the first conductivity type is N-type;
the plurality of well regions are arranged on the drift layer, are arranged at intervals adjacent to the well regions, and have a second conduction type, for example, the second conduction type is a P type;
a JFET region arranged between adjacent well regions and having a first conductivity type, for example, the first conductivity type is N-type; and the number of the first and second groups,
a channel region of the second conductivity type disposed in or on the well region at a depth L1Is the depth L of the channel region2At least 3 times higher; preferably 3 to 15 times.
According to the MOSFET device, the depth of the well region is increased to form a super junction structure with the JFET region, so that the resistance of the JFET region and the resistance of the drift region are obviously reduced, the resistance temperature coefficient of the device is improved, and the chip area of the device is reduced; meanwhile, the deeper well region is beneficial to reducing the surface electric field, so that stronger protection is provided for the gate oxide layer, and the characteristics and the reliability of the device are improved.
In some embodiments, the charge balance of the well region and the JFET region, or both, is no more than 20%; specifically, the doping concentration of the well region is 1x1016cm-3-5x1017cm-3Doping concentration of the JFET region is 1x1016cm-3-5x1017cm-3. It should be understood that it is difficult to balance the charges of the P-well and the JFET absolutely in actual manufacturing, so that the degree of charge imbalance does not exceed 20%, which falls within the protection scope of the present application.
In some embodiments, the distance d between adjacent channel regions1Not less than the distance d of adjacent well regions2So as to lower the surface doping of the channel and improve the carrier mobility; meanwhile, the length of the channel is increased, and the short-circuit tolerance of the device can be improved; wherein the distance d between adjacent channel regions10.5-5 μm, the distance d between adjacent well regions2Is 0.2-5 μm.
In some embodiments, the MOSFET device further includes a current spreading layer disposed on the drift layer and having the first conductivity type, wherein the JFET region is part of the current spreading layer. The doping concentration of the current spreading layer is 1x1016cm-3-5x1017cm-3. It is to be understood that in other embodiments, the current spreading layer may be omitted.
In some embodiments, the MOSFET device further comprises:
a source junction disposed in or on the well region; in some embodiments, the channel region is disposed in the well region and on a side of the source junction proximate to the JFET region;
the gate oxide layer is arranged on the JFET area and has a partial overlapping area with the source junction;
the gate electrode is arranged on the gate oxide layer;
the source electrode is arranged on the source electrode junction;
the substrate is arranged on one side, away from the well region, of the drift layer, and the drain electrode is arranged on one side, away from the drift layer, of the substrate. In one embodiment, the source junction includes a first conductive region and a second conductive region in contact with each other.
In some embodiments, the substrate is silicon carbide. It is to be understood that the solution of the present application is equally applicable to other types of substrates, such as gallium nitride, aluminum nitride or silicon.
In addition, the embodiment of the invention also provides a preparation process of the MOSFET device, which comprises the following steps:
forming a drift layer having a first conductivity type on a substrate; specifically, the drift layer may be formed on the substrate by epitaxial growth, ion implantation, or tilted ion implantation;
forming a plurality of well regions with a second conductivity type and JFET regions with a first conductivity type on the drift layer, wherein the JFET regions are formed between adjacent well regions; specifically, the well region can be formed by high-energy ion implantation or channel ion implantation, and the JFET can be formed by high-energy ion implantation or channel ion implantation;
forming a channel region of the second conductivity type in or over the well region to a depth L of the well region1Is the depth L of the channel region2At least 3 times higher; preferably 3 to 15 times.
In some embodiments, the process for manufacturing a MOSFET device further comprises: forming a current spreading layer of the first conductivity type on the drift layer, wherein the JFET region is one of the current spreading layersA moiety; the doping concentration of the current spreading layer is 1x1016cm-3-5x1017cm-3。
In some embodiments, the process for manufacturing a MOSFET device further comprises:
forming a source junction in or on the well region;
forming a gate oxide layer on the JFET area and a part of area on the source junction;
forming a gate electrode on the gate oxide layer;
forming a source electrode on the source electrode junction;
and forming a drain on the side of the substrate away from the drift layer.
It is to be understood that the channel region may be deeper than the source junction, extending beyond the source junction. In some embodiments, the channel region includes two portions below the source junction and on a side of the source junction near the current spreading layer, the two portions are connected with each other and may be formed simultaneously or separately; the specific formation method may be an ion implantation method.
In order to explain the technical scheme of the invention in detail, the following specific embodiments are provided:
example 1
The present embodiment provides a MOSFET device and a process for manufacturing the same, as shown in fig. 1, the MOSFET device includes:
substrate 1 of a first conductivity type, for example N-type, dopant of phosphorus or nitrogen, and dopant concentration greater than 5 × 1018cm-3(ii) a Specifically, the substrate 1 is made of silicon carbide;
a drift layer 2 disposed on the substrate 1 and having a first conductivity type, such as N-type, dopant selected from phosphorus and nitrogen, and doping concentration of 1 × 1014cm-3-5x1017cm-3；
A plurality of well regions 3 arranged on the drift layer 2 and spaced from each other by a distance d20.2-5 μm, and has a second conductivity type, for example, the second conductivity type is P-type, the dopant can be aluminum, boron, gallium, and the doping concentration is 1x1016cm-3-5x1017cm-3；
The current expansion layer 6 is arranged between the adjacent well regions 3 and the adjacent source electrode junctions 4, extends to the lower part of the adjacent well regions 3, and has the upper surface flush with the upper surfaces of the source electrode junctions 4; the current spreading layer has a first conductivity type, such as N-type, and the dopant is phosphorus or nitrogen with a doping concentration of 1 × 1016cm-3-5x1017cm-3(ii) a The JFET region 5 is formed by the part of the current expansion layer between the adjacent well regions to form a super junction structure with the well region 3, the charge balance between the well region and the JFET region or the charge unbalance degree of the well region and the JFET region is not more than 20%, and the doping concentration of the JFET region is 1x1016cm-3-5x1017cm-3；
A source junction 4 disposed in or on the well region 3 and comprising a first conductive region 41 and a second conductive region 42 in contact with each other, wherein the first conductive region has a first conductivity type, such as N, a dopant selected from phosphorus and nitrogen, and a doping concentration greater than 5 × 1018cm-3The second conductive region has a second conductivity type, such as P type, and the dopant is Al, B, or Ga with a doping concentration of more than 5 × 1018cm-3；
A channel region 7 disposed in the well region and on the side of the source junction 4 near the JFET region 5, specifically below the source junction 4 and on the side of the source junction 4 near the current spreading layer 6, and a well region depth L1Is the depth L of the channel region2At least 3 times, preferably 3 to 15 times; distance d between adjacent channel regions1Not less than the distance d of adjacent well regions2Distance d of adjacent channel regions10.5-5 μm;
the gate oxide layer 8 is arranged on the current expansion layer 6 and has a partial overlapping region with the source junction 4;
a gate electrode 9 disposed on the gate oxide layer 8;
a source electrode 10 disposed on the source junction 4;
and the drain electrode 11 is arranged on one side of the substrate 1, which is far away from the drift layer 2.
The preparation process of the MOSFET device comprises the following steps:
(1) forming a drift layer 2 having a first conductivity type on a substrate 1 by means of epitaxial growth, ion implantation or tilted ion implantation;
(2) forming a current spreading layer 6 having a first conductivity type on the drift layer 2 by epitaxial growth, ion implantation or tilted ion implantation;
(3) forming a plurality of well regions 3 with a second conductivity type, channel regions 7 with the second conductivity type and JFET regions 5 with the first conductivity type on the current spreading layer 6 by high-energy ion implantation or channel ion implantation, wherein the JFET regions are formed between adjacent well regions, and FIG. 11 is a schematic view of ion implantation curves of the JFET regions and the well regions, wherein the implantation energy can be 900KeV, and the depth L of the well regions is ensured1Is the depth L of the channel region2At least 3 times higher; preferably 3 to 15 times;
(4) forming a first mask layer (e.g., silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) in the well region 3, etching the first mask layer by a dry or wet etching process to form a first opening to expose the well region 3, and implanting a dopant into the well region 3 through the first opening by ion implantation to form a first conductive region 41 having a first conductivity type, such as N-type, which may be phosphorus or nitrogen; etching the first mask layer near the first opening by a dry or wet etching process, forming a second mask layer (e.g., silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) in the well region 3, etching the second mask layer by the dry or wet etching process to form a second opening to expose the well region 3, and implanting a dopant, which may be aluminum, boron, or gallium, in the well region 3 by ion implantation through the second opening to form a second conductive region 42 having a second conductivity type, such as the second conductivity type being P-type, in the well region 3, thereby obtaining a source junction 4;
(5) etching the remaining second mask layer by a dry etching process or a wet etching process, and then sequentially annealing and cleaning the surface; then, a mask layer is formed and selective etching is performed to form a gate oxide layer 8, a gate electrode 9, a source electrode 10 and a drain electrode 11.
Example 2
The present embodiment provides a MOSFET device and a process for manufacturing the same, as shown in fig. 2, the MOSFET device includes:
substrate 1 of a first conductivity type, for example N-type, dopant of phosphorus or nitrogen, and dopant concentration greater than 5 × 1018cm-3(ii) a Specifically, the substrate 1 is made of silicon carbide;
a drift layer 2 disposed on the substrate 1 and having a first conductivity type, such as N-type, dopant selected from phosphorus and nitrogen, and doping concentration of 1 × 1014cm-3-5x1017cm-3；
A plurality of well regions 3 arranged on the drift layer 2 and spaced from each other by a distance d20.2-5 μm, and has a second conductivity type, for example, the second conductivity type is P-type, the dopant can be aluminum, boron, gallium, and the doping concentration is 1x1016cm-3-5x1017cm-3；
The current expansion layer 6 is arranged between the adjacent well regions 3, extends to the lower part of the adjacent well regions 3, and the upper surfaces of the current expansion layer and the source electrode junction 4 are flush with the upper surfaces of the well regions 3; the current spreading layer 6 has a first conductivity type and a doping concentration of 1x1016cm-3-5x1017cm-3For example, the first conductivity type is N-type, and the dopant can be phosphorus or nitrogen; wherein, the part of the current spreading layer 6 between the adjacent well regions 3 forms a JFET region 5 to form a super junction structure with the well regions, the charge balance or the charge unbalance degree of the well region and the JFET region is not more than 20%, and the doping concentration of the JFET region is 1x1016cm-3-5x1017cm-3；
A source junction 4 disposed in or on the well region 3 and comprising a first conductive region 41 and a second conductive region 42 in contact with each other, wherein the first conductive region has a first conductivity type, such as N, a dopant selected from phosphorus and nitrogen, and a doping concentration greater than 5 × 1018cm-3(ii) a The second conductive region having a second conductivity type, e.g. second conductivityThe type is P type, the dopant can be aluminum, boron and gallium, and the doping concentration is more than 5 × 1018cm-3；
A channel region 7 disposed in the well region and located below the source junction 4, a distance d between adjacent channel regions 71Not less than the distance d of adjacent well regions 32Distance d of adjacent channel regions 710.5-5 μm;
the gate oxide layer 8 is arranged on the JFET region 5 and the well region 3 and has a partial overlapping area with the source junction 4;
a gate electrode 9 disposed on the gate oxide layer 8;
a source electrode 10 disposed on the source junction 4;
and the drain electrode 11 is arranged on one side of the substrate 1, which is far away from the drift layer 2.
The preparation process of the MOSFET device comprises the following steps:
(1) forming a drift layer 2 having a first conductivity type on a substrate 1 by means of epitaxial growth, ion implantation or tilted ion implantation;
(2) forming a current spreading layer 6 having a first conductivity type on the drift layer 2 by epitaxial growth, ion implantation or tilted ion implantation;
(3) forming a plurality of well regions 3 with a second conductivity type, channel regions 7 with the second conductivity type and JFET regions 5 with the first conductivity type on the current spreading layer 6 by high-energy ion implantation or channel ion implantation, wherein the JFET regions 5 are formed between adjacent well regions 3, FIG. 11 is a schematic view of the ion implantation curves of the JFET regions and the well regions, the implantation energy can be 900KeV, and the depth L of the well regions is ensured1Is the depth L of the channel region2At least 3 times higher; preferably 3 to 15 times;
(4) forming a first mask layer (e.g., silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) in the well region 3, etching the first mask layer by a dry or wet etching process to form a first opening to expose the well region 3, and implanting a dopant into the well region 3 through the first opening by ion implantation to form a first conductive region 41 having a first conductivity type, such as N-type, which may be phosphorus or nitrogen; etching the first mask layer near the first opening by a dry or wet etching process, forming a second mask layer (e.g., silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) in the well region 3, etching the second mask layer by the dry or wet etching process to form a second opening to expose the well region 3, and implanting a dopant, which may be aluminum, boron, or gallium, in the well region 3 by ion implantation through the second opening to form a second conductive region 42 having a second conductivity type, such as the second conductivity type being P-type, in the well region 3, thereby obtaining a source junction 4;
(5) etching the remaining second mask layer by a dry etching process or a wet etching process, and then sequentially annealing and cleaning the surface; then, a mask layer is formed and selective etching is performed to form a gate oxide layer 8, a gate electrode 9, a source electrode 10 and a drain electrode 11.
Example 3
The present embodiment provides a MOSFET device and a process for manufacturing the same, as shown in fig. 3, the MOSFET device includes:
substrate 1 of a first conductivity type, for example N-type, dopant of phosphorus or nitrogen, and dopant concentration greater than 5 × 1018cm-3(ii) a Specifically, the substrate 1 is made of silicon carbide;
a drift layer 2 disposed on the substrate 1 and having a first conductivity type, such as N-type, dopant selected from phosphorus and nitrogen, and doping concentration of 1 × 1014cm-3-5x1017cm-3；
A plurality of well regions 3 arranged on the drift layer 2 and spaced from each other by a distance d20.2-5 μm, and has a second conductivity type, for example, the second conductivity type is P-type, the dopant can be aluminum, boron, gallium, and the doping concentration is 1x1016cm-3-5x1017cm-3；
The current expansion layer 6 is arranged between the adjacent well regions 3, extends to the lower part of the adjacent well regions 3, and the upper surfaces of the current expansion layer and the source electrode junction 4 are flush with the upper surfaces of the well regions 3; the current spreading layer 6 has a first conductivity type, dopedImpurity concentration of 1x1016cm-3-5x1017cm-3For example, the first conductivity type is N-type, and the dopant can be phosphorus or nitrogen; wherein, the part of the current spreading layer 6 between the adjacent well regions 3 forms a JFET region 5 to form a super junction structure with the well regions, the charge balance or the charge unbalance degree of the well region and the JFET region is not more than 20%, and the doping concentration of the JFET region is 1x1016cm-3-5x1017cm-3；
A source junction 4 disposed in or on the well region 3 and comprising a first conductive region 41 and a second conductive region 42 in contact with each other, wherein the first conductive region has a first conductivity type, such as N, a dopant selected from phosphorus and nitrogen, and a doping concentration greater than 5 × 1018cm-3The second conductive region has a second conductivity type, such as P type, and the dopant is Al, B, or Ga with a doping concentration of more than 5 × 1018cm-3；
A channel region 7 disposed in the well region and on the side of the source junction 4 near the JFET region 5, specifically below the source junction 4 and on the side of the source junction 4 near the current spreading layer 6, and a well region depth L1Is the depth L of the channel region2At least 3 times, preferably 3 to 15 times; distance d between adjacent channel regions1Not less than the distance d of adjacent well regions2Distance d of adjacent channel regions10.5-5 μm;
the gate oxide layer 8 is arranged on the current expansion layer 6 and has a partial overlapping region with the source junction 4;
a gate electrode 9 disposed on the gate oxide layer 8;
a source electrode 10 disposed on the source junction 4;
and the drain electrode 11 is arranged on one side of the substrate 1, which is far away from the drift layer 2.
The preparation process of the MOSFET device comprises the following steps:
(1) forming a drift layer 2 having a first conductivity type on a substrate 1 by means of epitaxial growth, ion implantation or tilted ion implantation;
(2) forming a current spreading layer 6 having a first conductivity type on the drift layer 2 by epitaxial growth, ion implantation or tilted ion implantation;
(3) forming a plurality of well regions 3 with a second conductivity type, channel regions 7 with the second conductivity type and JFET regions 5 with the first conductivity type on the current spreading layer 6 by high-energy ion implantation or channel ion implantation, wherein the JFET regions 5 are formed between adjacent well regions 3, FIG. 11 is a schematic view of the ion implantation curves of the JFET regions and the well regions, the implantation energy can be 900KeV, and the depth L of the well regions is ensured1Is the depth L of the channel region2At least 3 times higher; preferably 3 to 15 times;
(4) forming a first mask layer (e.g., silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) in the well region 3, etching the first mask layer by a dry or wet etching process to form a first opening to expose the well region 3, and implanting a dopant into the well region 3 through the first opening by ion implantation to form a first conductive region 41 having a first conductivity type, such as N-type, which may be phosphorus or nitrogen; etching the first mask layer near the first opening by a dry or wet etching process, forming a second mask layer (e.g., silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) in the well region 3, etching the second mask layer by the dry or wet etching process to form a second opening to expose the well region 3, and implanting a dopant, which may be aluminum, boron, or gallium, in the well region 3 by ion implantation through the second opening to form a second conductive region 42 having a second conductivity type, such as the second conductivity type being P-type, in the well region 3, thereby obtaining a source junction 4;
(5) etching the remaining second mask layer by a dry etching process or a wet etching process, and then sequentially annealing and cleaning the surface; then, a mask layer is formed and selective etching is performed to form a gate oxide layer 8, a gate electrode 9, a source electrode 10 and a drain electrode 11.
Example 4
The present embodiment provides a MOSFET device and a process for manufacturing the same, as shown in fig. 4, the MOSFET device includes:
a substrate 1 of a first conductivity typeFor example, the first conductivity type is N-type, the dopant can be P or N, and the doping concentration is greater than 5 × 1018cm-3(ii) a Specifically, the substrate 1 is made of silicon carbide;
a drift layer 2 disposed on the substrate 1 and having a first conductivity type, such as N-type, dopant selected from phosphorus and nitrogen, and doping concentration of 1 × 1014cm-3-5x1017cm-3；
A plurality of well regions 3 arranged on the drift layer 2 and spaced from each other by a distance d20.2-5 μm, and has a second conductivity type, for example, the second conductivity type is P-type, the dopant can be aluminum, boron, gallium, and the doping concentration is 1x1016cm-3-5x1017cm-3；
The JFET area 5 is arranged between the adjacent well regions 3 and the adjacent source electrode junctions 4, extends to the lower part of the adjacent well regions 3, and has the upper surface flush with the upper surfaces of the source electrode junctions 4 so as to form a super junction structure with the well regions 3; the JFET region 5 has a first conductivity type, for example, the first conductivity type is N-type, the dopant can be phosphorus or nitrogen, the charge balance between the well region and the JFET region or the charge imbalance between the well region and the JFET region is not more than 20%, and the JFET region has a doping concentration of 1x1016cm-3-5x1017cm-3；
A source junction 4 disposed in or on the well region 3 and comprising a first conductive region 41 and a second conductive region 42 in contact with each other, wherein the first conductive region has a first conductivity type, such as N, a dopant selected from phosphorus and nitrogen, and a doping concentration greater than 5 × 1018cm-3The second conductive region has a second conductivity type, such as P type, and the dopant is Al, B, or Ga with a doping concentration of more than 5 × 1018cm-3；
A channel region 7 disposed in the well region and on the side of the source junction 4 near the JFET region 5, specifically below the source junction 4 and on the side of the source junction 4 near the current spreading layer 6, and a well region depth L1Is the depth L of the channel region2At least 3 times, preferably 3 to 15 times; distance d between adjacent channel regions1Not less than the distance d of adjacent well regions2Distance d of adjacent channel regions10.5-5 μm;
the gate oxide layer 8 is arranged on the JFET region 5 and has a partial overlapping region with the source junction 4;
a gate electrode 9 disposed on the gate oxide layer 8;
a source electrode 10 disposed on the source junction 4;
and the drain electrode 11 is arranged on one side of the substrate 1, which is far away from the drift layer 2.
The preparation process of the MOSFET device comprises the following steps:
(1) forming a drift layer 2 having a first conductivity type on a substrate 1 by means of epitaxial growth, ion implantation or tilted ion implantation;
(2) forming a plurality of well regions 3 with a second conductivity type, channel regions 7 with the second conductivity type and JFET regions 5 with the first conductivity type on the drift layer 2 by high-energy ion implantation or channel ion implantation, wherein the JFET regions 5 are formed between adjacent well regions 3, FIG. 11 is a schematic view of ion implantation curves of the JFET regions and the well regions, the implantation energy can be 900KeV, and the depth L of the well regions is ensured1Is the depth L of the channel region2At least 3 times higher; preferably 3 to 15 times;
(3) forming a first mask layer (e.g., silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) in the well region 3, etching the first mask layer by a dry or wet etching process to form a first opening to expose the well region 3, and implanting a dopant into the well region 3 through the first opening by ion implantation to form a first conductive region 41 having a first conductivity type, such as N-type, which may be phosphorus or nitrogen; etching the first mask layer near the first opening by a dry or wet etching process, forming a second mask layer (e.g., silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) in the well region 3, etching the second mask layer by the dry or wet etching process to form a second opening to expose the well region 3, and implanting a dopant, which may be aluminum, boron, or gallium, in the well region 3 by ion implantation through the second opening to form a second conductive region 42 having a second conductivity type, such as the second conductivity type being P-type, in the well region 3, thereby obtaining a source junction 4;
(4) etching the remaining second mask layer by a dry etching process or a wet etching process, and then sequentially annealing and cleaning the surface; then, a mask layer is formed and selective etching is performed to form a gate oxide layer 8, a gate electrode 9, a source electrode 10 and a drain electrode 11.
Example 5
The present embodiment provides a MOSFET device and a process for manufacturing the same, as shown in fig. 5, the MOSFET device includes:
substrate 1 of a first conductivity type, for example N-type, dopant of phosphorus or nitrogen, and dopant concentration greater than 5 × 1018cm-3(ii) a Specifically, the substrate 1 is made of silicon carbide;
a drift layer 2 disposed on the substrate 1 and having a first conductivity type, such as N-type, dopant selected from phosphorus and nitrogen, and doping concentration of 1 × 1014cm-3-5x1017cm-3；
A plurality of well regions 3 arranged on the drift layer 2 and spaced from each other by a distance d20.2-5 μm, and has a second conductivity type, for example, the second conductivity type is P-type, the dopant can be aluminum, boron, gallium, and the doping concentration is 1x1016cm-3-5x1017cm-3；
The current expansion layer 6 is arranged between the adjacent well regions 3 and the adjacent source electrode junctions 4, extends to the lower part of the adjacent well regions 3, and has the upper surface flush with the upper surfaces of the source electrode junctions 4; the current spreading layer has a first conductivity type, such as N-type, and the dopant is phosphorus or nitrogen with a doping concentration of 1 × 1016cm-3-5x1017cm-3(ii) a Wherein, partial area in the current spreading layer 6 constitutes JFET area 5, the JFET area 5 is positioned in partial area between adjacent well regions 3 in the current spreading layer 6 and extends to the upper edge of the current spreading layer 6 so as to form a super junction structure with the well regions 3, the charge balance of the well regions and the JFET area or the charge unbalance degree of the well regions and the JFET area is not more than 20%, JFThe doping concentration of the ET region is 1x1016cm-3-5x1017cm-3；
A source junction 4, arranged in or on the well region 3, comprising a first conductive region 41 and a second conductive region 42 in contact with each other; the first conductive region has a first conductivity type, such as N-type, the dopant is phosphorus or nitrogen, and the doping concentration is greater than 5 × 1018cm-3(ii) a The second conductive region has a second conductivity type, for example, the second conductivity type is P-type, the dopant can be Al, B, Ga, and the doping concentration is greater than 5x1018cm-3；
A channel region 7 disposed in the well region and on the side of the source junction 4 near the JFET region 5, specifically below the source junction 4 and on the side of the source junction 4 near the current spreading layer 6, and a well region depth L1Is the depth L of the channel region2At least 3 times, preferably 3 to 15 times; distance d between adjacent channel regions1Not less than the distance d of adjacent well regions2Distance d of adjacent channel regions10.5-5 μm;
the gate oxide layer 8 is arranged on the current expansion layer 6 and the JFET region 5, and has a partial overlapping region with the source junction 4;
a gate electrode 9 disposed on the gate oxide layer 8;
a source electrode 10 disposed on the source junction 4;
and the drain electrode 11 is arranged on one side of the substrate 1, which is far away from the drift layer 2.
The preparation process of the MOSFET device comprises the following steps:
(1) forming a drift layer 2 having a first conductivity type on a substrate 1 by means of epitaxial growth, ion implantation or tilted ion implantation;
(2) forming a current spreading layer 6 having a first conductivity type on the drift layer 2 by epitaxial growth, ion implantation or tilted ion implantation;
(3) forming a plurality of well regions 3 with a second conductivity type, channel regions 7 with the second conductivity type and JFET regions 5 with the first conductivity type on the current spreading layer 6 respectively by high-energy ion implantation or channel ion implantation5 formed between adjacent well regions 3, and fig. 11 is a schematic view of ion implantation curves of the JFET region and the well region, wherein the implantation energy can be 900KeV to ensure the depth L of the well region1Is the depth L of the channel region2At least 3 times higher; preferably 3 to 15 times;
(4) forming a first mask layer (e.g., silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) in the well region 3, etching the first mask layer by a dry or wet etching process to form a first opening to expose the well region 3, and implanting a dopant into the well region 3 through the first opening by ion implantation to form a first conductive region 41 having a first conductivity type, such as N-type, which may be phosphorus or nitrogen; etching the first mask layer near the first opening by a dry or wet etching process, forming a second mask layer (e.g., silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) in the well region 3, etching the second mask layer by the dry or wet etching process to form a second opening to expose the well region 3, and implanting a dopant, which may be aluminum, boron, or gallium, in the well region 3 by ion implantation through the second opening to form a second conductive region 42 having a second conductivity type, such as the second conductivity type being P-type, in the well region 3, thereby obtaining a source junction 4;
(5) etching the remaining second mask layer by a dry etching process or a wet etching process, and then sequentially annealing and cleaning the surface; then, a mask layer is formed and selective etching is performed to form a gate oxide layer 8, a gate electrode 9, a source electrode 10 and a drain electrode 11.
Example 6
The present embodiment provides a MOSFET device and a process for manufacturing the same, as shown in fig. 6, the MOSFET device includes:
substrate 1 of a first conductivity type, for example N-type, dopant of phosphorus or nitrogen, and dopant concentration greater than 5 × 1018cm-3(ii) a Specifically, the substrate 1 is made of silicon carbide;
a drift layer 2 disposed on the substrate 1 and having a first conductivity type, such as N-type, and a dopant selected from phosphorus and nitrogenImpurity concentration of 1x1014cm-3-5x1017cm-3；
A plurality of well regions 3 arranged on the drift layer 2 and spaced from each other by a distance d20.2-5 μm, and has a second conductivity type, for example, the second conductivity type is P-type, the dopant can be aluminum, boron, gallium, and the doping concentration is 1x1016cm-3-5x1017cm-3；
The current expansion layer 6 is arranged between the adjacent well regions 3 and the adjacent source electrode junctions 4, extends to the lower part of the adjacent well regions 3, and has the upper surface flush with the upper surfaces of the source electrode junctions 4; the current spreading layer has a first conductivity type, such as N-type, and the dopant is phosphorus or nitrogen with a doping concentration of 1 × 1016cm-3-5x1017cm-3(ii) a Wherein, partial area in the current spreading layer 6 forms a JFET area 5, the JFET area 5 is positioned in the partial area of the current spreading layer 6 close to the side edge of the well region 3 and extends to the upper edge of the current spreading layer 6 so as to form a super junction structure with the well region, the charge balance of the well region and the JFET area or the charge unbalance degree of the well region and the JFET area is not more than 20 percent, and the doping concentration of the JFET area is 1x1016cm-3-5x1017cm-3；
A source junction 4, arranged in or on the well region 3, comprising a first conductive region 41 and a second conductive region 42 in contact with each other; the first conductive region has a first conductivity type, such as N-type, the dopant is phosphorus or nitrogen, and the doping concentration is greater than 5 × 1018cm-3(ii) a The second conductive region has a second conductivity type, for example, the second conductivity type is P-type, the dopant can be Al, B, Ga, and the doping concentration is greater than 5x1018cm-3；
A channel region 7 disposed in the well region and on the side of the source junction 4 near the JFET region 5, specifically below the source junction 4 and on the side of the source junction 4 near the current spreading layer 6, and a well region depth L1Is the depth L of the channel region2At least 3 times, preferably 3 to 15 times; distance d of adjacent channel regions 71Not less than the distance d of adjacent well regions 32Adjacent to the channel region 7Distance d10.5-5 μm;
the gate oxide layer 8 is arranged on the current expansion layer 6 and the JFET region 5, and has a partial overlapping region with the source junction 4;
a gate electrode 9 disposed on the gate oxide layer 8;
a source electrode 10 disposed on the source junction 4;
and the drain electrode 11 is arranged on one side of the substrate 1, which is far away from the drift layer 2.
The preparation process of the MOSFET device comprises the following steps:
(1) forming a drift layer 2 having a first conductivity type on a substrate 1 by means of epitaxial growth, ion implantation or tilted ion implantation;
(2) forming a current spreading layer 6 having a first conductivity type on the drift layer 2 by epitaxial growth, ion implantation or tilted ion implantation;
(3) forming a plurality of well regions 3 with a second conductivity type, channel regions 7 with the second conductivity type and JFET regions 5 with the first conductivity type on the current spreading layer 6 by high-energy ion implantation or channel ion implantation, wherein the JFET regions 5 are formed between adjacent well regions 3, FIG. 11 is a schematic view of the ion implantation curves of the JFET regions and the well regions, the implantation energy can be 900KeV, and the depth L of the well regions is ensured1Is the depth L of the channel region2At least 3 times higher; preferably 3 to 15 times;
(4) forming a first mask layer (e.g., silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) in the well region 3, etching the first mask layer by a dry or wet etching process to form a first opening to expose the well region 3, and implanting a dopant into the well region 3 through the first opening by ion implantation to form a first conductive region 41 having a first conductivity type, such as N-type, which may be phosphorus or nitrogen; etching the first mask layer near the first opening by a dry or wet etching process, forming a second mask layer (e.g., silicon dioxide, or photoresist, or polysilicon layer, or nitride layer, such as silicon nitride) in the well region 3, etching the second mask layer by the dry or wet etching process to form a second opening to expose the well region 3, and implanting a dopant, which may be aluminum, boron, or gallium, in the well region 3 by ion implantation through the second opening to form a second conductive region 42 having a second conductivity type, such as the second conductivity type being P-type, in the well region 3, thereby obtaining a source junction 4;
(5) etching the remaining second mask layer by a dry etching process or a wet etching process, and then sequentially annealing and cleaning the surface; then, a mask layer is formed and selective etching is performed to form a gate oxide layer 8, a gate electrode 9, a source electrode 10 and a drain electrode 11.
Comparative example 1
As shown in fig. 7, the present comparative example provides a MOSFET device which is different from embodiment 1 in that the depth L of the well region1Depth of junction with the source L2Is less than 3, in particular to the depth L of the well region in this comparative example1Is the depth L of the source junction 22 times of the total weight of the powder.
Test example 1
The MOSFET devices provided in example 1 and comparative example 1 were simulated to compare the electric field intensity distribution in the longitudinal direction from the gate oxide layer to the substrate in the middle of the round cell, wherein the MOSFET device simulation conditions are shown in table 1 and the test results are shown in fig. 8. The simulation conditions are as follows: the drain voltage is 1200V; VGS 0V.
TABLE 1
Device with a metal layer Example 1 Comparative example 1
Round cell size (mum) 5 5
Channel length (μm) 0.35 0.35
Well region depth (mum) 6 0.7
Drift layer doping concentration (cm)-3) 2×1016 8×1015
Drift layer (mum) 3 9
Doping concentration (cm) of current spreading layer-3) 2×1016 2×1016
Current spreading layer (mum) 7 1
Doping concentration (cm) of JFET region-3) 2×1017 1×1017
In the MOSFET device provided in comparative example 1, the maximum electric field is about 2.3MV/cm at about 1.5 μm below the gate oxide layer, and the electric field is 2MV/cm below the gate oxide layer, whereas in the MOSFET device provided in example 1, the maximum electric field is about 4.5 μm and about 2MV/cm below the gate oxide layer, and the electric field is 1.6 MV/cm. below the gate oxide layer, i.e., deeper well regions are beneficial for reducing the surface electric field, and a lower gate oxide electric field not only reduces the DIB L (Drain Induced Barrier L descending) effect, but more importantly improves the htrb (high Temperature recovery bias) reliability of the MOSFET device, providing greater protection to the gate oxide layer.
Test example 2
The MOSFET devices provided in example 1 and comparative example 1 were subjected to an output characteristic test to compare the respective resistance compositions under a test condition of VGS which is a gate-level voltage at which the devices were completely turned on.
The results of the test at room temperature (25 ℃) are shown in FIG. 9, and the results of the test at 150 ℃ are shown in FIG. 10. The result shows that the resistance of a JFET area and the resistance of a drift area of the super junction/silicon carbide MOSFET device are obviously reduced, namely the temperature coefficient of resistance of the device is obviously improved; the total specific resistance of the super junction/silicon carbide MOSFET device at room temperature is 57% of the conventional device shown in comparative example 1, the reduction is 42% at 150 ℃, and the active area of the super junction device chip can be reduced by more than 50% due to the significant reduction in the drift region resistance.
In addition, according to the above description, the P-type MOSFET device and the n-type MOSFET device can be switched with each other, and both the P-type MOSFET device and the n-type MOSFET device are within the protection scope of the present invention.
Although the foregoing embodiments have been described with reference to specific figures, it should be understood that some embodiments of the invention may include additional and/or intervening layers, structures, or elements, and/or may be deleted or omitted. Although a few exemplary embodiments of this invention have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of this invention. Accordingly, all such modifications are intended to be included within the scope of this invention as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of the present invention and that the invention is not to be considered limited to the specific embodiments disclosed and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. The invention is defined by the following claims, with equivalents of the claims to be included therein.

Claims (10)

1. A MOSFET device, comprising:
a drift layer having a first conductivity type;
the plurality of well regions are arranged on the drift layer, have a second conduction type and are arranged adjacent to the well regions at intervals;
the JFET area is arranged between the adjacent well areas and has a first conduction type; and the number of the first and second groups,
a channel region of the second conductivity type disposed in or over the well region having a depth L1Is the depth L of the channel region2At least 3 times higher.
2. The MOSFET device of claim 1, wherein the well region and the JFET region are charge balanced or both are charge unbalanced by no more than 20%.
3. The MOSFET device of claim 2, wherein the well region has a doping concentration of 1x1016cm-3-5x1017cm-3The doping concentration of the JFET region is 1x1016cm-3-5x1017cm-3。
4. MOSFET device according to any of claims 1-3, characterized in that the distance d between adjacent channel regions1Not less than the distance d of adjacent well regions2。
5. The MOSFET device of claim 4, wherein the distance d between adjacent channel regions10.5-5 μm, the distance d between adjacent well regions2Is 0.2-5 μm.
6. The MOSFET device of any one of claims 1-5, further comprising a current spreading layer disposed on the drift layer, wherein the JFET region is part of the current spreading layer.
7. The MOSFET device of claim 6, wherein the current spreading layer has a doping concentration of 1x1016cm-3-5x1017cm-3。
8. The MOSFET device of any one of claims 1-7, further comprising,
a source junction disposed in or on the well region;
the gate oxide layer is arranged on the JFET area and has a partial overlapping area with the source junction;
the gate electrode is arranged on the gate oxide layer;
the source electrode is arranged on the source electrode junction;
the substrate is arranged on one side, away from the well region, of the drift layer, and the drain electrode is arranged on one side, away from the drift layer, of the substrate.
9. The MOSFET device of claim 8, wherein the substrate is silicon carbide.
10. A preparation process of a MOSFET device comprises the following steps:
forming a drift layer having a first conductivity type;
forming a plurality of well regions having a second conductivity type and JFET regions having a first conductivity type on the drift layer, the JFET regions being formed between adjacent well regions;
forming a channel region of the second conductivity type in or over the well region to a depth L of the well region1Is the depth L of the channel region2At least 3 times higher.
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