CN113838757B - Forming method of single event effect resistant VDMOS device and VDMOS device - Google Patents
Forming method of single event effect resistant VDMOS device and VDMOS device Download PDFInfo
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
The invention provides a method for forming a VDMOS device resistant to a single event effect and the VDMOS device, comprising the following steps: providing a substrate with a first doping type; extending and growing an epitaxial layer with the first doping type outwards on one surface of the substrate; forming a body region with a second doping type, a body contact region and a source region with the first doping type on one side of the epitaxial layer away from the substrate; etching on the epitaxial layer in a direction perpendicular to the contact surface of the substrate and the epitaxial layer to form a groove region, wherein the groove region passes through the body region and the body contact region; filling the groove region through the polysilicon with the second doping type to form a first filling region, wherein the first filling region is not electrically connected with the body region and the body contact region, and the residual region of the groove region is filled through an insulating medium; the invention can greatly improve the single particle burning resistance and single particle gate penetration resistance of the VDMOS device.
Description
Technical Field
The invention relates to the field of semiconductor radiation-resistant reinforcement, in particular to a method for forming a single event effect-resistant VDMOS device and the VDMOS device.
Background
After charged particles such as heavy ions, protons and the like in the space environment are incident on a semiconductor device in the spacecraft electronic system, energy is lost through an ionization process, and a large number of electron hole pairs are generated along a radial track. Under the action of an electric field in the device, the excessive carriers are collected by the sensitive nodes, and a single event effect (Single Event Effect, SEE) can be induced, so that interference is generated on the working state of the aerospace electronic system, and the function failure can be caused when the interference is serious. The power VDMOS device has the advantages of high input impedance, strong driving capability, wide safe working area, simple control circuit and the like, and is widely applied to a DC/DC converter of an aerospace vehicle power supply system. However, the effect of the conventional VDMOS device against the single event effect is not good, and how to effectively suppress the single event effect becomes a major problem to be solved in the current VDMOS device.
Disclosure of Invention
In view of the problems in the prior art, the invention provides a method for forming a single event effect resistant VDMOS device and the VDMOS device, which mainly solve the problems of single event burnout resistance and poor single event gate penetration resistance of the traditional VDMOS device.
In order to achieve the above and other objects, the present invention adopts the following technical scheme.
A forming method of a single event effect resistant VDMOS device comprises the following steps:
providing a substrate with a first doping type;
extending and growing an epitaxial layer with the first doping type outwards on one surface of the substrate;
forming a body region with a second doping type, a body contact region and a source region with the first doping type on one side of the epitaxial layer away from the substrate;
etching on the epitaxial layer in a direction perpendicular to the contact surface of the substrate and the epitaxial layer to form a groove region, wherein the groove region passes through the body region and the body contact region;
and filling the groove region through the polysilicon with the second doping type to form a first filling region, wherein the first filling region is not electrically connected with the body region and the body contact region, and the residual region of the groove region is filled through an insulating medium.
Optionally, forming a body region with a second doping type, a body contact region and a source region with the first doping type on a side of the epitaxial layer facing away from the substrate, including:
forming doped regions comprising the body region and the body contact region on two opposite sides of the epitaxial layer respectively;
and forming the source region on the basis of the body region on the corresponding side of the epitaxial layer.
Optionally, generating a gate oxide layer on the basis of the source region, the body region and the epitaxial layer;
generating a polysilicon gate on the basis of the gate oxide layer;
generating an insulating medium layer on the basis of the groove region, the body contact region, the source region and the polysilicon gate;
etching to form a window exposing the source region, the body contact region and the groove region on the basis of the insulating medium layer, and growing a metal contact layer as a source electrode on the basis of the window;
and growing a metal layer on the side of the substrate away from the epitaxial layer to serve as a drain electrode.
Optionally, the epitaxial layer comprises multiple layers of doped regions with different doping concentrations sequentially from the substrate upwards.
Optionally, the first doping type is N-type doping, and the second doping type is P-type doping; or, the first doping type is P-type doping, and the second doping type is N-type doping.
Optionally, the body region is located below and connected to the body contact region of the corresponding side, and the source region is connected to the body region and the body contact region of the corresponding side, respectively.
Optionally, the first filling region is located below the body region.
Optionally, the body region and the body contact region are formed by selective doping and annealing.
Optionally, the insulating dielectric layer includes silicon oxide or silicon nitride.
A single event effect resistant VDMOS device comprising:
a substrate having a first doping type;
an epitaxial layer having the first doping type on one of the faces of the substrate;
a body region with a second doping type, a body contact region and a source region with the first doping type, which are positioned on one side of the epitaxial layer away from the substrate;
a groove region which is positioned on the epitaxial layer and is perpendicular to the contact surface direction of the substrate and the epitaxial layer, wherein the groove region passes through the body region and the body contact region;
the first filling region is positioned in the groove region and is provided with the second doping type, and the first filling region is not electrically connected with the body region and the body contact region;
and the insulating medium filling region is positioned in the groove region and used for completely filling the groove region in cooperation with the first filling region.
As described above, the method for forming the anti-single event effect VDMOS device and the VDMOS device provided by the present invention have the following beneficial effects.
And by utilizing the doping type of the first filling region in the groove region to be different from the doping type of the epitaxial layer, a PN junction is formed between the first filling region and the epitaxial layer, so that the single particle burning and the single particle gate penetration effect can be effectively inhibited.
Drawings
Fig. 1 is a schematic diagram of an N-type epitaxial layer formed on an N-type substrate according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of forming P-type body regions and P-type body contact regions by selective doping and annealing in accordance with an embodiment of the present invention.
FIG. 3 is a schematic diagram of a selective etching process for forming a trench region according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of filling a trench region with P-type polysilicon according to an embodiment of the present invention.
Fig. 5 is a schematic illustration of depositing oxide to fill the trench regions and planarizing the surface in an embodiment of the invention.
Fig. 6 is a schematic diagram of forming a gate oxide layer, a polysilicon gate, a source region and an insulating dielectric layer in an embodiment of the invention.
FIG. 7 is a schematic diagram of a single event effect N-channel VDMOS device after electrode contact is formed in accordance with an embodiment of the invention;
fig. 8 is a graph of the change in VDMOS drain current over time after vertical incidence of heavy ions having different LCD values from the channel region in an embodiment of the present invention.
Fig. 9 is a graph showing the change in electric field intensity inside the VDMOS gate oxide after the heavy ions of lcd=1pc/μm are vertically incident for 50ps from the center of the neck region in an embodiment of the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
The inventor researches find that: because the source region, the body region and the epitaxial layer of the VDMOS form a parasitic bipolar transistor structure, after high-energy charged particles are incident into the device, a large number of electron hole pairs are generated along the radial trace, and under the action of a drain-source electric field, a large number of excessive carriers flow to the source electrode through the body region, so that a certain voltage drop is generated in the body region. When the voltage drop of the body region is larger than the on voltage of the EB junction of the parasitic bipolar transistor, the transistor enters a forward amplification state, and carriers of the source region are continuously injected into the body region and swept towards the drift region. If the source-drain voltage of the VDMOS is greater than the BVCEO of the parasitic bipolar transistor, the current through the transistor will increase further under the action of the forward feedback mechanism. Local spots in the VDMOS device cause a sharp rise in lattice temperature due to current concentration effects, resulting in a single event burn out (Sing Event Burnout, SEB) effect. In addition, when heavy ions are incident from the VDMOS neck region, a large number of carriers generated in the drift region are accumulated toward the gate oxide/silicon interface by the drain-source electric field, thereby generating an additional electric field in the gate oxide. When the electric field intensity in the gate oxide layer is higher than the intrinsic breakdown field intensity, the gate oxide layer is locally broken down, so that a single-particle gate penetrating (Single Event Gate Rapture, SEGR) effect is induced, the gate leakage current is increased, and even the gate control capability is lost. Single event burn-out and single event gate penetration are the most important two types of single event effects in VDMOS devices. Unlike the recoverable single event effects of single event transients (Single Event Transient, SET), single event upset (Single Event Upset, SEU), etc., both can cause irreversible material damage inside the device, so that VDMOS devices for aerospace applications must take anti-single event burn-out and single event gate penetration reinforcement measures.
Referring to fig. 1, the present invention provides a method for forming a single event effect resistant VDMOS device, comprising the following steps: providing a substrate with a first doping type; extending and growing an epitaxial layer with the first doping type outwards on one surface of the substrate; forming a body region with a second doping type, a body contact region and a source region with the first doping type on one side of the epitaxial layer away from the substrate; etching on the epitaxial layer in a direction perpendicular to the contact surface of the substrate and the epitaxial layer to form a groove region, wherein the groove region passes through the body region and the body contact region; and filling the groove region through the polysilicon with the second doping type to form a first filling region, wherein the first filling region is not electrically connected with the body region and the body contact region, and the residual region of the groove region is filled through an insulating medium.
In one embodiment, doped regions including the body region and the body contact region are formed on opposite sides of the epitaxial layer; and forming the source region on the basis of the body region on the corresponding side of the epitaxial layer.
In an embodiment, further, a gate oxide layer may be generated on the basis of the source region, the body region and the epitaxial layer; generating a polysilicon gate on the basis of the gate oxide layer; generating an insulating medium layer on the basis of the groove region, the body contact region, the source region and the polysilicon gate; etching to form a window exposing the source region, the body contact region and the groove region on the basis of the insulating medium layer, and growing a metal contact layer as a source electrode on the basis of the window; and growing a metal layer on the side of the substrate away from the epitaxial layer to serve as a drain electrode.
In an embodiment, the epitaxial layer comprises multiple layers of doped regions with different doping concentrations in sequence from the substrate upwards. Specifically, on the premise of ensuring that the breakdown voltage of the VDMOS does not obviously deteriorate, the doping concentration of a part of doping regions can be increased, or the doping concentration of all the doping regions can be increased, so that the on-resistance of the VDMOS device is reduced, and the service life of unbalanced carriers in a semiconductor is inversely proportional to the concentration of majority carriers according to the carrier recombination theory. Therefore, after the high-energy charged particles are incident to the VDMOS, the excessive carriers generated along the radial trace are quickly compounded, so that the number of the excessive carriers flowing to the body region and the neck region is reduced, and finally, the single particle burning and the single particle gate penetration effect are inhibited.
In an embodiment, the body region is located below and connected to the body contact region of the corresponding side, and the source region is connected to the body region and the body contact region of the corresponding side, respectively.
In an embodiment, the first doping type is N-type doping and the second doping type is P-type doping; or, the first doping type is P-type doping, and the second doping type is N-type doping.
In one embodiment, the insulating dielectric layer comprises silicon oxide or silicon nitride.
The following takes the forming method of the N-channel VDMOS device as an example, and the specific implementation flow is as follows:
step one, referring to FIG. 1, an N-type epitaxial layer 2 with a thickness of 18 μm is grown on a heavily doped N-type silicon substrate 1 (resistivity 0.002 Ω & cm), the doping concentration of the epitaxial layer 2 being sequentially 2×10 in different thickness regions from the surface of the silicon substrate 1 16 cm -3 (0μm-6.5μm)、5×10 15 cm -3 (6.5μm-8μm)、1×10 15 cm -3 (8μm-9μm)，7.4×10 14 cm -3 (9μm-18μm)；
Step two, referring to fig. 2, forming a P-type body region 3 and a P-type body contact region 4 by selective boron ion implantation and annealing;
step three, referring to fig. 3, selectively etching the device structure obtained in the step two to form a trench region 5 penetrating through the P-type body region 3 and the P-type body contact region 4 to the N-type epitaxial layer, wherein the depth of the trench is 11 μm and the width of the trench is 3 μm;
fourth, referring to fig. 4, the trench region 5 is filled with P-type polysilicon with a filling depth of 6 μm and a doping concentration of 1×10 16 cm -3 Forming a first filling region 6;
step five, referring to fig. 5, the filling of the remaining part of the trench may be completed by using an insulating medium such as a deposited oxide, to form an insulating medium filling region 7, and flattening the surface of the device by chemical mechanical planarization;
step six, referring to fig. 6, a gate oxide layer 8, a polysilicon gate 9, an N-type source region 10 and an oxide insulating dielectric layer 11 are formed by a conventional VDMOS manufacturing process;
step seven, referring to fig. 7, a source metal contact window is formed by selectively etching the oxide insulating dielectric layer 11, a source metal contact 12 is formed by a metallization process, and a drain metal contact 13 is formed by a metallization process on the side surface of the substrate 1 facing away from the epitaxial layer, so as to prepare an N-channel VDMOS structure with a polysilicon trench filling region.
Fig. 8 shows the drain current variation with time after vertical incidence of heavy ions from the channel region for different linear energy depositions (Linear Charge Deposition, LCD) for a reinforced VDMOS device and an unreinforced conventional VDMOS device using the above-described anti-single event effect device structure and fabrication method. It can be seen that for the unreinforced VDMOS device, the heavy ions with the LCD of 0.3pC/μm can induce single particle burning, while the reinforced VDMOS device still has no burning after the heavy ions with the LCD of 1pC/μm are incident. In conclusion, the reinforcement structure and the preparation method can remarkably improve the single particle burnout threshold of the VDMOS.
Fig. 9 shows the electric field strength contrast inside the gate oxide layer after the heavy ions of lcd=1pc/μm are vertically incident for 50ps from the center of the neck region for the reinforced VDMOS device and the unreinforced conventional VDMOS device using the above-described anti-single event effect device structure and manufacturing method. As can be seen from the figure, the electric field intensity inside the reinforced VDMOS gate oxide is significantly lower than that of the unreinforced device, thus suppressing the local breakdown of the oxide. In conclusion, the reinforcement structure and the preparation method can remarkably improve the single-particle gate penetration resistance of the VDMOS.
In an embodiment, the present invention further provides a single event effect resistant VDMOS device, which is characterized by comprising: a substrate having a first doping type; an epitaxial layer having the first doping type on one of the faces of the substrate; a body region with a second doping type, a body contact region and a source region with the first doping type, which are positioned on one side of the epitaxial layer away from the substrate; a groove region which is positioned on the epitaxial layer and is perpendicular to the contact surface direction of the substrate and the epitaxial layer, wherein the groove region passes through the body region and the body contact region; the first filling region is positioned below the body region and is not electrically connected with the body region and the body contact region; and the insulating medium filling region is positioned in the groove region and used for completely filling the groove region in cooperation with the first filling region.
In an embodiment, the first fill region is not connected to the body region and the body contact region. The body region is positioned below the body contact region and connected with the body contact region; the source region is located between the body region and the body contact region and is connected to the body region and the body contact region, respectively. A gate oxide layer is arranged on the basis of the source region, the body region and the epitaxial layer, a polysilicon gate is arranged on the gate oxide layer, and the gate oxide layer and the polysilicon gate are covered by an insulating medium layer; the insulating medium layer is provided with a window in the source region, and a metal contact layer is arranged at the window position and connected with the source region to serve as a source electrode; a metal contact layer is provided as a drain electrode on the side of the substrate facing away from the epitaxial layer.
In summary, the invention provides a method for forming a single event effect resistant VDMOS device and a VDMOS device, wherein a PN junction is formed between a polysilicon trench filling region of a second impurity doping type and a silicon epitaxial layer of a first impurity doping type. When voltage is applied between the drain and the source to reversely bias the PN junction, the polycrystalline silicon groove filling region obtains potential from the reversely biased PN junction, so that depletion of the first impurity doping type silicon epitaxial layer is facilitated, and the drift region can bear larger applied voltage. Thus, the doping concentration of the first impurity doping type silicon epitaxial layer can be increased or partially increased, while ensuring that no significant degradation of the VDMOS breakdown voltage occurs. According to carrier recombination theory, the unbalanced carrier lifetime in a semiconductor is inversely proportional to the majority carrier concentration. Therefore, after the high-energy charged particles are incident to the VDMOS, the excessive carriers generated along the radial trace are rapidly compounded, so that the number of the excessive carriers flowing to the body region and the neck region is reduced, and finally, the single particle burnout and the single particle gate penetration effect are inhibited; the process steps of filling the polysilicon trench are carried out after epitaxial growth and high-temperature promotion of the body region, so that the external diffusion of impurities in the polysilicon is weakened, and the reinforcement effect can be realized under the condition of not changing the whole flow thermal budget; the on-resistance of the VDMOS is reduced while the doping concentration of the epitaxial layer is increased; the polysilicon trench filling area is far away from the current transmission path of the VDMOS, the cell pitch is not increased, and the phenomenon of electric field concentration at the edge of the body area is avoided. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (6)
1. The method for forming the single event effect resistant VDMOS device is characterized by comprising the following steps:
providing a substrate with a first doping type;
facing on one of the faces of the substrateEpitaxial layer with the first doping type is grown by epitaxial extension, the epitaxial layer sequentially comprises a plurality of layers of doping areas with different doping concentrations from the substrate upwards, and the growth thickness of the epitaxial layer is 18 mu m; the doping concentration of the doped regions from the surface of the substrate to different layers is 2×10 in turn 16 cm -3 （0 μm-6.5 μm）、5×10 15 cm -3 （6.5 μm-8 μm）、1×10 15 cm -3 （8 μm-9 μm），7.4×10 14 cm -3 （9 μm-18 μm）；
Forming a body region with a second doping type, a body contact region and a source region with the first doping type on one side of the epitaxial layer away from the substrate, wherein the method comprises the following steps: forming doped regions comprising the body region and the body contact region on two opposite sides of the epitaxial layer respectively; forming the source region on the basis of the body region on the corresponding side of the epitaxial layer;
etching on the epitaxial layer in a direction perpendicular to the contact surface of the substrate and the epitaxial layer to form a groove region, wherein the groove region passes through the body region and the body contact region; wherein the body contact region and the body region are formed by selective boron ion implantation and annealing; the depth of the groove region is 11 mu m, and the width of the groove region is 3 mu m;
filling the trench region with polysilicon having the second doping type to form a first filling region with a depth of 6 μm and a doping concentration of 1×10 16 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the The first filling region is not electrically connected with the body region and the body contact region, the residual region of the trench region is filled with an insulating medium, and the first filling region is positioned below the body region; generating a gate oxide layer on the basis of the source region, the body region and the epitaxial layer; generating a polysilicon gate on the basis of the gate oxide layer; generating an insulating medium layer on the basis of the groove region, the body contact region, the source region and the polysilicon gate; etching to form a window exposing the source region, the body contact region and the groove region on the basis of the insulating medium layer, and growing a metal contact layer as a source electrode on the basis of the window; at the substrate facing away from the outer partAnd growing a metal layer on one side of the extension layer to serve as a drain electrode.
2. The method of forming a single event effect resistant VDMOS device of claim 1 wherein the first doping type is N-type doping and the second doping type is P-type doping; or, the first doping type is P-type doping, and the second doping type is N-type doping.
3. The method of claim 1, wherein the body region is located below and connected to the body contact region on the corresponding side, and the source region is connected to the body region and the body contact region on the corresponding side, respectively.
4. The method of claim 1, wherein the body region and the body contact region are formed by selective doping and annealing.
5. The method of claim 1, wherein the insulating medium comprises silicon oxide or silicon nitride.
6. A single event effect resistant VDMOS device obtainable by the method of forming as claimed in any one of claims 1 to 5, comprising:
a substrate having a first doping type;
an epitaxial layer with the first doping type is positioned on one surface of the substrate, and the epitaxial layer sequentially comprises a plurality of layers of doping areas with different doping concentrations from the substrate upwards;
a body region with a second doping type, a body contact region and a source region with the first doping type, which are positioned on one side of the epitaxial layer away from the substrate;
a groove region which is positioned on the epitaxial layer and is perpendicular to the contact surface direction of the substrate and the epitaxial layer, wherein the groove region passes through the body region and the body contact region;
the first filling region is positioned in the groove region and is provided with the second doping type, and the first filling region is not electrically connected with the body region and the body contact region;
and the insulating medium filling region is positioned in the groove region and used for completely filling the groove region in cooperation with the first filling region.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US6084264A (en) * | 1998-11-25 | 2000-07-04 | Siliconix Incorporated | Trench MOSFET having improved breakdown and on-resistance characteristics |
| CN107331707A (en) * | 2017-06-29 | 2017-11-07 | 电子科技大学 | VDMOS device with anti-single particle effect |
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| JP5530602B2 (en) * | 2008-04-09 | 2014-06-25 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| US10062749B2 (en) * | 2013-06-18 | 2018-08-28 | Monolith Semiconductor Inc. | High voltage semiconductor devices and methods of making the devices |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6084264A (en) * | 1998-11-25 | 2000-07-04 | Siliconix Incorporated | Trench MOSFET having improved breakdown and on-resistance characteristics |
| CN107331707A (en) * | 2017-06-29 | 2017-11-07 | 电子科技大学 | VDMOS device with anti-single particle effect |
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