CN113838757A - Forming method of single event effect resistant VDMOS device and VDMOS device - Google Patents
Forming method of single event effect resistant VDMOS device and VDMOS device Download PDFInfo
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- 239000002184 metal Substances 0.000 claims description 11
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- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
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- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000002245 particle Substances 0.000 abstract description 18
- 230000035515 penetration Effects 0.000 abstract description 7
- 239000000969 carrier Substances 0.000 description 9
- 230000005684 electric field Effects 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 5
- 239000012535 impurity Substances 0.000 description 5
- 230000009471 action Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
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- 238000001465 metallisation Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 230000003014 reinforcing effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000008713 feedback mechanism Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000000752 ionisation method Methods 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
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- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000005510 radiation hardening Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
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Abstract
The invention provides a forming method of a single event effect resistant VDMOS device and the VDMOS device, comprising the following steps: providing a substrate having a first doping type; growing an epitaxial layer with the first doping type on one face of the substrate in an extending mode; forming a body region with a second doping type, a body contact region and a source region with the first doping type on one side of the epitaxial layer, which is far away from the substrate; etching a groove region on the epitaxial layer in a direction perpendicular to the contact surface direction of the substrate and the epitaxial layer, wherein the groove region penetrates through the body region and the body contact region; filling the groove region by using the polysilicon with the second doping type to form a first filling region, wherein the first filling region is not electrically connected with the body region and the body contact region, and filling the rest region of the groove region by using an insulating medium; the invention can greatly improve the single-particle burnout resistance and single-particle gate penetration resistance of the VDMOS device.
Description
Technical Field
The invention relates to the field of semiconductor radiation hardening, in particular to a forming method of a single event effect resisting VDMOS device and the VDMOS device.
Background
After charged particles such as heavy ions, protons and the like in a space environment are incident to a semiconductor device in an electronic system of a spacecraft, energy is lost through an ionization process, and a large number of electron-hole pairs are generated along a track. Under the action of an electric field in the device, the excess carriers are collected by the sensitive nodes, and a Single Event Effect (SEE) can be induced, so that the working state of an aerospace electronic system is interfered, and functional failure can be caused in serious cases. The power VDMOS device has the advantages of high input impedance, strong driving capability, wide safe working area, simple control circuit and the like, and is widely applied to a DC/DC converter of an aircraft power supply system. However, the conventional VDMOS device has a poor single event effect resistance effect, and how to effectively suppress the single event effect becomes a big problem to be solved urgently in the current VDMOS device.
Disclosure of Invention
In view of the problems in the prior art, the invention provides a forming method of a single event effect resistant VDMOS device and the VDMOS device, and mainly solves the problems that the traditional VDMOS device is poor in single event burnout resistance and single event gate penetration resistance.
In order to achieve the above and other objects, the present invention adopts the following technical solutions.
A method for forming a single event effect resistant VDMOS device comprises the following steps:
providing a substrate having a first doping type;
growing an epitaxial layer with the first doping type on one face of the substrate in an extending mode;
forming a body region with a second doping type, a body contact region and a source region with the first doping type on one side of the epitaxial layer, which is far away from the substrate;
etching a groove region on the epitaxial layer in a direction perpendicular to the contact surface direction of the substrate and the epitaxial layer, wherein the groove region penetrates through the body region and the body contact region;
and filling the groove region by using the polysilicon with the second doping type to form a first filling region, wherein the first filling region is not electrically connected with the body region and the body contact region, and the rest region of the groove region is filled by using an insulating medium.
Optionally, forming a body region having a second doping type, a body contact region, and a source region having the first doping type on a side of the epitaxial layer facing away from the substrate includes:
forming doped regions comprising the body region and the body contact region on two opposite sides of the epitaxial layer respectively;
and forming the source region on the basis of the body region on the corresponding side of the epitaxial layer.
Optionally, a gate oxide layer is generated on the basis of the source region, the body region and the epitaxial layer;
generating a polysilicon gate on the basis of the gate oxide layer;
generating an insulating dielectric layer on the basis of the groove region, the body contact region, the source region and the polysilicon gate;
etching to form a window exposing the source region, the body contact region and the trench region on the basis of the insulating medium layer, and growing a metal contact layer on the basis of the window to serve as a source electrode;
and growing a metal layer on one side of the substrate, which is far away from the epitaxial layer, to serve as a drain electrode.
Optionally, the epitaxial layer comprises multiple doped regions with different doping concentrations in sequence from the substrate upwards.
Optionally, the first doping type is N-type doping, and the second doping type is P-type doping; or, the first doping type is P-type doping, and the second doping type is N-type doping.
Optionally, the body region is located below and connected to the body contact region on the corresponding side, and the source region is connected to the body region and the body contact region on the corresponding side, respectively.
Optionally, the first fill region is located below the body region.
Optionally, the body region and the body contact region are formed by selective doping and annealing.
Optionally, the insulating dielectric layer includes silicon oxide or silicon nitride.
A single event effect resistant VDMOS device comprising:
a substrate having a first doping type;
an epitaxial layer having the first doping type on one of the faces of the substrate;
the epitaxial layer is positioned on one side, away from the substrate, of the epitaxial layer and comprises a body region with a second doping type, a body contact region and a source region with the first doping type;
the groove region is positioned on the epitaxial layer and is vertical to the direction of the contact surface of the substrate and the epitaxial layer, and the groove region penetrates through the body region and the body contact region;
a first filling region of the second doping type located in the trench region, the first filling region not being electrically connected to the body region and the body contact region;
and the insulating medium filling area is positioned in the groove area and is used for being matched with the first filling area to completely fill the groove area.
As described above, the invention provides a method for forming a VDMOS device with resistance to single event effect and a VDMOS device, which have the following advantages.
The PN junction is formed between the first filling region and the epitaxial layer by utilizing the difference between the doping type of the first filling region in the groove region and the doping type of the epitaxial layer, so that the single-particle burnout and the single-particle gate-through effect can be effectively inhibited.
Drawings
Fig. 1 is a schematic diagram of an N-type epitaxial layer formed on an N-type substrate according to an embodiment of the invention.
FIG. 2 is a schematic diagram of the formation of a P-type body region and a P-type body contact region by selective doping and annealing in accordance with an embodiment of the present invention.
FIG. 3 is a schematic diagram of a trench region formed by selective etching according to an embodiment of the invention.
Fig. 4 is a schematic diagram illustrating filling of the trench region with P-type polysilicon according to an embodiment of the present invention.
FIG. 5 is a schematic view of an embodiment of depositing an oxide to fill the trench region and planarize the surface.
Fig. 6 is a schematic diagram of forming a gate oxide layer, a polysilicon gate, a source region and an insulating dielectric layer according to an embodiment of the invention.
FIG. 7 is a schematic structural diagram of an anti-single event effect N-channel VDMOS device after electrode contact is formed according to an embodiment of the invention;
FIG. 8 is a graph of VDMOS drain current versus time after vertical incidence from the channel region of heavy ions with different LCD values in an embodiment of the present invention.
Fig. 9 is a graph showing the variation of the electric field intensity inside the VDMOS gate oxide layer after the heavy ions of LCD 1pC/μm are vertically incident from the central position of the neck region for 50ps in accordance with an embodiment of the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The inventor researches and discovers that: because the source region, the body region and the epitaxial layer of the VDMOS form a parasitic bipolar transistor structure, after high-energy charged particles enter the device, a large number of electron-hole pairs are generated along the path, and a large number of surplus carriers flow to the source electrode through the body region under the action of a drain-source electric field, so that a certain voltage drop is generated in the body region. When the voltage drop of the body region is larger than the conduction voltage of the parasitic bipolar transistor EB junction, the transistor enters a forward amplification state, and the current carriers of the source region are continuously injected into the body region and are swept to the drift region. If the source-drain voltage of the VDMOS is greater than the BVCEO of the parasitic bipolar transistor, the current flowing through the transistor will further increase under the action of the forward feedback mechanism. Due to the current concentration effect, the temperature of the crystal lattice of a local point in the VDMOS device is sharply increased, so that the Single Event Burnout (SEB) effect is caused. In addition, when heavy ions are incident from the VDMOS neck region, under the action of the drain-source electric field, a large number of carriers generated in the drift region are accumulated toward the gate oxide/silicon interface, thereby generating an additional electric field in the gate oxide. When the electric field intensity in the Gate oxide layer is higher than the intrinsic breakdown field intensity of the Gate oxide layer, the Gate oxide layer is locally broken down, so that a Single Event Gate Rate (SEGR) effect is induced, and the Gate leakage current is increased, even the Gate control capability is lost. The single-particle burning and the single-particle gate penetration are two most important single-particle effects in the VDMOS device. Different from recoverable Single Event effects such as Single Event Transient (SET), Single Event Upset (SEU), and the like, both of them can cause irreversible material damage inside the device, so that the VDMOS device for aerospace application must adopt measures for preventing Single Event burnout and Single Event gate penetration.
Referring to fig. 1, the present invention provides a method for forming a VDMOS device with anti-single event effect, including the following steps: providing a substrate having a first doping type; growing an epitaxial layer with the first doping type on one face of the substrate in an extending mode; forming a body region with a second doping type, a body contact region and a source region with the first doping type on one side of the epitaxial layer, which is far away from the substrate; etching a groove region on the epitaxial layer in a direction perpendicular to the contact surface direction of the substrate and the epitaxial layer, wherein the groove region penetrates through the body region and the body contact region; and filling the groove region by using the polysilicon with the second doping type to form a first filling region, wherein the first filling region is not electrically connected with the body region and the body contact region, and the rest region of the groove region is filled by using an insulating medium.
In one embodiment, doped regions including the body region and the body contact region are formed on two opposite sides of the epitaxial layer respectively; and forming the source region on the basis of the body region on the corresponding side of the epitaxial layer.
In an embodiment, further, a gate oxide layer may be generated on the basis of the source region, the body region, and the epitaxial layer; generating a polysilicon gate on the basis of the gate oxide layer; generating an insulating dielectric layer on the basis of the groove region, the body contact region, the source region and the polysilicon gate; etching to form a window exposing the source region, the body contact region and the trench region on the basis of the insulating medium layer, and growing a metal contact layer on the basis of the window to serve as a source electrode; and growing a metal layer on one side of the substrate, which is far away from the epitaxial layer, to serve as a drain electrode.
In one embodiment, the epitaxial layer comprises multiple layers of doped regions with different doping concentrations in sequence from the substrate up. Specifically, on the premise of ensuring that the breakdown voltage of the VDMOS is not obviously degraded, the doping concentration of a part of doping regions can be increased, or the doping concentration of the whole doping regions can be increased, so that the on-resistance of the VDMOS device is reduced, and according to a carrier recombination theory, the service life of an unbalanced carrier in a semiconductor is in inverse proportion to the concentration of a majority carrier. Therefore, after the high-energy charged particles are incident to the VDMOS, the excess carriers generated along the path are quickly compounded, so that the number of the excess carriers flowing to the body region and the neck region is reduced, and the single-particle burnout and the single-particle gate penetration effect are finally inhibited.
In an embodiment, the body region is located below and connected to the body contact region on the corresponding side, and the source region is connected to the body region and the body contact region on the corresponding side, respectively.
In one embodiment, the first doping type is N-type doping, and the second doping type is P-type doping; or, the first doping type is P-type doping, and the second doping type is N-type doping.
In one embodiment, the insulating dielectric layer comprises silicon oxide or silicon nitride.
Taking the forming method of the N-channel VDMOS device as an example, the specific implementation flow is as follows:
step one, referring to fig. 1, an N-type epitaxial layer 2 with a thickness of 18 μm is grown on a heavily doped N-type silicon substrate 1 (with a resistivity of 0.002 Ω · cm), and the doping concentrations of the epitaxial layers 2 in different thickness intervals from the surface of the silicon substrate 1 are sequentially 2 × 1016cm-3(0μm-6.5μm)、5×1015cm-3(6.5μm-8μm)、1×1015cm-3(8μm-9μm)，7.4×1014cm-3(9μm-18μm)；
Step two, please refer to fig. 2, forming a P-type body region 3 and a P-type body contact region 4 by selective boron ion implantation and annealing;
step three, referring to fig. 3, selectively etching the device structure obtained in the step two to form a trench region 5 penetrating through the P-type body region 3 and the P-type body contact region 4 to the N-type epitaxial layer, wherein the depth of the trench is 11 micrometers, and the width of the trench is 3 micrometers;
step four, referring to fig. 4, the trench region 5 is filled with P-type polysilicon with a filling depth of 6 μm and a doping concentration of 1 × 1016cm-3Forming a first fill region 6;
step five, referring to fig. 5, the remaining part of the trench can be filled with an insulating medium such as deposited oxide to form an insulating medium filling region 7, and the surface of the device is planarized by chemical mechanical planarization;
step six, referring to fig. 6, forming a gate oxide layer 8, a polysilicon gate 9, an N-type source region 10 and an oxide insulating dielectric layer 11 by a conventional VDMOS manufacturing process;
step seven, referring to fig. 7, selectively etching the oxide insulating dielectric layer 11 to form a source metal contact window, forming a source metal contact 12 through a metallization process, and forming a drain metal contact 13 on the side of the substrate 1 away from the epitaxial layer through the metallization process, thereby preparing the N-channel VDMOS structure having the polysilicon trench filling region.
Fig. 8 shows the change of the drain current with time after the heavy ions vertically incident from the channel region of the reinforced VDMOS device and the unreinforced conventional VDMOS device with the above structure and the preparation method of the anti-single event effect device are deposited (LCD) at different Linear energies. As can be seen from the figure, for the non-reinforced VDMOS device, the single particle burnout can be induced by the heavy ions with the LCD of 0.3pC/μm, while the reinforced VDMOS device is not burnt out after the heavy ions with the LCD of 1pC/μm are incident. In conclusion, the reinforcing structure and the preparation method provided by the invention can obviously improve the single-particle burning threshold of the VDMOS.
Fig. 9 shows the comparison of the electric field intensity inside the gate oxide layer after the heavy ions with the LCD of 1pC/μm vertically enter 50ps from the central position of the neck region in the reinforced VDMOS device and the non-reinforced conventional VDMOS device adopting the structure and the manufacturing method of the anti-single event effect device. As can be seen from the figure, the electric field intensity inside the reinforced VDMOS gate oxide layer is obviously lower than that of an unreinforced device, so that the local breakdown of the oxide layer is inhibited. In conclusion, the reinforced structure and the preparation method provided by the invention can obviously improve the single-particle-resistant gate penetration capability of the VDMOS.
In an embodiment, the present invention further provides a single event effect resistant VDMOS device, including: a substrate having a first doping type; an epitaxial layer having the first doping type on one of the faces of the substrate; the epitaxial layer is positioned on one side, away from the substrate, of the epitaxial layer and comprises a body region with a second doping type, a body contact region and a source region with the first doping type; the groove region is positioned on the epitaxial layer and is vertical to the direction of the contact surface of the substrate and the epitaxial layer, and the groove region penetrates through the body region and the body contact region; a first filling region of the second doping type located in the trench region, wherein the first filling region is located below the body region and is not electrically connected with the body region and the body contact region; and the insulating medium filling area is positioned in the groove area and is used for being matched with the first filling area to completely fill the groove area.
In an embodiment, the first fill region is not connected to the body region and the body contact region. The body region is positioned below the body contact region and connected with the body contact region; the source region is located between the body region and the body contact region and is respectively connected with the body region and the body contact region. A gate oxide layer is arranged on the basis of the source region, the body region and the epitaxial layer, a polysilicon gate is arranged on the gate oxide layer, and the gate oxide layer and the polysilicon gate are covered by an insulating medium layer; the insulating medium layer is provided with a window in the source region, and a metal contact layer is arranged at the window position and connected with the source region to serve as a source electrode; and a metal contact layer is arranged on one side of the substrate, which is far away from the epitaxial layer, and is used as a drain electrode.
In summary, the invention provides a method for forming a single event effect resistant VDMOS device and a VDMOS device, wherein a PN junction is formed between the polysilicon trench filling region of the second impurity doping type and the silicon epitaxial layer of the first impurity doping type. When a voltage is applied between the drain and the source to enable the PN junction to be reversely biased, the polycrystalline silicon groove filling region obtains potential from the reversely biased PN junction, so that the depletion of the first impurity doping type silicon epitaxial layer is facilitated, and the drift region can bear larger applied voltage. Therefore, the doping concentration of the first impurity doping type silicon epitaxial layer can be increased or partially increased on the premise of ensuring that the breakdown voltage of the VDMOS does not undergo significant degradation. According to carrier recombination theory, the lifetime of non-equilibrium carriers within a semiconductor is inversely proportional to the majority carrier concentration. Therefore, after the high-energy charged particles are incident to the VDMOS, the excess carriers generated along the path are quickly compounded, so that the number of the excess carriers flowing to the body region and the neck region is reduced, and the single-particle burnout and the single-particle gate penetration effect are finally inhibited; the process steps of the polycrystalline silicon groove filling area are arranged after epitaxial growth and high-temperature body area propulsion, so that the external diffusion of impurities in polycrystalline silicon is weakened, and the reinforcing effect can be realized under the condition of not changing the thermal budget of the whole process; the doping concentration of the epitaxial layer is improved, and meanwhile, the on-resistance of the VDMOS is reduced; the polycrystalline silicon groove filling region is far away from a current transmission path of the VDMOS, the cell pitch is not increased, and the electric field concentration phenomenon at the edge of the body region is avoided. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A method for forming a VDMOS device resisting single event effect is characterized by comprising the following steps:
providing a substrate having a first doping type;
growing an epitaxial layer with the first doping type on one face of the substrate in an extending mode;
forming a body region with a second doping type, a body contact region and a source region with the first doping type on one side of the epitaxial layer, which is far away from the substrate;
etching a groove region on the epitaxial layer in a direction perpendicular to the contact surface direction of the substrate and the epitaxial layer, wherein the groove region penetrates through the body region and the body contact region;
and filling the groove region by using the polysilicon with the second doping type to form a first filling region, wherein the first filling region is not electrically connected with the body region and the body contact region, and the rest region of the groove region is filled by using an insulating medium.
2. The method for forming the single event effect resistant VDMOS device according to claim 1, wherein forming a body region having a second doping type, a body contact region and a source region having the first doping type on a side of the epitaxial layer facing away from the substrate comprises:
forming doped regions comprising the body region and the body contact region on two opposite sides of the epitaxial layer respectively; forming the source region on the basis of the body region on the corresponding side of the epitaxial layer; .
3. The method for forming the single event effect resistant VDMOS device according to claim 1, comprising:
generating a gate oxide layer on the basis of the source region, the body region and the epitaxial layer;
generating a polysilicon gate on the basis of the gate oxide layer;
generating an insulating dielectric layer on the basis of the groove region, the body contact region, the source region and the polysilicon gate;
etching to form a window exposing the source region, the body contact region and the trench region on the basis of the insulating medium layer, and growing a metal contact layer on the basis of the window to serve as a source electrode;
and growing a metal layer on one side of the substrate, which is far away from the epitaxial layer, to serve as a drain electrode.
4. The method for forming the single event effect resistant VDMOS device according to claim 1, wherein the epitaxial layer comprises a plurality of doped regions with different doping concentrations in sequence from the substrate upwards.
5. The method for forming the single event effect resistant VDMOS device according to claim 1, wherein the first doping type is N-type doping, and the second doping type is P-type doping; or, the first doping type is P-type doping, and the second doping type is N-type doping.
6. The method for forming a single event effect resistant VDMOS device according to claim 2, wherein the body region is under and connected to the body contact region on the corresponding side, and the source region is connected to the body region and the body contact region on the corresponding side respectively.
7. The method for forming the single event effect resistant VDMOS device according to claim 1 or 6, wherein the first filling region is located below the body region.
8. The method for forming a single event effect resistant VDMOS device of claim 1, wherein the body region and the body contact region are formed by selective doping and annealing.
9. The method for forming the single event effect resistant VDMOS device of claim 1, wherein the insulating dielectric layer comprises silicon oxide or silicon nitride.
10. A VDMOS device resisting single event effect, comprising:
a substrate having a first doping type;
an epitaxial layer having the first doping type on one of the faces of the substrate;
the epitaxial layer is positioned on one side, away from the substrate, of the epitaxial layer and comprises a body region with a second doping type, a body contact region and a source region with the first doping type;
the groove region is positioned on the epitaxial layer and is vertical to the direction of the contact surface of the substrate and the epitaxial layer, and the groove region penetrates through the body region and the body contact region;
a first filling region of the second doping type located in the trench region, the first filling region not being electrically connected to the body region and the body contact region;
and the insulating medium filling area is positioned in the groove area and is used for being matched with the first filling area to completely fill the groove area.
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| US6084264A (en) * | 1998-11-25 | 2000-07-04 | Siliconix Incorporated | Trench MOSFET having improved breakdown and on-resistance characteristics |
| US20090256197A1 (en) * | 2008-04-09 | 2009-10-15 | Yoshito Nakazawa | Semiconductor device and manufacturing method thereof |
| US20140367771A1 (en) * | 2013-06-18 | 2014-12-18 | Monolith Semiconductor, Inc. | High voltage semiconductor devices and methods of making the devices |
| CN107331707A (en) * | 2017-06-29 | 2017-11-07 | 电子科技大学 | VDMOS device with anti-single particle effect |
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2021
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6084264A (en) * | 1998-11-25 | 2000-07-04 | Siliconix Incorporated | Trench MOSFET having improved breakdown and on-resistance characteristics |
| US20090256197A1 (en) * | 2008-04-09 | 2009-10-15 | Yoshito Nakazawa | Semiconductor device and manufacturing method thereof |
| US20140367771A1 (en) * | 2013-06-18 | 2014-12-18 | Monolith Semiconductor, Inc. | High voltage semiconductor devices and methods of making the devices |
| CN107331707A (en) * | 2017-06-29 | 2017-11-07 | 电子科技大学 | VDMOS device with anti-single particle effect |
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