CN111354310A - 像素补偿电路 - Google Patents

像素补偿电路 Download PDF

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CN111354310A
CN111354310A CN201910870811.XA CN201910870811A CN111354310A CN 111354310 A CN111354310 A CN 111354310A CN 201910870811 A CN201910870811 A CN 201910870811A CN 111354310 A CN111354310 A CN 111354310A
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signal
transistor
control signal
pixel compensation
emission control
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郑士嵩
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Taizhou Guanyu Technology Co.,Ltd.
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INT Tech Co Ltd
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Abstract

一像素电路经配置以补偿与一主动矩阵有机发光二极体显示器或类似照明系统中薄膜晶体管的元件的电子特性相关的临界参数，以避免电压降效应导致的亮度不均匀。像素补偿电路界定于一子像素区域中，其中有七个薄膜晶体管与一个电容器，且所述电路系由两个控制信号而操作。相较之下，传统技术使用了三个控制信号。使用较少的控制信号有益于布局弹性与规格设计。

Description

像素补偿电路
技术领域
本发明是关于一种像素补偿电路，更明确地说，是关于用以改善一主动矩阵有机发光二极体(AMOLED)的亮度均匀性的像素补偿电路。
背景技术
近来显示器领域的焦点之一为主动矩阵有机发光二极体(active matrixorganic light emitting diode，AMOLED)显示器，因为其具有极佳的影像品质且光学规格优于传统显示器。
AMOLED显示器使用透过有机发光二极体的电流而作为发光装置，所述电流系由主动矩阵所控制，且灰阶的亮度是由发光过程中的电流量所决定。
主动矩阵系由一群像素单元所组成，且有效发光面积系由解析度所定义。有效发光区域为像素单元面积乘以垂直方向的解析度再乘以水平方向的解析度。
常见的像素单元是由三个子像素单元所组成。一般来说，一个子像素单元是由复数个薄膜晶体管与电容器所组成，一子像素面积的发光亮度的灰阶是由薄膜晶体管所控制，且电容器是作为一储存电位以稳定驱动电流。
然而，相较于其他显示器(譬如，液晶显示器)，由于主动矩阵有机发光二极体显示器的特性为电流驱动发光，灰阶的亮度差异会直接受到薄膜晶体管的元件的电子特性所影响。当不同子像素间的薄膜晶体管的元件电子特性差异过大时，会形成不均匀的影像特性。譬如，会出现云纹(mura)效应。
因此，为了克服上述问题，会使用像素补偿电路来补偿关键元件的电子特性参数(例如阈值电压Vth)，以便修复因不同元件间特性差异造成的影响品质低落。
除此之外，现有驱动系统中另一种常见的问题是电压降(IR-drop)效应，这是当系统的电子负载造成远端电压降所产生的。大量输出电流对应于大的电子负载，而使得通常经设计为共用电源的主动矩阵有机发光二极体(AMOLED)显示器中接近电源端的亮度高于远离电源端的亮度。可利用补偿电路来克服亮度均匀性的问题。
然而，随着显示器技术的进步，一个单元尺寸中有越来越多的像素，因此每一像素中的元件尺寸也相应地变小。传统像素补偿电路至少需要三个信号，因此需要至少三个信号产生器或线路，这使得尺寸的减小受到限制。
综上所述，传统技术有许多缺点亟待改进。有鉴于此，本发明提出一种像素补偿电路以改善AMOLED的亮度并可减少所需的控制信号数目。
发明内容
本发明是关于一种像素补偿电路，更明确地说，是关于用以改善一主动矩阵有机发光二极体(AMOLED)的亮度均匀性的像素补偿电路。
本发明的一实施例提出一种像素补偿电路。根据本揭示内容一实施方式，所述像素补偿电路包括一输入模块、一重置模块、一资料处理模块及一切换模块。输入模块接收一参考值及一资料信号，并回应一发光控制信号及一扫描信号而产生一第一信号。重置模块接收参考值并回应一子发光控制信号及扫描信号而产生一重置信号。资料处理模块接收第一信号、重置信号及一第一电压，并回应扫描信号而产生一第二信号。切换模块接收第二信号并回应发光控制信号而产生一发光信号。
输入模块包括一第一晶体管、一第六晶体管及一储存电容器。第一晶体管包括一第一漏极端其经施予资料信号、一第一栅极端其经施予扫描信号及一第一源极端其连接至一第二节点。第六晶体管包括一第六源极端其经施予参考值、一第六栅极端其经施予发光控制信号及一第六漏极端其连接至第二节点。储存电容器包括一第一电极及一第二电极，第一电极连接至第二节点，且第二电极连接至资料处理模块。
又，资料处理模块包括一第四晶体管及一第二晶体管。第四晶体管包括一第四源极端其经施予第一电压、一第四栅极端其连接至输入模块及一第四漏极端其连接至切换模块。第二晶体管包括一第二源极端其连接至第三节点、一第二栅极端其经施予扫描信号及一第二漏极端其连接至第四漏极端。
此外，重置模块包括一第五晶体管及一第三晶体管。第五晶体管包括一第五漏极端其经施予参考值及一第五栅极端其经施予一子发光控制信号。第三晶体管包括一第三漏极端其连接至第五晶体管的一第五源极端、一第三栅极端其经施予扫描信号及一第三源极端其连接至第三节点。
在实际应用中，当复数个像素补偿电路经串联连接而形成一组像素补偿电路时，则一第(N+1)级像素补偿电路的发光控制信号作为一第N级像素补偿电路的子发光控制信号，且N为一正整数。
像素补偿电路还包括一发光元件，用以接收发光信号且之后发出光线。
相较于传统技术，本发明的像素补偿电路可用于补偿与主动矩阵有机发光二极体显示器或类似照明系统中薄膜晶体管的元件的电子特性相关的临界参数，以改善影像品质与避免因电压降(IR-drop)效应导致的亮度不均匀。本发明的像素补偿电路界定于一子像素区域中，其中有八个薄膜晶体管与一个电容器，且所述电路系由两个控制信号而操作。相较之下，传统技术使用了三个控制信号。本发明使用较少的控制信号，这有益于布局弹性与规格设计。
在阅读了下文实施方式以及附随图式时，能够最佳地理解本揭示内容的优点与精神。
附图说明
在阅读了下文实施方式以及附随图式时，能够最佳地理解本揭露的多种态样。应注意到，根据本领域的标准作业习惯，图中的各种特征并未依比例绘制。事实上，为了能够清楚地进行描述，可能会刻意地放大或缩小某些特征的尺寸。
图1的概要图式绘示了根据本发明一实施方式的像素补偿电路；
图2的概要图式绘示了本发明的像素补偿电路，其以串联连接而形成一组像素补偿电路；
图3的概要图式绘示了利用本发明之像素补偿电路的显示器系统；
图4的时序图绘示了根据本发明一实施方式之像素补偿电路的操作图；
图5的概要图式绘示了在图4之像素补偿电路在第一时点的操作；
图6的概要图式绘示了在图4之像素补偿电路在第二时点的操作；
图7的概要图式绘示了在图4之像素补偿电路在第三时点的操作。
具体实施方式
参照附随图式详细描述本发明，以清楚地说明本发明之目的、技术方案与优点。
请参照图1，其概要绘示了电路根据本发明一实施方式的像素补偿。本发明的一态样提出了一种像素补偿电路(PCC)1。根据本揭示内容一实施方式，像素补偿电路1包括一输入模块12、一重置模块14、一资料处理模块16及一切换模块18。输入模块12接收一参考值Vref及一资料信号DATA，并可回应一发光控制信号EM及一扫描信号SN，以产生一第一信号。重置模块14接收参考值Vref及回应一子发光控制信号EM+1及扫描信号SN，以产生一重置信号。资料处理模块16接收第一信号、重置信号及一第一电压VDD，并回应扫描信号SN，以产生一第二信号。切换模块18接收第二信号，并回应发光控制信号EM，以产生一发光信号。
子发光控制信号EM+1为发光控制信号EM，其具有一个列时间的偏移。
输入模块12包括一第一晶体管T1、一第六晶体管T6及一储存电容器C1。第一晶体管T1具有一第一漏极端其经施予一资料信号DATA、一第一栅极端其经施予一扫描信号SN、及一第一源极端其连接至一第二节点Q2。第六晶体管T6包括一第六源极端其经施予一参考值Vref、一第六栅极端其经施予一发光控制信号EM、及一第六漏极端其连接至第二节点Q2。储存电容器C1具有一第一电极及一第二电极、第一电极连接至第二节点Q2、及第二电极连接至资料处理模块16。
资料处理模块16包括一第四晶体管T4及一第二晶体管T2。第四晶体管T4具有一第四源极端其经施予一第一电压VDD、一第四栅极端其连接至输入模块12、及一第四漏极端其连接至切换模块18。第二晶体管T2具有一第二漏极端其连接至第四漏极端、一第二栅极端其经施予一扫描信号SN、及一第二源极端其连接至一第三节点Q3。
重置模块14包括一第五晶体管T5及一第三晶体管T3。第五晶体管T5具有一第五漏极端其经施予一参考值Vref、及一第五栅极端其经施予一子发光控制信号EM+1。第三晶体管T3具有一第三漏极端其连接至第五晶体管T5的一第五源极端、一第三晶体管T3的一第三栅极端其经施予一扫描信号SN、及一第三源极端其连接至一第三节点Q3。
切换模块18包括一第七晶体管T7，其具有一第七源极端其连接至资料处理模块16、一第七栅极端其经施予一发光控制信号EM、及一第七漏极端用以输出一发光信号。
像素补偿电路1还包括一发光元件用以接收发光信号且之后发出光线。
在实际应用中，发光元件包括一第一极点及一第二极点。第一极点是用于接收发光信号，且第二极点是连接至一第二电压VEE，其电压值与第一电压VDD不同。
此外，发光元件可以是主动矩阵有机发光二极体(AMOLED)。
在实际运用中，可藉由连接至接地而得到第二电压VEE。
请参照图2，其概要绘示了本发明的像素补偿电路1，其以串联连接而形成一组像素补偿电路1。在实际运用中，当复数个像素补偿电路1经串联连接而形成一组像素补偿电路1时，第(N+1)级像素补偿电路1的发光控制信号EM可作为第N级像素补偿电路1的子发光控制信号EM+1，其中N为一正整数。
由于第N级补偿电路1因为连接至下一级发光控制信号EM+1而可作为子发光控制信号EM+1，因而能够减少所需的信号产生器以及该信号产生器之线路所占据的空间。因此，相较于传统的像素补偿电路需要使用三个控制信号，本发明的像素补偿电路1仅需要两个控制信号，这有利于布局的最佳化。
请参照图3，其概要绘示了利用本发明像素补偿电路1之显示器系统。于一实施方式中，可将具有[N+1]*[M+1]解析度的显示器系统分成两个区域，其中一个是栅极驱动电路阵列(gate driver on array，GOA)电路区域2另一个是显示像素电路区域3，其中显示像素电路区域3是由串联连接的复数个像素补偿电路1所组成。将两倍的列时间作为GOA电路区域2的时间偏移单位以扫描传递，且可利用具有相同功能的积体电路IC来取代GOA电路2。显示像素电路区域3中的每一子像素电路即为本发明的像素补偿电路1，且其系由GOA电路区域2控制与驱动。在一GOA扫描方向中依SN[1]→SN[2]…、EM[1]→EM[2]…的顺序启动作业。在图3中，每一像素补偿电路1仅需要两个控制信号，且可视布局排列的空间与方式将第一电压VDD、第二电压VEE及参考值Vref的线路布局于一水平或垂直方向中，因而能够提升布局排列的弹性。
请参照图4，此时序图绘示了根据本发明一实施方式之像素补偿电路1的作业。图4为本发明之补偿电路1的作业顺序图，应注意到其中仅绘示了第N级与第(N+1)级发光控制信号EM、EM+1以及扫描信号SN、SN+1，且发光控制信号EM、EM+1以及扫描信号SN、SN+1分别偏移一个列时间(L-T)。譬如，在第N级像素补偿电路1中，像素补偿电路1会在三个阶段中运作：一重置阶段(第一时点t1)、一补偿阶段(第二时点t2)及一写入发光阶段(第三时点t3)，下文将分别详述之。在后文所述的图中，加入一第一节点Q1以利说明，其中第一节点Q1为储存电容器C1、第二晶体管T2及第四晶体管T4的电性连接接点。
请参照图4及图5。图5的概要图式绘示了图4之像素补偿电路于第一时点t1的操作。在重置阶段中，由于发光控制信号EM、第六晶体管T6及第七晶体管T7为关闭，且剩余的晶体管导通。此时，第一节点Q1的信号为参考值Vref、第二节点Q2的信号为资料信号DATA且第三节点Q3的信号为参考值Vref。
同一时间，用于驱动的第四晶体管T4的栅极电位Vg是由第一节点Q1(Vref)所供应，源极电位Vs系由第一电压VDD供应，且满足Vsg＝VDD–Vref>Vth，其中Vth为阈值偏压。
由于储存电容器C1的两端为第一节点Q1供应的参考值Vref以及第二节点Q2供应的资料信号DATA，能够重置储存电容器C1两端的电位。
请参照图4及图6。图6的概要图式绘示了图4之像素补偿电路于第二时点t2的操作。在补偿阶段中，由于发光控制信号EM及子发光控制信号EM+1，第五晶体管T5、第六晶体管T6及第七晶体管T7为关闭的。此时，第一节点Q1的电压由Vref变为VDD-|Vth|，第二节点Q2保持先前的状态(DATA)，而第三节点Q3的电压由Vref变为VDD-|Vth|。
同一时间，用于驱动的第四晶体管T4的栅极电位Vg为VDD-|Vth|，且源极电位Vs为VDD。由VDD透过第四晶体管T4来充电第一节点Q1，直到第四晶体管T4中出现夹断，因此使得Vsg＝|Vth|。
此外，由于储存电容器C两端的电极电位分别为VDD-|Vth|以及DATA，能够使得储存电容器C两端的电位重新平衡。
请参照图4及图7。图7的概要图式绘示了图4之像素补偿电路于第三时点t3的操作。在写入发光阶段中，由于扫描信号SN，第一晶体管T1、第二晶体管T2、及第三晶体管T3为关闭的。此时，第一节点Q1的电压由VDD-|Vth|变为VDD–DATA+Vref-|Vth|，第二节点Q2的电压由DATA变为Vref，且第三节点Q3可保持先前状态(VDD-|Vth|)。
同一时间，用于驱动的第四晶体管T4的栅极电位为VDD–DATA+Vref-|Vth|，且源极电位Vs为VDD。第二节点Q2的电位改变使得第一节点Q1因为储存电容器的耦合效应而写入DATA值，使得Vsg＝DATA–Vref+|Vth|。
此时，此一阶段的作业不会受到第五晶体管T5的开启或关闭而影响。
在补偿之后，用以驱动晶体管的电流可表示为以下方程式。
|Isd|＝κ*(|Vsg|-|Vth|)2＝κ*(DATA-Vref)2
上述方程式中没有Vth及VDD，因而能够补偿阈值偏压电压Vth且可改善电压降(IR-drop)效应。
如此一来，本发明的像素补偿电路1可运用于主动矩阵有机发光二极体显示器中，以便补偿薄膜晶体管的阈值偏压Vth且可避免因为元件间电性差异而导致的影像劣化，譬如云纹效应(Mura)。此时，亦可补偿因为系统电力分布而导致的电压降(IR-drop)以改善显示器发光时的面板亮度。
相较于传统技术，本发明的像素补偿电路可用以补偿主动矩阵有机发光二极体显示器或类似照明系统中薄膜晶体管之元件的电子特性相关之临界参数，譬如临界电压Vth，以便改善影像品质以及避免因的电压降(IR-drop)效应而导致的亮度不均。本发明之像素补偿电路系界定于一子像素区域中，其中有八个薄膜晶体管与一个电容器，且电路是由两个控制信号所操作。相较之下，传统技术需使用三个控制信号。本发明所需的控制信号较少，这有助于布局弹性与规格设计。
上文的实施方式已明确描述本发明之特征与范围，但本发明不限于此。此外，各种改变与均等的排置皆属于本发明之申请专利范围之内容。
符号说明：
1 像素补偿电路
2 栅极驱动电路阵列(GOA)电路区域
3 显示像素电路区域
12 输入模块
14 重置模块
16 资料处理模块
18 切换模块18
C1 储存电容器
DATA 资料信号
EM 发光控制信号
EM+1 子发光控制信号
Q1、Q2、Q3 节点
SN 扫描信号
T1、T2、T3、T4、T5、T6、T7 晶体管
VDD 第一电压
Vref 参考值
t1、t2、t3 时点

Claims (20)

1.一种像素补偿电路，包含：
一输入模块，接收一参考值与一资料信号并回应一发光控制信号与一扫描信号而产生一第一信号；
一重置模块，接收该参考值并回应一子发光控制信号及该扫描信号而产生一重置信号，其中该子发光控制信号及该发光控制信号偏移一个列时间；
一资料处理模块，接收该第一信号、该重置信号及一第一电压，并回应该扫描信号而产生一第二信号；以及
一切换模块，接收该第二信号并及回应该发光控制信号而产生一发光信号，
其中该重置模块包括一第三晶体管且该资料处理模块包括一第四晶体管，其中该第三晶体管的一第三源极端其连接至该第四晶体管的一第四栅极端。
2.如权利要求1所述的像素补偿电路，其中该输入模块包含：
一第一晶体管，具有一第一漏极端其经施予该资料信号、一第一栅极端其经施予该扫描信号及一第一源极端其连接至一第二节点；
一第六晶体管，具有一第六源极端其经施予该参考值、一第六栅极端其经施予该发光控制信号及一第六漏极端其连接至该第二节点；以及
一储存电容器，具有一第一电极及一第二电极，其中该第一电极连接至该第二节点，且该第二电极连接至该资料处理模块。
3.如权利要求1所述的像素补偿电路，其中该资料处理模块还包含：
一第二晶体管，具有一第二漏极端其连接至该第四晶体管的一第四漏极端、一第二栅极端其经施予该扫描信号及一第二源极端其连接至一第三节点，
其中该第四晶体管具有一第四源极端其经施予该第一电压，该第四栅极端其连接至该输入模块及该第四源极端其连接至该切换模块。
4.如权利要求3所述的像素补偿电路，其中该重置模块还包含：
一第五晶体管，具有一第五漏极端其经施予该参考值及一第五栅极端其经施予一子发光控制信号，
其中该第三晶体管具有一第三漏极端其连接至该第五晶体管的一第五源极端、一第三栅极端其经施予该扫描信号及该第三源极端其连接至该第三节点。
5.如权利要求1所述的像素补偿电路，其中该切换模块包含：
一第七晶体管，具有一第七源极端其连接至该资料处理模块、一第七栅极端其经施予该发光控制信号及一第七漏极端用于输出该发光信号。
6.如权利要求1所述的像素补偿电路，其中当复数个该像素补偿电路为串联连接以形成一组像素补偿电路时，则一第(N+1)级像素补偿电路的该发光控制信号作为一第N级像素补偿电路的该子发光控制信号，且N为一正整数。
7.一种主动矩阵有机发光二极体显示器，包含：
一像素补偿电路，包含：
一输入模块，接收一参考值及一资料信号并回应一发光控制信号及一扫描信号而产生一第一信号；
一重置模块，接收该参考值并回应一子发光控制信号及该扫描信号而产生一重置信号，其中该子发光控制信号及该发光控制信号偏移一个列时间；
一资料处理模块，接收该第一信号、该重置信号及一第一电压，并回应该扫描信号而产生一第二信号；以及
一切换模块，接收该第二信号并回应该发光控制信号而产生一发光信号，
其中该重置模块包括一第三晶体管且该资料处理模块包括一第四晶体管，其中该第三晶体管的一第三源极端其连接至该第四晶体管的一第四栅极端。
8.如权利要求7所述的主动矩阵有机发光二极体显示器，其中该输入模块包含：
一第一晶体管，具有一第一漏极端其经施予该资料信号、一第一栅极端其经施予该扫描信号及一第一源极端其连接至一第二节点；
一第六晶体管，具有一第六源极端其经施予该参考值、一第六栅极端其经施予该发光控制信号及一第六漏极端其连接至该第二节点；以及
一储存电容器，具有一第一电极及一第二电极，其中该第一电极连接至该第二节点，且该第二电极连接至该资料处理模块。
9.如权利要求7所述的主动矩阵有机发光二极体显示器，其中该资料处理模块包含：
一第二晶体管，具有一第二漏极端其连接至该第四晶体管的一第四漏极端、一第二栅极端其经施予该扫描信号及一第二源极端其连接至一第三节点，
其中该第四晶体管具有一第四源极端其经施予该第一电压，该第四栅极端其连接至该输入模块，且该第四漏极端其连接至该切换模块。
10.如权利要求9所述的主动矩阵有机发光二极体显示器，其中该重置模块包含：
一第五晶体管，具有一第五漏极端其经施予该参考值及一第五栅极端其经施予一子发光控制信号，
其中该第三晶体管具有一第三漏极端其连接至该第五晶体管的一第五源极端、一第三栅极端其经施予该扫描信号及该第三源极端其连接至该第三节点。
11.如权利要求7所述的主动矩阵有机发光二极体显示器，其中该切换模块包含：
一第七晶体管，具有一第七源极端其连接至该资料处理模块、一第七栅极端其经施予该发光控制信号、及一第七漏极端用以输出该发光信号。
12.如权利要求7所述的主动矩阵有机发光二极体显示器，其中当复数个该像素补偿电路为串联连接以形成一组像素补偿电路时，则一第(N+1)级像素补偿电路的该发光控制信号作为一第N级像素补偿电路的该子发光控制信号，且N为一正整数。
13.如权利要求7所述的主动矩阵有机发光二极体显示器，其中该像素补偿电路还包括一发光元件，该发光元件具有一第一极点及一第二极点，该第一极点系用于接收该发光信号，且该第二极点连接至一第二电压，其中该第二电压的电压值与该第一电压不同。
14.一显示器系统，包含：
一像素补偿电路，包含：
一输入模块，接收一参考值及一资料信号并回应一发光控制信号及一扫描信号而产生一第一信号；
一重置模块，接收该参考值并回应一子发光控制信号及该扫描信号而产生一重置信号，其中该子发光控制信号及该发光控制信号偏移一个列时间；
一资料处理模块，接收该第一信号、该重置信号及一第一电压，并回应该扫描信号而产生一第二信号；以及
一切换模块，接收该第二信号并回应该发光控制信号而产生一发光信号，
其中该重置模块包括一第三晶体管且该资料处理模块包括一第四晶体管，其中该第三晶体管的一第三源极端其连接至该第四晶体管的一第四栅极端。
15.如权利要求14所述的显示器系统，其中该输入模块包含：
一第一晶体管，具有一第一漏极端其经施予该资料信号、一第一栅极端其经施予该扫描信号及一第一源极端其连接至一第二节点；
一第六晶体管，具有一第六源极端其经施予该参考值、一第六栅极端其经施予该发光控制信号及一第六漏极端其连接至该第二节点；以及
一储存电容器，具有一第一电极及一第二电极，其中该第一电极连接至该第二节点，且该第二电极连接至该资料处理模块。
16.如权利要求14所述的显示器系统，其中该资料处理模块包含：
一第二晶体管，具有一第二漏极端其连接至该第四晶体管的一第四漏极端、一第二栅极端其经施予该扫描信号及一第二源极端其连接至一第三节点，
其中该第四晶体管具有一第四源极端其经施予该第一电压，该第四栅极端其连接至该输入模块，且该第四漏极端其连接至该切换模块。
17.如权利要求16所述的显示器系统，其中该重置模块包含：
一第五晶体管，具有一第五漏极端其经施予该参考值及一第五栅极端其经施予一子发光控制信号，
其中该第三晶体管具有一第三漏极端其连接至该第五晶体管的一第五源极端、一第三栅极端其经施予该扫描信号及该源极端其连接至该第三节点。
18.如权利要求14所述的显示器系统，其中该切换模块包含：
一第七晶体管，具有一第七源极端其连接至该资料处理模块、一第七栅极端其经施予该发光控制信号及一第七漏极端用以输出该发光信号。
19.如权利要求14所述的显示器系统，其中当复数个该像素补偿电路为串联连接以形成一组像素补偿电路时，则一第(N+1)级像素补偿电路的该发光控制信号作为一第N级像素补偿电路的该子发光控制信号，且N为一正整数。
20.如权利要求14所述的显示器系统，还包含一显示像素电路区域，其系由复数个串联连结与并联连结的该像素补偿电路所组成。
CN201910870811.XA 2018-12-21 2019-09-16 像素补偿电路 Pending CN111354310A (zh)

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