CN111276498A - 阵列基板及其光刻补偿构造的制造方法、显示面板 - Google Patents

阵列基板及其光刻补偿构造的制造方法、显示面板 Download PDF

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CN111276498A
CN111276498A CN202010102202.2A CN202010102202A CN111276498A CN 111276498 A CN111276498 A CN 111276498A CN 202010102202 A CN202010102202 A CN 202010102202A CN 111276498 A CN111276498 A CN 111276498A
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layer
substrate
compensation
compensation pattern
photoetching
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刘汉辰
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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Priority to PCT/CN2020/079869 priority patent/WO2021164086A1/zh
Priority to US16/770,622 priority patent/US20210408077A1/en
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Abstract

本发明公开一种阵列基板光刻补偿构造，包括基板、基底层、感光层及光刻补偿图案层，所述基底层叠设于所述基板一侧表面，所述感光层叠设于所述基底层远离所述基板侧表面，所述光刻补偿图案层夹设于所述基板与所述基底层之间，所述光刻补偿图案层包括多个阵列分布设置的补偿图案，沿所述基板的厚度方向，所述光刻补偿图案层改变了所述基底层的厚度，使所述补偿图案所对应区域的感光层厚度小于所述补偿图案周边相对应区域的感光层厚度。同时本发明还提供一种采用所述阵列基板光刻补偿构造的阵列基板制造方法和采用上述方法获得的阵列基板和显示面板。本发明的阵列基板于导电线路分布密集区域的加工精度高，开口率高且加工效率高，成本低。

Description

阵列基板及其光刻补偿构造的制造方法、显示面板
技术领域
本发明涉及显示技术领域，具体地说，涉及一种阵列基板光刻补偿构造及其制造方法，以及采用所述补偿构造加工而成的阵列基板、显示面板。
背景技术
随着电子产品的发展，消费者对于显示面板的解析度需求不断提升。为了进一步提高解析度，对应的，PPI(Pixels Per Inch,像素数目或像素密度)的提高势在必行。
现有技术的一种显示面板，如图1所示。所述显示面板40包括显示区域41、扇出区43，其中所述显示区域41设于所述显示面板40的中心区域，所述扇出区43设于所述显示面板40的一侧端部。
请同时参阅图2及图3，其中图2是图1所示显示区域的局部放大示意图，图3是图1所示扇出区域的局部放大示意图。于所述显示区域41中，设置多个阵列设置的薄膜晶体管411(TFT-LCD)及垂直相交设置的栅极线413和数据线415。所述栅极线413及所述数据线415的一端连接至所述显示区域41，另一端经所述扇出区43延伸至驱动芯片45。
GOA(Gate Driver On Array,阵列基板行驱动)电路的级数逐渐增加，导致GOA电路的宽度逐渐变窄，如此使得GOA电路中的薄膜晶体管(Thin Film Transistor,TFT)的排布更加集中。进一步的，所述栅极线413与薄膜晶体管411之间的间距进一步减小。同理，所述数据线415与所述薄膜晶体管411之间的间距同样逐渐减小。
另一方面，自所述显示区域41引出至所述扇出区43的导电线路同样会逐渐更加密集排布。
在TFT-LCD阵列制作工艺中，特别是随着高分辨率产品的逐渐导入，TFT-LCD阵列段的各项参数边缘值越来越小，工艺要求更为严格，现有技术采用曝光制程加工工艺在基板上形成导电线路，但是曝光工艺受限于不同材质、不同温度、不同导电线路的走线弯折趋势影响、曝光精度、显影周期等因素影响而难以达到统一的导电线路线宽精度，甚至导致相邻导电线路之间的短路。
业界也有针对不同区域加工精度难以均一化的技术问题，提供一种对应分别补偿的方式来解决上述技术问题，具体如图4及图5所示。但是上述现有技术需要分区域调整光罩尺寸，如此增加成本且效率降低，同时对加工设备和设计空间提出更高要求。
针对现有技术显示面板不同区域导电线路走线疏密程度需求不同以及需要更高加工精度的技术问题，有必要提供一种针对不同区域的导电线路疏密程度相异的区域，对应采用单一光罩和统一加工工艺保证不同区域导电线路的加工精度。
发明内容
有鉴于此，本发明提供一种阵列基板光刻补偿结构及其制造方法，以解决现有技术的显示面板不同区域导电线路间距过小引起的短路及加工成本高、效率低的技术问题。
同时，本发明还提供一种采用上述阵列基板光刻补偿结构的阵列基板及显示面板。
本发明提供一种阵列基板光刻补偿构造，包括基板、基底层、感光层及光刻补偿图案层，所述基底层叠设于所述基板一侧表面，所述感光层叠设于所述基底层远离所述基板一侧表面，所述光刻补偿图案层夹设于所述基板与所述基底层之间，所述光刻补偿图案层包括多个阵列分布设置的补偿图案，沿所述基板的厚度方向，所述光刻补偿图案层改变了所述基底层的厚度，使所述补偿图案所对应区域的感光层厚度小于所述补偿图案周边相对应区域的感光层厚度。
更优的，于本发明阵列基板光刻补偿构造的一实施例中，所述补偿图案是通过光刻工艺形成于所述基板与所述基底层之间。
更优的，于本发明阵列基板光刻补偿构造的一实施例中，所述补偿图案是非晶硅半导体层、绝缘层或者金属导电层中的任意一种。
更优的，于本发明阵列基板光刻补偿构造的一实施例中，所述基底层包括具有遮光层、栅极层、绝缘层、有源层的阵列基板结构。
更优的，于本发明阵列基板光刻补偿构造的一实施例中，所述基底层远离所述基板侧表面还包括待制备层，所述感光层为制备该层图案过程中形成光刻图案所用。
一种阵列基板的制造方法，包括如下步骤：
提供基板；
提供补偿图案层，并形成于所述基板一侧表面，所述补偿图案层包括多个阵列设置的补偿图案；
提供基底层，形成于所述基板一侧表面，并夹设所述补偿图案层于所述基板与所述基底层之间；
提供感光层，所述感光层叠设于所述基底层上，沿所述基板的厚度方向，所述补偿图案所对应区域的感光层厚度小于所述补偿图案周边相对应区域的感光层厚度；
提供光罩，对所述感光层进行感光、显影工艺形成沟槽，沿所述基板的厚度方向，所述沟槽与所述补偿图案相对应，所述补偿图案是在需制备沟槽区域设置图案，形成补偿图案。
更优的，于本发明的阵列基板制造方法中，沿所述补偿图案的水平延伸方向，所述补偿图案的宽度大于或者等于所述沟槽的宽度。
更优的，于本发明的阵列基板制造方法中，所述补偿图案是通过独立的光刻光罩制程加工而成。
本发明还提供一种阵列基板，其包括基板、光刻补偿图案层、基底层及线路层，所述光刻补偿图案层叠设于所述基板一侧表面，所述光刻补偿图案层包括多个补偿图案，所述基底层形成于所述基板一侧表面，所述线路层制成的图案包含沟槽或小孔，所述沟槽或小孔形成图案间隔区，所述补偿图案与所述图案间隔区沿所述基板的厚度方向分别相对应。
本发明同时还提供一种显示面板，包括相互间隔相对设置的阵列基板和彩色滤光片基板、以及收容于所述阵列基板与彩色滤光片基板之间的液晶层，所述阵列基板包括沟槽或小孔及光刻补偿图案层，所述沟槽或小孔形成间隔区，所述光刻补偿图案层包括多个补偿图案，每一补偿图案与其中一间隔区沿所述阵列基板的厚度方向上相对应。
相较于现有技术，在本发明的阵列基板与基底层之间增加设置光刻补偿图案作为光刻补偿结构，增加了所述基底层的厚度，因所述感光层在制备过程中的自流平效应，使得所述补偿图案所对应区域的感光层厚度小于所述补偿图案周边相对应区域的感光层厚度，因为所述感光层的膜厚与基底层覆盖区域的间隔区域的加工关键尺寸精度呈负相关线性关系，也就是说，增加设置所述补偿图案于所述感光层下方，减小基底层覆盖区域上方的感光层厚度，如此感光显影后的沟槽宽度增加，使得相邻导电线路之间的间隔宽度增加，降低加工难度和降低对加工设备的极限要求。同时，对于同一显示面板的加工工艺而言，其不需要根据不同导电线路疏密程度来调整光罩尺寸，降低成本和提高加工效率。
进一步的，因为所述补偿图案可以直接利用现有导电线路设置工艺直接加工形成，不需要额外增加加工成本的前提下，提高加工精度和产品良率。当然，其还可以基于现有薄膜晶体管阵列加工的基础，通过单独的曝光工艺直接加工所述补偿图案，简化工艺。
附图说明
图1是现有技术一种显示面板的平面结构示意图；
图2是图1所示A区域局部放大示意图；
图3是图1所示B区域局部放大示意图；
图4是现有技术中显示区域与扇出区域采用统一工艺加工导电线路结果示意图；
图5是现有技术结合显示区域线宽进行补偿工艺加工显示区域与扇出区域导电线路结果示意图；
图6是本发明一种显示面板的立体结构示意图；
图7是图6所示阵列基板的平面示意图；
图8是图7所示显示区域阵列基板的C区域放大示意图；
图9是图7所示周边区域阵列基板的D区域放大示意图；
图10是图7所示周边区域的局部剖视图；
图11是图10所示周边区域第二间隔的加工工艺步骤示意图。
具体实施方式
下面将结合本发明实施例中的附图，对本发明所提供的各个示例性的实施例的技术方案进行清楚、完整地描述。在不冲突的情况下，下述各个实施例及其技术特征可以相互组合。
本发明提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧方、周围、中央、水平、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附图的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。另外，对于特性相同或相似的结构元件，本发明采用相同的标号进行标识。
请参阅图6，是本发明一种显示面板的立体结构示意图。所述显示面板10包括阵列基板11、液晶层13及彩色滤光片基板15。所述阵列基板11与所述彩色滤光片基板15相对间隔设置，所述液晶层13夹设于所述阵列基板11与所述彩色滤光片基板15之间。
请结合参阅图7-9，其中图7是图6所示阵列基板的平面示意图，图8是图7所示显示区域阵列基板的C区域放大示意图，图9是图7所示周边区域阵列基板的D区域放大示意图。所述阵列基板11与所述彩色滤光片基板15叠设形成位于中心区域的显示区域20和环绕所述显示区域20设置的周边区域30，所述显示区域20位于中心区域，用于显示画面；所述周边区域30位于所述显示区域20的周边，多个驱动器件和导电线路设于所述周边区域30用于实现走线布局。
于所述显示区域20内，所述阵列基板11包括基板111、于所述基板111表面垂直交叉设置的多个栅极线113和多个数据线115。所述多个栅极线113与所述多个数据线115共同界定多个阵列设置的像素区域117。所述像素区域117内设置薄膜晶体管118和像素电极119。所述薄膜晶体管118的栅极1181与栅极线113对应电连接，所述源极1183与数据线115对应电连接，所述漏极1185与所述像素电极119对应电连接。设定在该区域内，所述栅极线113、所述数据线115、所述像素区域的导电线路定义为第一导电线路，相邻第一导线线路之间的间隔定义为第一间隔201。
所述栅极线113及所述数据线115自所述显示区域20延伸至周边区域30。
于所述周边区域30内，设置多个公共电极端子(图未示)、阵列行驱动线路(未标示)、静电放电端子(图未示)、扇出区域、驱动芯片连接电极、印刷电路板焊接电极、复用驱动架构等多个功能区域，所述不同功能区域通过导电线路对应分别电连接。设定于该区域内的导电线路为第二导电线路，相邻第二导电线路之间的间隔定义为第二间隔301。
位于所述显示区域20内的第一导电线路之间的第一间隔201的宽度d1大于位于周边区域30内的第二导电线路之间的第二间隔301的宽度d2。
请参阅图10，是图7所示周边区域的局部剖视图。所述周边区域30的阵列基板11包括基板111、依次形成于所述基板111一侧表面的补偿图案层121、基底层123及第二导电线路层125。
所述基板111是玻璃基板，承载所述第一导电线路及所述第二导电线路并形成所述显示区域20和所述周边区域30。
所述补偿图案层121包括多个阵列分布于所述基板111表面的补偿图案122，所述补偿图案122夹设于所述基板111与基底层123之间，沿所述基板的厚度方向，所述补偿图案122与所述第二间隔301相对应。同时沿着所述补偿图案延伸方向，所述补偿图案122的宽度d3大于所述第二间隔301的宽度d2。当然，作为上述实施方式的进一步改进，所述补偿图案122的宽度d3也可以等于所述第二间隔301的宽度d2。所述光刻补偿图案层121是非晶硅半导体层、绝缘层或者金属导电层中的任意一种。优选地，所述补偿图案122是通过光刻工艺形成于所述基板111与所述基底层123之间。在本实施方式中，所述补偿图案122可以是基于通过曝光工艺加工薄膜晶体管118的工艺基础上，增加一道独立的曝光工艺即可实现对补偿图案122的加工。当然，所述补偿图案122不仅仅局限于上述实施方式加工而成，其还可以是其他工艺加工而成，比如：化学沉积方法实现，凡是在基底层123与基板111之间形成补偿层，以调整用以加工导电线路的感光层(参阅图11)厚度的方案皆属于本发明的创造宗旨，属于本发明的保护范畴。
所述基底层123是直接形成于基板111表面的绝缘层或者半导体层，其同时覆盖所述基板111表面及所述补偿图案122。优选地，所述基底层123包括具有遮光层、栅极层、栅绝缘层、有源层等阵列基板结构。
所述第二导电线路125是形成于所述基板111表面的导电线路，其可以是扇出区域的导线，也可以是栅极驱动电极端子，或者是连接驱动芯片、控制电路板的电极端子等，在本发明的具体实施方式中，对本领域技术人员而言，设置在阵列基板11的导电线路，且相邻导电线路之间的间隔值在设定的范围内的，皆可认定为第二导电线路。
在本实施方式中，所述显示面板10包括位于中心的显示区域20及环绕中心区域的周边区域，设定显示区域的相邻导电线路之间的间隔为第一间隔，设定周边区域的相邻导电线路的间隔为第二间隔，且所述第一间隔值大于所述第二间隔值，也就是说，所述显示区域20与所述周边区域30内的相邻导电线路之间的间隔值相异，且第一间隔值大于所述第二间隔值，因此所述周边区域30内的导电线路排布相较于所述显示区域20内的导电线路排布更加密集。具体的，所述间隔区域是形成在阵列基板11表面的沟槽或者小孔，所述沟槽或小孔是通过在基底层123表面通过曝光工艺或化学沉积等工艺加工而成的导电线路之间的间隔区域。具体而言，其可以是相邻第一导电线路之间的第一间隔201，还可以是相邻第二导线线路之间的第二间隔301，所述间隔可以是沟槽或者小孔。
在导电线路排布相对舒松的显示区域20内，于所述第一间隔对应的相邻第一导电线路之间未被导电线路覆盖，对应的，未增加设置补偿图案，所述第一导电线路加工过程中的加工精度是由预设的光罩尺寸确定的。
在导线线路排布密集的周边区域30内，于所述第二间隔对应的相邻第二导线线路之间未被导电线路覆盖，对应的，增加设置补偿图案122，在采用与显示区域20内相统一的光罩尺寸加工的基础上，所述补偿图案122进一步补偿所述第二导线线路加工过程中的边缘关键尺寸误差，增加第二间隔值，保障所述相邻第二导电线路的加工精度。
如此，通过在导电线路分布密集区域增加设置补偿图案122的方式来有效补偿所述补偿图案122对应的相邻导电线路之间的间隔区域的关键尺寸加工误差，扩大间隔值，提高开口率和加工精度，避免修改光罩，降低成本。
相较于现有技术，在本发明的显示面板的阵列基板11中，于导电线路密集区域，对应沿所述基板11的厚度方向增加设置补偿图案122，通过所述补偿图案122改变了基底层123的厚度，进而减小感光层厚度，增加对应位置的相邻导电线路之间间隔值，提高加工精度，使得整个阵列基板的导电线路加工精度接近设计值，更加统一化。
请参阅图11，是图10所示周边区域第二间隔的加工工艺步骤示意图。当对位于周边区域30内的第二导电线路进行加工时，包括如下步骤：
步骤S01，提供所述基板111；
步骤S02，于所述基板111上形成所述补偿图案层121，所述补偿图案层121包括多个分布于所述基板111表面的补偿图案122；
在该步骤中，沿所述基板111厚度方向，所述补偿图案122是在需制备沟槽的间隔区域设置图案，形成补偿图案。所述光刻补偿图案层121是非晶硅半导体层、绝缘层或者金属导电层中的任意一种，其形成方法为现有技术，例如，可以采用曝光工艺或化学气相沉积法形成，更具体的，所述曝光工艺是通过独立的曝光工艺直接加工而成。
步骤S03，提供基底层123，形成于所述基板111的一侧表面，并覆盖所述基板111及所述补偿图案层121；
在该步骤中，所述基底层123包括具有遮光层、栅极层、绝缘层、有源层等阵列基板结构，各层的形成方法均为现有技术，例如，所述遮光层可通过涂布方式形成，所述栅极层和所述有源层通过曝光工艺和蚀刻工艺形成，所述栅极绝缘层采用化学气相沉积法形成。
步骤S04，提供感光层124，所述感光层124叠设于所述基底层123上，沿所述基板111的厚度方向，所述补偿图案122所对应区域的感光层124厚度小于所述补偿图案122周边相对应区域的感光层124厚度；
在该步骤中，可通过在所述基底层123表面涂布光敏胶材形成所述感光层124，由于所述基板111一侧表面形成有所述光刻补偿图案层121，从而增加了所述基底层123的厚度，因此，在所述感光层124的制备过程中，因其自流平效应，使得所述补偿图案122所对应区域的感光层厚度小于所述补偿图案122周边相对应区域的感光层厚度。
步骤S05，提供光罩(图未示)，通过所述光罩对所述感光层进行显影，获得第二沟槽或小孔，所述第二沟槽或小孔形成间隔区，所述补偿图案与所述图案间隔区沿所述基板111的厚度方向分别相对应，所述第二沟槽对应相邻第二导电线路之间的第二间隔，沿所述基板的厚度方向，所述第二沟槽对应所述补偿图案122设置。具体而言，所述补偿图案122的宽度略大于或者等于所述第二沟槽的宽度，如图10所示；
步骤S06，于所述第二沟槽两侧形成相邻间隔设置的第二导电线路，去除感光层，至此，获得阵列基板11。
在对第二导电线路加工过程中，可以采用现有技术中的光罩光刻工艺加工，在所述导电线路形成前，在所述基底层123表面涂布导电层，然后经过光罩光刻工艺加工而成，也就是说，所述导电线路形成之前，是直接在待制备层加工形成阵列设置的沟槽或者小孔，沿所述基板111厚度方向，在沟槽或者小孔所对应区域设置所述补偿图案122，在形成沟槽或者小孔之前，所述补偿图案122对应的位置称作待制备层，形成所述补偿图案122和沟槽或小孔后的导电层称作线路层。
需要说明的是，在对所述周边区域进行光刻加工的同时，也采用光罩对应显示区域进行光刻加工，工艺基本一致，唯区别在于：所述周边区域30需要增加设置补偿图案层121，以补偿增加所述第二沟槽的宽度值，以提高第二导电线路之间的间隔值，使得显示区域20与周边区域30的导电线路之间的间隔值更加精确，提高产品可靠度。
在本发明所示阵列基板11中，所述第一间隔与所述第二间隔所在区域并不局限于周边区域及显示区域，对本领域技术人员而言，在所述显示面板10中，阵列基板包括导电线路分布密集度相异的至少二区域，相对而言，凡是设定导电线路布局较为密集区域，对应相邻导电线路之间增加设置用以补偿光罩显影工艺导致的精度降低进行补偿，以扩大相邻导电线路之间未被导电线路覆盖区域的间隔值，对应的提高加工精度，提高开口率，降低加工成本和提高加工效率。所谓显示区域和周边区域，是相对而言的，旨在区别导电线路分布密集度相异的不同区域，并不具体指某一具体的区域。
尽管已经相对于一个或多个实现方式示出并描述了本发明，但是本领域技术人员基于对本说明书和附图的阅读和理解将会想到等价变型和修改。本发明包括所有这样的修改和变型，并且仅由所附权利要求的范围限制。特别地关于由上述组件执行的各种功能，用于描述这样的组件的术语旨在对应于执行所述组件的指定功能(例如其在功能上是等价的)的任意组件(除非另外指示)，即使在结构上与执行本文所示的本说明书的示范性实现方式中的功能的公开结构不等同。
即，以上所述仅为本发明的实施例，并非因此限制本发明的专利范围，凡是利用本发明说明书及附图内容所作的等效结构或等效流程变换，例如各实施例之间技术特征的相互结合，或直接或间接运用在其他相关的技术领域，均同理包括在本发明的专利保护范围内。
此外，尽管本说明书的特定特征已经相对于若干实现方式中的仅一个被公开，但是这种特征可以与如可以对给定或特定应用而言是期望和有利的其他实现方式的一个或多个其他特征组合。而且，就术语“包括”、“具有”、“含有”或其变形被用在具体实施方式或权利要求中而言，这样的术语旨在以与术语“包含”相似的方式包括。进一步地，应当理解，在本文中提及的“多个”是指两个或两个以上。

Claims (10)

1.一种阵列基板光刻补偿构造，包括：
基板；
基底层，所述基底层叠设于所述基板一侧表面；
感光层，叠设于所述基底层远离所述基板一侧表面，其特征在于，还包括光刻补偿图案层，所述光刻补偿图案层夹设于所述基板与所述基底层之间，所述光刻补偿图案层包括多个阵列分布设置的补偿图案，沿所述基板的厚度方向，所述光刻补偿图案层改变了所述基底层的厚度，使所述补偿图案所对应区域的感光层厚度小于所述补偿图案周边相对应区域的感光层厚度。
2.如权利要求1所述阵列基板光刻补偿构造，其特征在于，所述补偿图案是通过光刻工艺形成于所述基板与所述基底层之间。
3.如权利要求1所述的阵列基板光刻补偿构造，其特征在于，所述光刻补偿图案层是非晶硅半导体层、绝缘层或者金属导电层中的任意一种。
4.如权利要求1所述的阵列基板光刻补偿构造，其特征在于，所述基底层包括具有遮光层、栅极层、绝缘层、有源层的阵列基板结构。
5.如权利要求1所述的阵列基板光刻补偿构造，其特征在于，所述基底层远离所述基板侧表面还包括待制备层，所述感光层为制备该层图案过程中形成光刻图案所用。
6.一种阵列基板的制造方法，包括如下步骤：
提供基板；
提供光刻补偿图案层，并形成于所述基板一侧表面，所述光刻补偿图案层包括多个阵列设置的补偿图案；
提供基底层，形成于所述基板一侧表面，并夹设所述补偿图案层于所述基板与所述基底层之间；
提供感光层，所述感光层叠设于所述基底层上，沿所述基板的厚度方向，所述补偿图案所对应区域的感光层厚度小于所述补偿图案周边相对应区域的感光层厚度；
提供光罩，对所述感光层进行感光、显影工艺形成沟槽，沿所述基板的厚度方向，所述沟槽与所述补偿图案相对应，所述补偿图案是在需制备沟槽区域设置图案，形成补偿图案。
7.如权利要求6所述的阵列基板制造方法，其特征在于，沿所述补偿图案的水平延伸方向，所述补偿图案的宽度大于或者等于所述沟槽的宽度。
8.如权利要求6所述的阵列基板制造方法，其特征在于，所述补偿图案是通过独立的光刻光罩制程加工而成。
9.一种阵列基板，包括：
基板；
基底层，形成于所述基板一侧表面，在所述基底层制备光刻补偿图案层，所述光刻补偿图案层包括多个阵列设置的补偿图案，所述补偿图案夹设在所述基底层与所述基板之间；及
线路层，形成于所述基底层远离所述基板一侧表面，所述线路层制成的图案包含沟槽或小孔，所述沟槽或小孔形成图案间隔区，所述补偿图案与所述图案间隔区沿所述基板的厚度方向分别相对应。
10.一种显示面板，包括相互间隔相对设置的阵列基板和彩色滤光片基板、以及收容于所述阵列基板与彩色滤光片基板之间的液晶层，其特征在于：所述阵列基板包括沟槽或小孔及光刻补偿图案层，所述沟槽或小孔形成间隔区，所述光刻补偿图案层包括多个补偿图案，每一补偿图案与其中一间隔区沿所述阵列基板的厚度方向上相对应。
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