CN111194478A - 电子控制装置 - Google Patents

电子控制装置 Download PDF

Info

Publication number
CN111194478A
CN111194478A CN201880065755.6A CN201880065755A CN111194478A CN 111194478 A CN111194478 A CN 111194478A CN 201880065755 A CN201880065755 A CN 201880065755A CN 111194478 A CN111194478 A CN 111194478A
Authority
CN
China
Prior art keywords
outermost peripheral
wiring board
peripheral corner
solder joint
semiconductor package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201880065755.6A
Other languages
English (en)
Inventor
加藤薰子
河喜多心哉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Astemo Ltd
Original Assignee
Hitachi Automotive Systems Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Automotive Systems Ltd filed Critical Hitachi Automotive Systems Ltd
Publication of CN111194478A publication Critical patent/CN111194478A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02KDYNAMO-ELECTRIC MACHINES
    • H02K11/00Structural association of dynamo-electric machines with electric components or with devices for shielding, monitoring or protection
    • H02K11/30Structural association with control circuits or drive circuits
    • H02K11/33Drive circuits, e.g. power electronics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B60VEHICLES IN GENERAL
    • B60KARRANGEMENT OR MOUNTING OF PROPULSION UNITS OR OF TRANSMISSIONS IN VEHICLES; ARRANGEMENT OR MOUNTING OF PLURAL DIVERSE PRIME-MOVERS IN VEHICLES; AUXILIARY DRIVES FOR VEHICLES; INSTRUMENTATION OR DASHBOARDS FOR VEHICLES; ARRANGEMENTS IN CONNECTION WITH COOLING, AIR INTAKE, GAS EXHAUST OR FUEL SUPPLY OF PROPULSION UNITS IN VEHICLES
    • B60K1/00Arrangement or mounting of electrical propulsion units
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838Geometry or layout
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0271Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13017Shape in side view being non uniform along the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109Indium [In] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113Bismuth [Bi] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/1312Antimony [Sb] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141Disposition
    • H01L2224/1412Layout
    • H01L2224/1413Square or rectangular array
    • H01L2224/14131Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1605Shape
    • H01L2224/16057Shape in side view
    • H01L2224/16058Shape in side view being non uniform along the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705Shape
    • H01L2224/17051Bump connectors having different shapes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171Disposition
    • H01L2224/1712Layout
    • H01L2224/1713Square or rectangular array
    • H01L2224/17134Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/17135Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171Disposition
    • H01L2224/1712Layout
    • H01L2224/1713Square or rectangular array
    • H01L2224/17134Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/17136Covering only the central area of the surface to be connected, i.e. central arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171Disposition
    • H01L2224/1712Layout
    • H01L2224/17179Corner adaptations, i.e. disposition of the bump connectors at the corners of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/175Material
    • H01L2224/17505Bump connectors having different materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81193Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/38Effects and problems related to the device integration
    • H01L2924/381Pitch distance
    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02KDYNAMO-ELECTRIC MACHINES
    • H02K2211/00Specific aspects not provided for in the other groups of this subclass relating to measuring or protective devices or electric components
    • H02K2211/03Machines characterised by circuit boards, e.g. pcb
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/0939Curved pads, e.g. semi-circular or elliptical pads or lands
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/094Array of pads or lands differing from one another, e.g. in size, pitch, thickness; Using different connections on the pads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09418Special orientation of pads, lands or terminals of component, e.g. radial or polygonal orientation
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09372Pads and lands
    • H05K2201/09427Special relation between the location or dimension of a pad or land and the location or dimension of a terminal
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/042Remote solder depot on the PCB, the solder flowing to the connections from this depot
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04Soldering or other types of metallurgic bonding
    • H05K2203/047Soldering with different solders, e.g. two different solders on two sides of the PCB
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Abstract

控制马达的控制部具有半导体装置,半导体装置具有:具有多个第一电极的半导体封装体;具有以与多个第一电极分别对应的方式配置的多个第二电极的配线基板;以及连接第一电极和第二电极的焊锡接合部,配置于配线基板的最外周角部的第二电极的前端部位于比半导体封装体的外周端部靠外侧。

Description

电子控制装置
技术领域
本发明涉及电子控制装置
背景技术
近年来,随着电子器件的小型化、高密度化以及高功能化,对半导体装置也要求小型化及高密度化。因此,作为半导体装置,多利用BGA(Ball Brid Array)、CSP(Chip SizePackage)这样的面阵型的封装体型半导体装置。
面阵型的封装体型半导体装置在背面以一定的尺寸、面积以及间距形成有电极及焊锡球。为了与这些电极及焊锡球对应,配线基板的电极也以一定的尺寸、面积以及间距形成。然后,通过在配线基板搭载封装体型半导体装置并加热,形成焊接凸块,对应的电极彼此接合。
例如,在专利文献1公开了以下构造:在BGA封装体与配线基板的连接中,配线基板的最外周电极中的位于阵列状配列的最外侧的端部位于比BGA封装体侧的最外周电极中的位于阵列状配列的最外侧的端部靠阵列状配列的外侧,将配线基板的电极表面和焊接凸块表面形成的角度设为锐角。
现有技术文献
专利文献
专利文献1:日本特开2000-114315号公报
发明内容
发明所要解决的课题
面阵型的封装体型半导体装置由于各构成部件的线膨胀系数的差异而在具有温度负荷时变形,对最外周的焊接凸块施加应力。
特别是BGA封装体的对最外周角部的焊接凸块的负荷大,且在这些焊接凸块中,尤其在与焊接凸块上侧的电极的界面显著引起皲裂伸展,使热疲劳寿命降低。
具体而言,在经由焊接凸块将面阵型封装体连接于配线基板的半导体装置中,由于使用环境下的温度变化,半导体装置整体变形。但是,各个构成部件由于线膨胀系数的差异而翘曲量分别不同,在面阵型封装体与配线基板间的焊接凸块引起皲裂伸展。特别是面阵型封装体的最外周角部的焊接凸块容易损坏,热疲劳寿命降低,从而半导体装置的可靠性降低。
专利文献1提到了缓和外部冲击时对最外周焊接凸块施加的应力。但是,由于构成部件的线膨胀系数的差异,翘曲量分别不同,对于因此而对热疲劳寿命产生的影响未进行考虑。
本发明的目的在于,在内置有半导体装置的电子控制装置中,防止热疲劳寿命降低。
用于解决课题的方案
本发明的一方案的电子控制装置具备控制马达的控制部,其特征在于,上述控制部具有半导体装置,上述半导体装置具有:半导体封装体,其具有多个第一电极;配线基板,其具有以与上述多个第一电极分别对应的方式配置的多个第二电极;以及焊锡接合部,其连接上述第一电极和上述第二电极,配置于上述配线基板的最外周角部的上述第二电极的前端部位于比上述半导体封装体的外周端部靠外侧。
发明的效果
根据本发明的一方案,在内置有半导体装置的电子控制装置中,能够防止热疲劳寿命降低。
附图说明
图1是实施例1的半导体装置的剖视图。
图2是实施例1的半导体装置的俯视图。
图3是表示实施例1的半导体装置的制造工序的剖视图。
图4是实施例2的半导体装置的俯视图。
图5是实施例2的半导体装置的俯视图。
图6是实施例3的半导体装置的俯视图。
图7是实施例4的电子控制装置的块图。
图8是搭载于实施例4的电子控制装置的半导体装置的剖视图。
具体实施方式
面阵型的封装体型半导体装置(半导体封装体)的电极及焊锡球由封装体制造厂预先形成,焊锡球的组成一般为Sn-3.0Ag-0.5Cu。
焊接凸块通过缩小尺寸及间距可以在一定面积内配置多个,有利于小型化及高密度化。另外,由于相比经由引线连接的构造,配线长度更短,因此有利于高速传送,能够实现高性能化。
面阵型的封装体型半导体装置的BGA封装体是作为半导体元件的Si片通过例如引线连接于硅中介层。构成为,在硅中介层的背面形成有电极及焊锡球,利用树脂在硅中介层上进行塑模。将其经由焊接凸块连接于配线基板,但由于各结构部件的线膨胀系数的差异,在具有温度负荷时变形,在BGA封装体的最外周的焊接凸块作用应力。
特别地,对BGA封装体的最外周角部的焊接凸块的负荷大,且在这些焊接凸块中,尤其在与焊接凸块上侧的电极的界面显著引起皲裂伸展,成为热疲劳寿命降低的主要原因。
在以下的实施例中,在经由焊接凸块将面阵型封装体连接于配线基板的半导体装置中,降低作用于最外周角部的焊接凸块的应力,防止热疲劳寿命降低。
以下,参照附图对实施例进行说明。
实施例1
参照图1~图3,对实施例1的半导体装置进行说明。
如图1所示,半导体装置具有配线基板1和半导体封装体(面阵型封装体)2。配线基板1在上表面具有多个电极4。半导体封装体2在下表面具有多个电极3。半导体封装体2经由连接多个电极4和多个电极3的焊锡接合部(凸块)5与配线基板1对置地安装。
形成于配线基板1的上表面的电极4中的最外周角部以外的电极4b以与配备于半导体封装体2的下表面的电极3对置的方式均匀地形成。最外周角部以外的焊锡接合部5b具有鼓型的凸块形状。配置于最外周角部的焊锡接合部5a具有延伸到比半导体封装体2的外周端部靠外侧的倒角形状。
最外周角部的四个电极4a的前端部位于比半导体封装体2的外周端部靠外侧。因此,最外周角部的焊锡接合部5a的前端部也位于比半导体封装体2的外周端部靠外侧。
如图2所示,在配线基板1之上安装有半导体封装体2。最外周角部以外的配线基板上的电极4b以与设于半导体封装体2的下表面的电极3对应的方式以圆形形状配置。电极4b的尺寸可以与电极3相同,从生产的观点出发,也可以不同,只要适当设计即可。
如图2所示,就最外周角部的配线基板1上的电极4a的形状而言,将进入半导体封装体2的内侧的端部设为圆形,使露出在半导体封装体2的外侧的端部的形状具有角。但是,不限于该形状,只要最外周角部的配线基板1上的电极4a的前端部露出在半导体封装体2的外周即可,露出在半导体封装体2的外侧的端部也可以设为圆形,也可以将电极4a的形状设为椭圆。
这样,就实施例1的半导体装置而言,配置于配线基板1的最外周角部的电极4a的前端部位于比半导体封装体2的外周端部靠外侧。进一步地,配置于配线基板1的最外周角部的焊锡接合部5a的前端部也位于比半导体封装体2的外周端部靠外侧。
进一步地,配置于配线基板1的最外周角部的电极4a的面积比配置于半导体封装体2的最外周角部的电极3的面积大。进一步地,配置于配线基板1的最外周角部的电极4a的面积比配置于配线基板1的最外周角部以外的电极4b的面积大。
而且,如图2所示,配置于配线基板1的最外周角部的电极4a的中心9b相比配置于半导体封装体2的最外周角部的电极3的中心9a,向从半导体封装体2的中心朝向外侧的方向偏移。
另外,配置于配线基板1的最外周角部的焊锡接合部5a的形状与配置于配线基板1的最外周角部以外的焊锡接合部5b的形状不同。具体而言,配置于配线基板1的最外周角部的焊锡接合部5a具有延伸到比半导体封装体2的外周端部靠外侧的倒角形状。配置于配线基板1的最外周角部以外的焊锡接合部5b具有鼓型的形状。
另外,如图2所示,配置于配线基板1的最外周角部的电极4a配置于最外周角部的对角线上。
接下来,参照图3,对实施例1的半导体装置的制造工序进行说明。
首先,在配线基板1之上形成多个电极4(参照图3(a))。在此,配线基板1在其上表面具有电极4。就电极4而言,最外周角部的电极4a和除此以外的电极4b具有不同的面积,电极4a的面积比电极4b的面积大。
然后,面向配线基板1上的电极4形成焊锡6(参照图3(b))。此时,迎面焊锡6可以通过印刷形成,也可以通过分配器涂布,其形成方法不限于此。迎面焊锡6的组成可以与在半导体封装体2预先形成的焊锡球7相同,也可以不同。从搭载于配线基板1的半导体封装体2以外的电子部件的接合性、生产性以及可靠性的观点出发,综合判断。
使用搭载机(未图示)在迎面焊锡6的形成部位搭载半导体封装体2。然后,在位于半导体封装体2的最外周角部的配线基板1上的电极4a搭载含有Bi、In、Sb的任一个或多个元素的金属片8(参照图3(c))。此时,从生产性的观点出发,期望金属片8也具有能够通过搭载机进行卷盘搭载的片型焊锡形状。
搭载于电极4a的金属片8的体积根据配备于半导体封装体2的焊锡球7的体积及电极4a的面积计算而决定。此外,也可以在搭载金属片8后搭载半导体封装体2,该搭载顺序可适当决定。
然后,使用回流炉(未图示)将半导体封装体2和搭载有金属片8的配线基板1加热,使焊锡球7和迎面焊锡6及金属片8熔融。之后,通过冷却,半导体封装体2和配线基板1接合(参照图3(d))。此时,半导体封装体2的最外周角部的焊锡接合部5a和除此以外的焊锡接合部5b的焊锡接合部的金属组成不同。具体而言,最外周角部的焊锡接合部5a的Bi、In、Sb的至少任一个元素的浓度比焊锡接合部5b高。在此,Bi、In、Sb是提高热疲劳寿命的元素。半导体封装体2的最外周角部的焊锡接合部5a与除此以外的焊锡接合部5b的组成不同,能够简单地改变长寿命组成。这样,图1所示的半导体装置完成。
实施例1中,通过使含有Bi、In、Sb的任一个或多个元素的金属片8熔融,Bi、In、Sb的任一个或多个金属仅在主要组成为SnAgCu的半导体封装体2的最外周角部的焊锡接合部5a扩散。由此,能够使热疲劳寿命长寿命化。
另外,在实施例1中,通过使金属片8熔融,能够容易地使最外周角部的焊锡接合部5a的体积增大。由此,通过最外周角部的焊锡接合部5a成为倒角形状,应力的施加部位改变,能够抑制裂纹进展。其结果,半导体封装体2的最外周角部的焊锡接合部5a的应力降低,能够提高安装半导体封装体2时的可靠性。
进一步地,在实施例1中,能够不变更半导体封装体2的焊锡球7本身的焊锡组成,而且变更最外周角部的焊锡接合部5a的焊锡组成。其结果,能够利用市售品的半导体封装体2,因此能够削减制造成本。
在此,在焊锡接合部5的组成为一般的Sn-3Ag-0.5Cu的模型A和焊锡接合部5a的组成为Sn-3Ag-3Bi-3In且焊锡接合部5b的组成为Sn-3Ag-0.5Cu的模型B这两种模式中,实施热应力解析。
在此,就模型A而言,构成为,形成于配线基板1上的电极4a和电极4b的面积相同,半导体封装体2的最外周角部的焊锡接合部5a和除此以外的焊锡接合部5b的形状具有相同的凸块形状,在该构造中,焊锡接合部5的组成为一般的Sn-3Ag-0.5Cu。另一方面,就模型B而言,构成为,使电极4a的前端部位于比半导体封装体2的外周端部靠外侧,将最外周角部的焊锡接合部5a设为倒角形状,在该构造中,该焊锡接合部5a的组成为Sn-3Ag-3Bi-3In,焊锡接合部5b的组成为Sn-3Ag-0.5Cu。除了电极4a的尺寸及最外周角部的焊锡接合部5a的形状及组成以外,模型A、模型B完全相同。
对于模型A、模型B,在赋予模拟反复-40℃和125℃的温度循环试验的热负荷的解析结果中,模型B的最外周角部的焊锡接合部5a的热疲劳寿命相比模型A的最外周角部的焊锡接合部5a的热疲劳寿命,成为1.9倍。根据该热应力解析的结果,也可知,在实施例1中,热疲劳寿命提高。
实施例2
参照图4、图5,对实施例2的半导体装置进行说明。
在图2所示的实施例1的半导体装置中,与半导体封装体2的最外周角部对应的配线电极1的电极4a配置于角的对角线上。与之相对,图4所示的实施例2的半导体装置中,与半导体封装体2的最外周角部对应的配线电极1的电极4a引出到半导体封装体2的对置的边的垂直方向的延长线上。该情况下,最外周角部的焊锡接合部5a为在半导体封装体2的对置的边的垂直方向上具有长边的倒角形状。
另外,如图5所示,除了最外周角部的电极4a,将半导体封装体2的对置的边的最外周的电极4c的外侧端部也露出在半导体封装体2的外周外侧,将位于半导体封装体2的对置的边的最外周的焊锡接合部设为倒角形状。
在图4、图5中,成为倒角形状的半导体封装体2的对置的边的最外周的焊锡接合部5a的组成与除此以外的焊锡接合部5b相比,Bi、In、Sb的至少任一个元素的浓度更高。
除此以外的结构与实施例1的半导体装置相同,因此省略其说明。
实施例3
参照图6,对实施例3的半导体装置进行说明。
如图6所示,就实施例3的半导体装置而言,与半导体封装体2的最外周角部对应的配线电极1的电极4a将其外侧端部露出在角的对角线上,将半导体封装体2的对置的各个边的最外周的电极4c引出到半导体封装体2的对置的边各自的垂直方向的延长线上。
该情况下,最外周角部的焊锡接合部5a为在角部的对角方向上具有长边的倒角形状,除此以外的最外周的焊锡接合部为在半导体封装体2的对置的边的垂直方向上具有长边的倒角形状。
此外,最外周角部的焊锡接合部5a也可以不是在角部的对角方向上具有长边的倒角形状,也可以是在半导体封装体2的对置的某个边的垂直方向上具有长边的倒角形状。
在图6中,成为倒角形状的半导体封装体2的最外周的焊锡接合5a的组成与除此以外的焊锡连接部5b相比,Bi、In、Sb的至少任一个元素的浓度更高。
除此以外的结构与实施例1的半导体装置相同,因此省略其说明。
实施例4
参照图7、图8,对具有实施例1的半导体装置的电子控制装置进行说明。
在面向车载的电子设备中,从确保车室内空间的观点出发,其设置环境从车室内向发动机舱内转移,要求更高温环境下的耐性。另外,由于车辆寿命的延伸,电子设备也要求长寿命化。
参照图7,对实施例4的电子控制装置进行说明。
如图7所示,电子控制装置(ECU)70具备变换部71、控制部72、输出部73,具备将来自传感器部74的信号传送到马达部75的功能。电子控制装置70的控制部72搭载有实施例1的半导体装置。
在此,发动机控制单元(engine control unit、ECU)是使用电辅助装置进行发动机的运转控制时将它们综合控制的微控制器(微电脑)。
车载用途的电子控制装置70暴露于环境温度,反复高温环境和低温环境。即使在车室内,在发动机停止中,达到50℃左右,另外,在寒冷地区,暴露于冰点下。在设置于发动机舱内的电子控制装置70中,环境温度最高为100℃以上。
参照图8,对搭载于电子控制装置70的实施例1的半导体装置被置于反复高温和低温的环境时的状态进行说明。
主要使用有机基板的配线基板1和搭载于配线基板1的半导体封装体2各自的线膨胀系数不同。因此,在反复高温和低温的环境下,各自的翘曲量不同,在半导体封装体2的最外周角部的焊锡接合部5a作用大的负荷。因此,最外周角部的焊锡接合部5a的连接长度长对于焊锡接合部5a的裂纹进展及直至断裂的热疲劳寿命是有效的。
符号说明
1—配线基板,2—半导体封装体,3—电极,4a—最外周角部电极,4b—最外周角部以外的电极,5a—最外周角部的焊锡接合部,5b—最外周角部以外的焊锡接合部,70—电子控制装置,71—变换部,72—控制部,73—输出部,74—传感器部,75—马达部。

Claims (12)

1.一种电子控制装置,其具备控制马达的控制部,
上述电子控制装置的特征在于,
上述控制部具有半导体装置,
上述半导体装置具有:
半导体封装体,其具有多个第一电极;
配线基板,其具有以与上述多个第一电极分别对应的方式配置的多个第二电极;以及
焊锡接合部,其连接上述第一电极和上述第二电极,
配置于上述配线基板的最外周角部的上述第二电极的前端部位于比上述半导体封装体的外周端部靠外侧。
2.根据权利要求1所述的电子控制装置,其特征在于,
配置于上述配线基板的上述最外周角部的上述焊锡接合部的前端部位于比上述半导体封装体的外周端部靠外侧。
3.根据权利要求2所述的电子控制装置,其特征在于,
配置于上述配线基板的最外周角部的上述第二电极的面积比配置于上述半导体封装体的最外周角部的上述第一电极的面积大。
4.根据权利要求3所述的电子控制装置,其特征在于,
配置于上述配线基板的最外周角部的上述第二电极的面积比配置于上述配线基板的最外周角部以外的上述第二电极的面积大。
5.根据权利要求4所述的电子控制装置,其特征在于,
配置于上述配线基板的最外周角部的上述第二电极的中心与配置于上述半导体封装体的最外周角部的上述第一电极的中心相比,向从上述半导体封装体的中心朝向外侧的方向偏移。
6.根据权利要求1所述的电子控制装置,其特征在于,
配置于上述配线基板的最外周角部的上述焊锡接合部的形状与配置于上述配线基板的最外周角部以外的上述焊锡接合部的形状不同。
7.根据权利要求6所述的电子控制装置,其特征在于,
配置于上述配线基板的最外周角部的上述焊锡接合部具有延伸到比上述半导体封装体的外周端部靠外侧的倒角形状。
8.根据权利要求1所述的电子控制装置,其特征在于,
配置于上述配线基板的最外周角部的上述第二电极配置于上述最外周角部的对角线上。
9.根据权利要求1所述的电子控制装置,其特征在于,
配置于上述配线基板的最外周角部的上述第二电极引出到上述半导体封装体的对置的边的垂直方向的延长线上。
10.根据权利要求1所述的电子控制装置,其特征在于,
配置于上述配线基板的最外周角部的上述焊锡接合部的组成与配置于上述配线基板的最外周角部以外的上述焊锡接合部的组成不同,
配置于上述配线基板的最外周角部的上述焊锡接合部含有Bi、In以及Sb中的至少一个元素,
配置于上述最外周角部的上述焊锡接合部的上述元素的浓度比配置于上述配线基板的最外周角部以外的上述焊锡接合部含有的Bi、In、Sb中的至少一个元素的浓度高。
11.根据权利要求1所述的电子控制装置,其特征在于,
上述控制部的上述半导体装置搭载于面向车载的电子设备。
12.根据权利要求11所述的电子控制装置,其特征在于,
上述配线基板和上述半导体封装体的线膨胀系数分别不同,
在上述面向车载的电子设备中,在反复高温和低温的环境下,上述配线基板和上述半导体封装体的翘曲量分别不同,
在配置于上述配线基板的最外周角部的上述焊锡接合部作用的负荷比在配置于上述配线基板的最外周角部以外的上述焊锡接合部作用的负荷大。
CN201880065755.6A 2017-10-10 2018-09-11 电子控制装置 Pending CN111194478A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2017196587A JP6955954B2 (ja) 2017-10-10 2017-10-10 電子制御装置
JP2017-196587 2017-10-10
PCT/JP2018/033563 WO2019073734A1 (ja) 2017-10-10 2018-09-11 電子制御装置

Publications (1)

Publication Number Publication Date
CN111194478A true CN111194478A (zh) 2020-05-22

Family

ID=66100510

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880065755.6A Pending CN111194478A (zh) 2017-10-10 2018-09-11 电子控制装置

Country Status (4)

Country Link
US (1) US20200243470A1 (zh)
JP (1) JP6955954B2 (zh)
CN (1) CN111194478A (zh)
WO (1) WO2019073734A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2021125546A (ja) * 2020-02-05 2021-08-30 富士電機株式会社 半導体モジュール及び半導体モジュールの製造方法
CN212303653U (zh) 2020-03-26 2021-01-05 北京小米移动软件有限公司 芯片、电路板、电路板组件及电子设备
JP2022011066A (ja) * 2020-06-29 2022-01-17 日本電気株式会社 量子デバイス

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11121525A (ja) * 1997-10-20 1999-04-30 Sony Corp 半導体装置
JP2000195982A (ja) * 1998-12-28 2000-07-14 Pfu Ltd 小型半導体装置および小型半導体装置の実装構造ならびにセラミック基板の製造方法
JP2007251053A (ja) * 2006-03-17 2007-09-27 Fujitsu Ltd 半導体装置の実装構造及びその実装構造の製造方法
WO2015072294A1 (ja) * 2013-11-12 2015-05-21 日立オートモティブシステムズ株式会社 車載電子制御装置の放熱構造
JP2015176940A (ja) * 2014-03-14 2015-10-05 日立オートモティブシステムズ株式会社 半導体装置の実装構造

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3351355B2 (ja) * 1998-09-29 2002-11-25 株式会社デンソー 電子部品の実装構造
JP2003197813A (ja) * 2001-12-28 2003-07-11 Mitsubishi Electric Corp 電子装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11121525A (ja) * 1997-10-20 1999-04-30 Sony Corp 半導体装置
JP2000195982A (ja) * 1998-12-28 2000-07-14 Pfu Ltd 小型半導体装置および小型半導体装置の実装構造ならびにセラミック基板の製造方法
JP2007251053A (ja) * 2006-03-17 2007-09-27 Fujitsu Ltd 半導体装置の実装構造及びその実装構造の製造方法
WO2015072294A1 (ja) * 2013-11-12 2015-05-21 日立オートモティブシステムズ株式会社 車載電子制御装置の放熱構造
JP2015176940A (ja) * 2014-03-14 2015-10-05 日立オートモティブシステムズ株式会社 半導体装置の実装構造

Also Published As

Publication number Publication date
WO2019073734A1 (ja) 2019-04-18
JP6955954B2 (ja) 2021-10-27
JP2019071345A (ja) 2019-05-09
US20200243470A1 (en) 2020-07-30

Similar Documents

Publication Publication Date Title
KR101332861B1 (ko) 아이씨 패키지 및 그 제조방법
US6800945B2 (en) Multi-chip semiconductor device with specific chip arrangement
US7365426B2 (en) Semiconductor device
CN111194478A (zh) 电子控制装置
US20030080437A1 (en) Electronic assembly with filled no-flow underfill and methods of manufacture
US20020185744A1 (en) Semiconductor device and a method of manufacturing the same
US6238948B1 (en) Controlled collapse chip connection (C4) integrated circuit package that has a fillet which seals an underfill material
US6331446B1 (en) Process for underfilling a controlled collapse chip connection (C4) integrated circuit package with an underfill material that is heated to a partial gel state
US20020014688A1 (en) Controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials
JP2000022034A (ja) 電子回路装置の接続構造
JP2010283215A (ja) 電子装置および電子装置を製造する方法
US8368215B2 (en) Semiconductor device and method of manufacturing the same
KR101021821B1 (ko) 반도체 디바이스
WO2000052751A1 (en) A process line for underfilling a controlled collapse chip connection (c4) integrated circuit package
WO2004030075A1 (ja) 半導体装置の製造方法
JP6272674B2 (ja) ボンディングワイヤ、接続部構造、並びに半導体装置およびその製造方法
JP2004047758A (ja) 半導体装置
JP3659872B2 (ja) 半導体装置
WO2024018729A1 (ja) 半導体装置
US11189557B2 (en) Hybrid package
JP2011159840A (ja) 電子部品の実装接続構造
US20160029486A1 (en) Solder joint structure and electronic component module including the same
JP2019508908A (ja) はんだボールを備えたパッケージング構造、及びパッケージング構造を製造する方法
CN115513158A (zh) 具有带有多个焊球材料的球栅阵列的半导体装置封装
JPH08340060A (ja) 半導体用パッケージおよび半導体実装モジュール

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: Ibaraki

Applicant after: Hitachi astemo Co.,Ltd.

Address before: Ibaraki

Applicant before: HITACHI AUTOMOTIVE SYSTEMS, Ltd.

CB02 Change of applicant information
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20200522

WD01 Invention patent application deemed withdrawn after publication