CN1111826A - 共栅极结构的晶体管 - Google Patents

共栅极结构的晶体管 Download PDF

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Publication number
CN1111826A
CN1111826A CN95100427A CN95100427A CN1111826A CN 1111826 A CN1111826 A CN 1111826A CN 95100427 A CN95100427 A CN 95100427A CN 95100427 A CN95100427 A CN 95100427A CN 1111826 A CN1111826 A CN 1111826A
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region
grid
semiconductor substrate
common gate
gate insulator
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CN95100427A
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黄�俊
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SK Hynix Inc
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Hyundai Electronics Industries Co Ltd
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Publication of CN1111826A publication Critical patent/CN1111826A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)

Abstract

本发明涉及一种晶体管结构，更详细地说，涉及 共栅极结构的晶体管，它包括两个晶体管共同夹着一 个在同一层中形成的栅极，从而改进了布局结构并使 工艺简单。

Description

本发明涉及一种晶体管结构，特别是涉及一种共栅极结构的晶体管，该结构包括其间具有一个栅极的两个重叠的晶体管。
为了更好理解本发明的背景技术，将结合图1和图2对常规的共栅极晶体管作以下说明。
图1是一种采用常规共栅极的SRAM单元电路。图2说明图1的SRAM单元电路的共栅极结构的晶体管制造工艺。如图2所示，首先形成一个NMOS薄膜晶体管。对于此NMOS薄膜晶体管而言，硅衬底21备有场氧化层22，接着形成NMOS栅极23的图形。在形成此NMOS薄膜晶体管之后，淀积一氮化物的绝缘层24。随后，淀积用做PMOS薄膜晶体管栅极的多晶硅，该多晶硅覆盖在所得到的结构上，再经光刻，而形成PMOS栅极25的图形。接着以栅极氧化层26盖在PMOS栅极25上，又淀积一多晶硅层27，以使其形成沟道和源/漏区。
由于PMOS薄膜晶体管和NMOS薄膜晶体管形成在不同的薄层上，由上述常规工艺制造的晶体管结构，从图2可以明显看出，在布局上是极差的，这个缺点造成难以进行后续工艺，诸如曝光、蚀刻等。因此，尽管此常规方法使制造工艺变得更复杂，而且集成度方面还受到限制。
所以，本发明的目的是为了解决现有技术中上述问题，提供一种改进了布局结构和使工艺简单的共栅极结构的晶体管。
根据本发明，通过采用一种共栅极结构的晶体管，可以达到本发明上述目的。共栅极晶体管结构包括：一第1半导体衬底;在第1半导体衬底的各预定区域形成第1源区和第1漏区;除此第1源区和第1漏区外，还在半导体衬底区域上形成第1栅极绝缘区;在此第1栅极绝缘区上形成栅极;在此栅极上再形成第2栅极绝缘区;在由第1栅极绝缘区、栅极与第2栅极绝缘区提供的侧壁上以及在第1源区与第1漏区的顶面上形成的绝缘区;覆盖此第2栅极绝缘区和绝缘区上形成的第2半导体衬底;以及在此第2半导体衬底中形成的第二源区和第2漏区，所述的第2源区与绝缘区和第1源区对齐，所述的第2漏区与绝缘区和第1漏区对齐。
参照附图，通过详细地描述本发明的最佳实施例，本发明的上述目的和其它优点将变得更加清楚。
附图简要说明：
图1是采用共同栅极的SRAM单元电路图;
图2是一种常规共栅极结构的晶体管示意剖面图;
图3是根据本发明的一种共栅极晶体管结构的示意剖面图;
图4A是图3共栅极晶体管结构的电路图;和
图4B是采用多个本发明的共栅极晶体管结构的电路图。
参照附图，其中相同的标号分别用于相同或相应的零件，以便更好地理解本发明的最佳实施例。
参照图3，图3中所示的根据本发明一种共栅极结构的晶体管，包括两个共同夹着一个栅极的晶体管。第一半导体衬底31在各自预定区域具有第1源区38和第1漏区38′。同样，第2半导体衬底37在各自的预定区域也具有第2源区388和第2漏区388′。本发明的共栅极结构的晶体管是这样实现的，其包括在第1栅极绝缘区35顶面上和用第2栅极绝缘区366与在由栅极33提供的侧壁上的绝缘区32覆盖的栅极33、第1栅极绝缘区35以及第2栅极绝缘区366形成的栅极结构，该结构被夹在第1半导体衬底31和第2半导体衬底37之间，用这样的一种方式，可以使第1源区38和第1漏区38′，通过绝缘区32，分别与第2源区388和第2漏区388′面对着，以及可使第1栅极绝缘区35和第二栅极绝缘区366与除源和漏区以外的第1和第2半导体衬底区域直接面对着。
图4A是对应于图3的共栅极晶体管的电路图，而图4B则是表示采用多个共栅极晶体管结构应用的电路图。
如上文所述，本发明是共栅极结构的晶体管，其中两个晶体管共同夹着同一层形成的一个栅极，因此不仅改进了布局结构并使工艺简化。
通过上述描述使本发明的目的、特征、优点将更清楚。但上述实施例的改变和修改都不会脱离如权利要求所述的本发明的构思与范围。

Claims (1)

1、一种共栅极结构的晶体管，包括：
一第1半导体衬底；
一第1源区和一第1漏区，它被形成在此第1半导体衬底的各自预定区域；
一第1栅极绝缘区，它形成在除第1源区和第1漏区外的半导体衬底区域上；
一栅极，它形成在所述第1栅极绝缘区上；
一第2栅极绝缘区，它形成在所述栅极上；
一绝缘区，它形成在由所述第1栅极绝缘区、栅极以及所述第2栅极绝缘区提供的侧壁上和在所述第1源区和第1漏区顶面上；
一第2半导体衬底，它被覆盖在所述第2栅极绝缘区和绝缘区上形成；以及
一第2源区和一第2漏区，它形成在第2半导体衬底内，所述第2源区与绝缘区和第1源区对齐，所述第2漏区与所述绝缘区第1漏区对齐。
CN95100427A 1994-02-28 1995-02-27 共栅极结构的晶体管 Pending CN1111826A (zh)

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KR1994-3877 1994-02-28
KR1019940003877A KR950026008A (ko) 1994-02-28 1994-02-28 게이트전극 공유 트랜지스터

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1079996C (zh) * 1995-12-02 2002-02-27 Lg半导体株式会社 高压金属氧化物硅场效应晶体管结构
CN105438566A (zh) * 2015-12-17 2016-03-30 温州市国泰轻工机械有限公司 一种落杯结构

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1079996C (zh) * 1995-12-02 2002-02-27 Lg半导体株式会社 高压金属氧化物硅场效应晶体管结构
CN105438566A (zh) * 2015-12-17 2016-03-30 温州市国泰轻工机械有限公司 一种落杯结构

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