CN111106171B - AlN势垒层、AlN/GaN HEMT外延结构及其生长方法 - Google Patents

AlN势垒层、AlN/GaN HEMT外延结构及其生长方法 Download PDF

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CN111106171B
CN111106171B CN201911405708.4A CN201911405708A CN111106171B CN 111106171 B CN111106171 B CN 111106171B CN 201911405708 A CN201911405708 A CN 201911405708A CN 111106171 B CN111106171 B CN 111106171B
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付羿
周名兵
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Jingneng Optoelectronics Co ltd
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    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

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Abstract

本发明提供了一种AlN势垒层、AlN/GaN HEMT外延结构及其生长方法，其中，AlN/GaN HEMT外延结构从下到上依次包括：生长衬底、位错过滤层、应力控制层、GaN薄层及AlN势垒层，其中，所述AlN势垒层中掺杂饵。由于铒的原子半径比Al大，稀土元素铒掺入AlN势垒层后，会在AlN材料中产生晶格畸变从而提高AlN势垒层的压电性能；另外，由于铒的电负性小，增加了AlN势垒层中的离子键比例，进一步增强了稀土掺杂AlN势垒层的压电系数和极化效应，使得掺铒的AlN势垒层厚度减薄后仍然可以获得高面密度的二维电子气。

Description

AlN势垒层、AlN/GaN HEMT外延结构及其生长方法
技术领域
本发明涉及半导体技术领域，尤其是一种AlN势垒层、AlN/GaN HEMT外延结构及其生长方法。
背景技术
在应用于太兹范围的HEMT结构中，为了增强栅控能力以抑制短沟道效应，可以采用厚度在5nm~10nm的AlN势垒层，使得HEMT的栅极位置非常靠近二维电子气沟道，最大化栅极和二维电子气之间的静电耦合。但是，AlN和GaN之间存在2.4%的晶格失配，在GaN沟道层上，即使5nm厚度的薄AlN势垒层中也存在很大的张应力，容易产生密集微裂纹。进一步减薄AlN势垒层虽然可以减少张应力防止微裂纹的产生，但同时降低了二维电子气面密度，导致HEMT器件的功率密度下降。
发明内容
为了克服以上不足，本发明提供了一种AlN势垒层、AlN/GaN HEMT外延结构及其生长方法，有效解决现有技术中AlN势垒层易产生密集微裂纹的技术问题。
本发明提供的技术方案为：
一种AlN/GaN HEMT外延结构中的AlN势垒层，所述AlN势垒层中掺杂铒。
进一步优选地，所述AlN势垒层的厚度为1~15nm。
进一步优选地，在所述AlN势垒层中，铒的掺杂浓度为1~2E20。
本发明还提供了一种AlN/GaN HEMT外延结构，从下到上依次包括：生长衬底、位错过滤层、应力控制层、GaN薄层及上述AlN势垒层。
本发明还提供了一种AlN/GaN HEMT外延结构生长方法，应用于上述AlN/GaN HEMT外延结构，所述AlN/GaN HEMT外延结构生长方法包括：
提供生长衬底；
于所述生长衬底表面依次生长错过滤层、应力控制层及GaN薄层；
于所述GaN薄层表面生长掺杂铒的AlN势垒层。
进一步优选地，所述AlN势垒层的厚度为1~15nm。
在本发明提供的AlN势垒层、AlN/GaN HEMT外延结构及其生长方法中，由于铒的原子半径比Al大，稀土元素铒掺入AlN势垒层后，会在AlN材料中产生晶格畸变从而提高AlN势垒层的压电性能；另外，由于铒的电负性小，增加了AlN势垒层中的离子键比例，进一步增强了稀土掺杂AlN势垒层的压电系数和极化效应，使得掺铒的AlN势垒层厚度减薄后仍然可以获得高面密度的二维电子气。
附图说明
图1为本发明中HEMT外延结构示意图。
附图标记：
101-生长衬底，102-位错过滤层/应力控制层，103-GaN薄层，104-AlN势垒层。
实施方式
为了更清楚地说明本发明实施案例或现有技术中的技术方案，下面将对照附图说明本发明的具体实施方式。显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图，并获得其他的实施方式。
针对现有技术中AlN势垒层中容易产生密集微裂纹的问题，本发明提供了一种AlN/GaN HEMT外延结构中的AlN势垒层，该AlN势垒层中掺杂铒，铒的掺杂浓度为1~2E20，且该AlN势垒层的厚度为1~15nm。
基于此，本发明还提供了一种AlN/GaN HEMT外延结构，如图1所示，该AlN/GaNHEMT外延结构从下到上依次包括：生长衬底101、位错过滤层/应力控制层102、GaN薄层103及AlN势垒层104，其中，位错过滤层为AlN缓冲层，应力控制层为AlGaN缓冲层，且位错过滤层和应力控制层的总厚度为500~2000nm；GaN薄层的厚度为500~5000nm。生长衬底101可以为硅衬底、蓝宝石衬底、SiC衬底等，且采用金属有机化学气相沉积的方法对该AlGaN/GaNHEMT外延结构进行生长。
在一实例中，生长衬底为硅衬底，生长过程如下：
1）将（111）晶向的硅衬底放入MOCVD反应室中，并于70torr压力、1050℃纯H2的条件下高温烘烤，去除硅衬底表面的氧化物；
2）在70torr压力、1000℃温度下生长一层厚度为800nm的AlN/AlGaN多层缓冲层，其中，AlN层的厚度为200nm，AlGaN层的厚度为600nm；
3）改变气氛至GaN生长条件，在200torr压力、1050℃温度下生长2000nm厚的GaN薄层；
4）改变气氛至至AlN生长条件，在70torr压力、1030℃温度下，同时通入TRIPEr源，进行原位Er掺杂，流量为2000sccm，生长6nm厚的掺ErAlN势垒层，其中，TRIPEr源源温设置为70℃，完成AlN/GaN HEMT外延结构的生长。
在一实例中，生长衬底为蓝宝石衬底，生长过程如下：
1）将蓝宝石PSS衬底放入MOCVD反应室中，并于200torr压力、1050℃温度下进行高温烘烤处理，去除表面氧化物；
2）在500torr压力、550℃温度下生长一层厚度为50nm的GaN缓冲层或AlGaN缓冲层；
3）在500torr压力、1000℃温度的3DGaN条件，生长500nm的岛状3D GaN薄层；
4）在150torr压力、1070℃温度的UGaN生长条件下生长2000nm的非掺杂UGaN层；
5）改变气氛至至AlN生长条件，在70torr压力、1030℃温度下，同时通入TRIPEr源，进行原位Er掺杂，流量为2000sccm，生长6nm厚的掺ErAlN势垒层，其中，TRIPEr源源温设置为70℃，完成AlN/GaN HEMT外延结构的生长。
应当说明的是，上述实施例均可根据需要自由组合。以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。

Claims (7)

1.一种AlN/GaN HEMT外延结构中的AlN势垒层，其特征在于，以GaN为沟道层，所述AlN势垒层中掺杂铒。
2.如权利要求1所述的AlN势垒层，其特征在于，所述AlN势垒层的厚度为1~15nm。
3.如权利要求1或2所述的AlN势垒层，其特征在于，在所述AlN势垒层中，铒的掺杂浓度为1~2E20。
4.一种AlN/GaN HEMT外延结构，其特征在于，从下到上依次包括：生长衬底、位错过滤层、应力控制层、GaN沟道层及如权利要求1或2或3所述的AlN势垒层。
5.一种AlN/GaN HEMT外延结构生长方法，其特征在于，应用于如权利要求4所述的AlN/GaN HEMT外延结构，所述AlN/GaN HEMT外延结构生长方法包括：
提供生长衬底；
于所述生长衬底表面依次生长位错过滤层、应力控制层及GaN沟道层；
于所述GaN沟道层表面生长掺杂铒的AlN势垒层。
6.如权利要求5所述的AlN/GaN HEMT外延结构生长方法，其特征在于，所述AlN势垒层的厚度为1~15nm。
7.如权利要求5或6所述的AlN/GaN HEMT外延结构生长方法，其特征在于，在所述AlN势垒层中，铒的掺杂浓度为1~2E20。
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