CN111095552A - 一种芯片互连结构、芯片及芯片互连方法 - Google Patents

一种芯片互连结构、芯片及芯片互连方法 Download PDF

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CN111095552A
CN111095552A CN201980004314.XA CN201980004314A CN111095552A CN 111095552 A CN111095552 A CN 111095552A CN 201980004314 A CN201980004314 A CN 201980004314A CN 111095552 A CN111095552 A CN 111095552A
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chip
wafer
conductive
conductive member
bonding pad
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CN111095552B (zh
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冷寒剑
吴宝全
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Shenzhen Goodix Technology Co Ltd
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Shenzhen Goodix Technology Co Ltd
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Abstract

本申请提供一种芯片互连结构、芯片及芯片互联方法，芯片互连结构包括第一芯片和至少一个第二芯片，所述第一芯片的转接面和所述第二芯片的转接面相对设置，所述第二芯片和所述第一芯片之间还设有至少一个导电组件，每个所述导电组件包括至少一个导电件，所述导电件连接在所述第二芯片的焊盘与所述第一芯片的焊盘之间，本申请提供的芯片互连结构，能够让两个或两个以上芯片互连并高速通信。

Description

一种芯片互连结构、芯片及芯片互连方法
技术领域
本申请涉及半导体制造技术领域，特别涉及一种芯片互连结构、芯片及芯片互连方法。
背景技术
随着半导体技术的发展，芯片尺寸趋向微型化，科技的发展对芯片的通讯速度要求也随之越来越高。
目前，传统的封装方式依靠打线和电路板基板连接两颗或多颗芯片，从而实现芯片间引脚的互联，完成通信。其中，打线叫压焊，是指使用金属丝利用热压或超声能源，完成微电子器件中固态电路内部互连接线的连接，即芯片与电路或引线框架之间的连接，常见于表面封装工艺。
然而采用上述传统的封装方式实现两颗或多颗芯片间的互连时，由于两颗或多颗芯片互连时的所采用的引线和基板绕线过长，电阻增大，将导致通讯速度会有瓶颈，如通讯速度下降等，如果需维持通讯速度不变，则需增大功率。若直接将两颗或多颗需要互连通信的芯片做在同一片晶圆上，又会大大的增加生产成本。因此，需要一种能够实现高速通信的芯片互连技术。
发明内容
本申请提供一种芯片互连结构、芯片及芯片互连方法，能够让两个或两个以上芯片互连并高速通信。
第一方面，本申请提供一种芯片互连结构，包括第一芯片和至少一个第二芯片，所述第一芯片的转接面和所述第二芯片的转接面相对设置，所述第二芯片和所述第一芯片之间还设有至少一个导电组件，每个所述导电组件包括至少一个导电件，所述导电件连接在所述第二芯片的焊盘与所述第一芯片的焊盘之间。
如上所述的一种芯片互连结构，可选的，每个所述导电组件包括至少两个依次相连的导电件。
如上所述的一种芯片互连结构，可选的，每个所述导电组件包括第一导电件和第二导电件，所述第一导电件的第一端和所述第一芯片的焊盘连接，所述第一导电件的第二端和所述第二导电件的第一端相互对接，所述第二导电件的第二端和所述第二芯片的焊盘连接。
如上所述的一种芯片互连结构，可选的，所述导电件为金属件。
如上所述的一种芯片互连结构，可选的，所述第一导电件和所述第二导电件通过焊接连接，或者，所述第一导电件和所述第二导电件通过导电胶连接。
如上所述的一种芯片互连结构，可选的，所述导电件的材料为铜、银、锡、金以及铝中的一种或两种。
如上所述的一种芯片互连结构，可选的，所述第一导电件和所述第二导电件为能够形成共晶的导电金属。
如上所述的一种芯片互连结构，可选的，所述第一导电件和所述第二导电件通过焊接连接时，所述第一导电件和所述第二导电件的连接处具有共晶层。
如上任一所述的一种芯片互连结构，可选的，所述导电件和所述焊盘为一体式结构。
如上所述的一种芯片互连结构，可选的，所述第一导电件的第二端与所述第二导电件的第一端具有相同的截面形状。
如上所述的一种芯片互连结构，可选的，所述导电件垂直设置在所述第二芯片的焊盘与所述第一芯片的焊盘之间。
如上所述的一种芯片互连结构，可选的，所述导电件为圆柱体或棱柱体。
如上所述的一种芯片互连结构，可选的，所述第二芯片的数量为至少两个，所述第二芯片均设置在所述第一芯片的同一侧，或者所述第二芯片设置在所述第一芯片的正反两侧。
如上任一所述的一种芯片互连结构，可选的，所述第一芯片和所述第二芯片均为单颗裸芯片。
如上所述的一种芯片互连结构，可选的，所述第一芯片包括第一晶圆，所述第一晶圆上设有第一功能层，所述第一功能层上开设有第一焊盘，所述第一功能层上还设有与外部电路互连的第二焊盘；
所述第二芯片包括第二晶圆，所述第二晶圆上设有第二功能层，所述第二功能层上开设有第三焊盘，所述导电件相接在所述第三焊盘和所述第一焊盘之间。
如上所述的一种芯片互连结构，可选的，所述第一芯片还包括第一绝缘层，所述第一绝缘层上设有与所述第一焊盘相连通的第一开窗结构，所述第二芯片还包括第二绝缘层，所述第二绝缘层上设有与所述第三焊盘相连通的第二开窗结构，所述导电件位于所述第一开窗结构和所述第二开窗结构之间。
如上所述的一种芯片互连结构，可选的，所述第一芯片和所述第二芯片之间还设有用于密封所述导电组件的密封层。
如上所述的一种芯片互连结构，可选的，所述第一芯片的焊盘设置在所述第一芯片的转接面，所述第二芯片的焊盘设置在所述第二芯片的转接面，所述第一芯片的焊盘与对应的第二芯片的焊盘通过所述一个导电组件互连。
第二方面，本申请提供一种芯片，其包括如上述任一所述的芯片互连结构。
第三方面，本申请提供一种芯片互连方法，应用于第一芯片和至少一个第二芯片的相互连接，包括：
在第一晶圆和第二晶圆的至少一者上形成导电件，其中，所述第一晶圆为所述第一芯片所在的晶圆，所述第二晶圆为所述第二芯片所在的晶圆，所述导电件的位置与焊盘的位置相对应；
在所述第一晶圆和所述第二晶圆上分别获得所述第一芯片和所述第二芯片；
对接所述第一芯片和所述第二芯片，并利用所述导电件连接所述第一芯片的焊盘与所述第二芯片的焊盘。
如上所述的一种芯片互连方法，可选的，所述在第一晶圆和第二晶圆的至少一者上形成导电件，具体包括：
分别在所述第一晶圆上和所述第二晶圆上形成所述导电件。
如上所述的一种芯片互连方法，可选的，所述导电件的形成方式包括以下一种或几种：溅射、蒸镀、电镀、化镀、贴导电膜。
如上所述的一种芯片互连方法，可选的，所述在所述第一晶圆和所述第二晶圆上分别获得所述第一芯片和所述第二芯片，具体包括：
在所述第一晶圆上切割出所述第一芯片，在所述第二晶圆上切割出所述第二芯片，其中所述第一芯片和所述第二芯片均为单颗裸芯片。
如上所述的一种芯片互连方法，可选的，所述利用所述导电件连接所述第一芯片的焊盘与所述第二芯片的焊盘，具体包括：
通过焊接或压合连接所述第一芯片上的导电件和/或所述第二芯片上的导电件，以使所述导电件连接所述第一芯片的焊盘与所述第二芯片的焊盘。
如上所述的一种芯片互连方法，可选的，所述在第一晶圆和第二晶圆的至少一者上形成导电件的步骤之前，还包括：
若所述第一晶圆和第二晶圆的表面上具有绝缘层，则在所述第一晶圆的绝缘层上开设与所述第一晶圆的焊盘相连通的第一开窗结构，在所述第二晶圆的绝缘层上开设与所述第二晶圆的焊盘相连通的第二开窗结构；
若所述第一晶圆和第二晶圆的表面上没有所述绝缘层，则在所述第一晶圆和第二晶圆的表面上分别形成绝缘层，并在所述第一晶圆的绝缘层上开设与所述第一晶圆的焊盘相连通的第一开窗结构，在所述第二晶圆的绝缘层上开设与所述第二晶圆的焊盘相连通的第二开窗结构。
如上所述的一种芯片互连方法，可选的，所述利用所述导电件连接所述第一芯片焊盘与所述第二芯片的焊盘之后，还包括：
在所述第一芯片和所述第二芯片之间形成密封层。
本申请提供一种芯片互连结构、芯片及互连方法，所述芯片互连结构，包括第一芯片和至少一个第二芯片，所述第一芯片的转接面和所述第二芯片的转接面相对设置，所述第二芯片和所述第一芯片之间还设有至少一个导电组件，每个所述导电组件包括至少一个导电件，所述导电件连接在所述第二芯片的焊盘与所述第一芯片的焊盘之间本申请通过导电件连接在所述第一芯片的焊盘和所述第二芯片的焊盘之间，使得至少两个以上芯片互连时的引线做到最短，从而减少芯片工作时的功率消耗，进而实现芯片的高速通信，因此，本申请提供的一种芯片互连结构、芯片及互连方法实现了两个或两个以上芯片互连且能够实现互连芯片的高速通信的目的。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例一提供的芯片互连结构的结构示意图；
图2是本申请实施例一提供的另一种芯片互连结构的结构示意图；
图3是本申请实施例六提供的互连方法的流程示意图；
图4是本申请实施例六提供的第一晶圆的结构示意图；
图5是本申请实施例六提供的第二晶圆的结构示意图；
图6是本申请实施例六提供的第一芯片的结构示意图；
图7是本申请实施例六提供的第二芯片的结构示意图。
附图标识说明：
1-第一芯片；
101-第一导电件；
102-第一晶圆；
103-第一功能层；
104-第一绝缘层；
105-第一焊盘；
106-第二焊盘；
107-第一开窗结构；
2-第二芯片；
201-第二导电件；
202-第二晶圆；
203-第二功能层；
204-第二绝缘层；
205-第三焊盘；
206-第二开窗结构；
3-密封件；
4-共晶层；
5-导电胶。
具体实施方式
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
目前，传统的封装方式依靠打线和电路板基板连接两颗或多颗芯片，从而实现芯片间引脚的互联，完成通信。随着科技的发展对芯片的通讯速度要求越来越高，因此，需要将芯片间的引脚互连时且不能降低芯片的通讯速度。然而采用上述传统的封装方式实现两颗或多颗芯片间的互连时，将导致通讯速度下降，如果需维持芯片的通讯速度不变，则需增大功率。而若直接将两颗或多颗需要互连通信的芯片做在同一片晶圆上，又会大大的增加生产成本。为了实现芯片互连时，芯片具有正常的通讯速度，本申请提供一种芯片互连结构、芯片及互连方法。
实施例一
图1是本申请实施例一提供的芯片互连结构的结构示意图，图2是本申请实施例一提供的另一种芯片互连结构的结构示意图。
本实施例提供的一种芯片互连结构可以用于半导体技术员领域芯片间的互连尤其适用于需要互连通讯的芯片间的互连，本实施例提供的一种芯片互连结构实现了两个或两个以上芯片互连且能够实现互连芯片的高速通信的目的，解决了现有技术中芯片互连时通讯速度下降的技术问题。
如图1和图2所示，芯片互连结构包括：第一芯片1和至少一个第二芯片2，第一芯片1的转接面和第二芯片2的转接面相对设置，第二芯片2和第一芯片1之间还设有至少一个导电组件，每个导电组件包括至少一个导电件，导电件连接在第二芯片2的焊盘与第一芯片1的焊盘之间。
其中，本实施例中，第一芯片1和第二芯片2可以是任何需要互连通信的芯片。本实施例第一芯片1和第二芯片2可以为微控制单元(Microcontroller Unit，简称MCU)芯片和Flash芯片，第一芯片1和第二芯片2也可以均为存储类芯片，如XROM芯片，即本实施例中对于第一芯片1和第二芯片2并不做具体的限定，第一芯片1和第二芯片2可以为逻辑芯片、存储芯片、图像芯片或者控制芯片，在本实施例中，只需保证第一芯片1和第二芯片2为任何需要互连通信的芯片即可。
其中，本实施例中，第一芯片1的转接面为第一芯片1上设有焊盘的一面，第二芯片2的转接面为第二芯片2上设有焊盘的一面，本实施例中，第一芯片1的转接面和第二芯片2的转接面相对设置，即第一芯片1和第二芯片2互连时，第二芯片2反向倒接在第一芯片1上，以使第一芯片1的焊盘和第二芯片2的焊盘相对设置，便于尽可能的缩短第一芯片1和第二芯片2互连时的引线。
需要说明的是，本实施例中，如图1和图3所示，由于需要将至少一个第二芯片2与第一芯片1互连，因此，第一芯片1在至少一个第二芯片2上的投影面积需大于等于第二芯片2的总面积，即当两个或两个以上第二芯片2与第一芯片1互连时，第一芯片1在第二芯片2上的投影面积需大于等于与第一芯片1互连的所有第二芯片2的总面积。在本实施例中，对于第一芯片1和第二芯片2的面积大小，在本实施例中并不做进一步限定。
其中，本实施例中，如图1所示，导电件可以为导电金属，在本实施例中，每个导电组件包括至少一个导电件，第一芯片1和第二芯片2之间设置至少一个导电组件，也就是说，第一芯片1和第二芯片2之间至少包括一个或多个导电件，通过将导电件连接第二芯片2的焊盘与第一芯片1的焊盘之间，能够将第一芯片1和第二芯片2电导通，从而实现第一芯片1和第二芯片2的通讯，且通过导电件的设置相较于现有技术中通过依靠打线和电路板基板连接两颗或多颗芯片实现芯片间的引脚的互连的方式，无需通过打线和基板绕线，不仅能够大大缩短第一芯片1和第二芯片2互连时的引线，从而减小芯片工作时的功率消耗，实现芯片的高速通讯，而且本实施例互连结构简单易操作，无需引入复杂工艺，相较于现有技术中直接将两颗或多颗需要互连通信的芯片做在同一片晶圆上，能够大大降低生产成本。
其中，本实施例中，导电件和焊盘为一体式结构，本实施例中，导电件可以与第一芯片1的焊盘为一体化结构，通过导电件与第二芯片2的焊盘连接，导电件可以与第二芯片2的焊盘为一体化结构，通过导电件与第一芯片1的焊盘连接，即，本实施例中，不管采用何种方式，均能够实现第一芯片1和第二芯片2的互连通信。
需要说明的是，本实施例中，第一芯片1和第二芯片2上的焊盘可以为金属焊盘或者其他能够实现第一芯片1和第二芯片2表面贴装装配的焊盘，该焊盘为现有技术，本实施例具体采用何种材料的焊盘，在本实施例中，并不做进一步限定。
需要说明的是，本实施例中，第一芯片1和第二芯片2分别所在的晶圆，该晶圆在出厂之前，其上均设有焊盘，并且在晶圆的表面自带有绝缘层，在该自带的绝缘层可达到现有技术中理论需满足的绝缘标准和防护标准时，本申请无需再加工出第一芯片1和第二芯片2的绝缘层。
需要说明的是，本实施例中，如图1所示，导电件可以为一体式结构，也可以为分体式结构，即，本实施例当导电件为一体式结构时，导电件位于在第一芯片1或第二芯片2的转接面上，当导电件为分体式结构时，导电件的第一部分位于第一芯片1上，导电件的第二部分位于第二芯片2上，第一芯片1和第二芯片2互连时，导电件的第一部分和导电件的第二部分相接。在本实施例中，只需保证导电件连接在第二芯片2的焊盘与第一芯片1的焊盘之间，以实现第一芯片1和第二芯片2的互连通信即可，本实施例对于导电件的结构并不作进一步限定。
其中，本实施例中，如图1所示，为了尽可能的将第一芯片1和第二芯片2互连时的引线做到最短，导电件垂直设置在第二芯片2的焊盘与第一芯片1的焊盘之间，以减少第一芯片1和第二芯片2工作时的功率消耗，实现第一芯片1和第二芯片2的高速通信。
其中，本实施例中，导电件可以为圆柱体，也可以为棱柱体或其他结构，即本实施例中，导电件包括但不见限于圆柱体或棱柱体。
其中，本实施例中，第一芯片1的焊盘设置在第一芯片1的转接面，第二芯片2的焊盘设置在第二芯片2的转接面，第一芯片1的焊盘与对应的第二芯片2的焊盘通过一个导电组件互连。
其中，本实施例中，第一芯片1和第二芯片2均为单颗裸芯片。
其中，本实施例中，裸芯片为芯片电路在晶圆上完成制作并从晶圆上切割下来但未进行完整封装的芯片，也就是说，本实施例互连的第一芯片1和第二芯片2均为单颗的裸芯片。
具体的，相较于现有技术中的倒装芯片，即在芯片的焊盘上沉积锡铅球，然后将芯片翻转加热利用熔融的锡铅球与陶瓷基板结合形成倒装芯片。本实施例是通过导电件将两个或两个以上的芯片进行互连，而已知的倒装芯片是通过焊料将芯片连接在陶瓷基板上，因此，本实施例的芯片互连结构与倒装芯片的结构主体不同，本实施例中是将互连的单颗裸芯片相对设置并通过导电件连接，通过导电件垂直连接在互连的裸芯片之间能够将芯片互连时的引线做到最短，以减少芯片互连时的引线长度，进而实现芯片的高速通信。
具体的，现有技术中的芯片对整片晶圆的对焊工艺(简称：CoW工艺),CoW工艺是将一个经过切割的单颗裸芯片通过倒装芯片的方式倒焊在晶圆上未经切割的芯片上，最后通过点胶实现芯片与整片晶圆的对焊，其中，CoW工艺中的晶圆未经切割，所以采用CoW工艺实现芯片与整片晶圆的对焊时，必须需要引入专有设备和专有材料，如晶圆级(即waferlevel)点胶设备和热压缩非导电糊胶(简称：TCNCP)材料，其中，TCNCP也叫非导电热固胶。由于wafer level点胶设备和TCNCP的引入，将大大增加芯片与整片晶圆互连时的成本。
与现有技术中的CoW工艺相比，由于本实施例中的芯片互连结构的作用主体为两个或多个单颗的裸芯片，其中，每颗裸芯片分别为单独的功能芯片，因此，本实施例第一芯片1和第二芯片2互连时采用国内的常规设备即可完成实现芯片互连，且能够实现互连芯片的高通信速度的目的，无需从外国引入wafer level点胶设备和TCNCP。因此，本实施例芯片互连结构具有较低的生产成本。需要说明的是，本实施例中，常规设备包括但不仅限于芯片级点胶设备，还包括芯片级的其他封装设备。相较于现有技术中的采用CoW工艺实现芯片与整片晶圆互连的方式，由于本实施例的互连的主体为两个或多个单颗的裸芯片，采用芯片级的点胶设备、以及芯片级的其他封装设备就可实现芯片的互连，因此本实施例芯片互连结构相较于采用CoW工艺制作的芯片与晶圆的互连结构具有较低的生产成本。
因此，本实施例提供一种芯片互连结构，该芯片互连结构包括第一芯片1和至少一个第二芯片2，第一芯片1的转接面和第二芯片2的转接面相对设置，第二芯片2和第一芯片1之间还设有至少一个导电组件，每个导电组件包括至少一个导电件，导电件连接在第二芯片2的焊盘与第一芯片1的焊盘之间本申请通过导电件连接在第一芯片1的焊盘和第二芯片2的焊盘之间，使得至少两个以上芯片互连时的引线做到最短，从而减少芯片工作时的功率消耗，进而实现芯片的高速通信，因此，本申请提供的一种芯片互连结构、芯片及互连方法实现了两个或两个以上芯片互连且能够实现互连芯片的高速通信的目的。
实施例二
进一步的，在上述实施例的基础上，本实施例中，如图1和图3所示，每个导电组件包括至少两个依次相连的导电件，通过两个或两个依次相连的导电件将第一芯片1的焊盘和第二芯片2的焊盘相连接。
其中，本实施例中，如图1和图3所示，每个导电组件包括第一导电件101和第二导电件201，第一导电件101的第一端和第一芯片1的焊盘连接，第一导电件101的第二端和第二导电件201的第一端相互对接，第二导电件201的第二端和第二芯片2的焊盘连接。
需要说明的是，第一导电件101连接在第一芯片1的焊盘上且与第一芯片1的焊盘为一体化结构，第二导电件201连接在第二芯片2的焊盘上且与第二芯片2的焊盘为一体化结构。其中，本实施例相接的第一导电件101和第二导电件201位于同一中轴线上，以缩短第一芯片1和第二芯片2互连时的引线，减小第一芯片1和第二芯片2工作时的功率消耗，实现第一芯片1和第二芯片2的高速通信。
其中，本实施例中，导电件的长宽高均为微米级别，优选1-100um。
其中，本实施例中，导电件为圆柱体时，导电柱的直径优选45um，高度优选60um。
其中，本实施例中，导电件为金属件，第一导电件101和第二导电件201可以通过焊接连接。其中焊接方式包括热压焊、回流焊或超声焊等，本实施例根据导电件所具体采用的材料来选择与该导电件的材料相适配的焊接方式。
其中，本实施例中，导电件的材料为铜、银、锡、金以及铝中的一种或两种。即本实施例，第一导电件101和第二导电件201的材料可以选用相同的材料，也可以选用不同的材料。
具体的，在本实施例中，当第一导电件101和第二导电件201的材料相同时，如第一导电件101和第二导电件201均为锡时，第一导电件101的第二端和第二导电件201的第一端靠锡和锡的互融对焊相连接，优选回流焊，当第一导电件101和第二导电件201选用铜、银、锡、金以及铝的两种材料时，根据选用的材料采取一定的焊接方法。
具体的，本实施例中，第一导电件101和第二导电件201可为铜、银、锡、金以及铝中任意两种金属的组合，其中，第一导电件101和第二导电件201还可以为铜、银、锡、金以及铝中任意两种能够形成共晶的导电金属。
需要说明的是，本实施例，第一导电件101和第二导电件201为能够形成共晶的导电金属，第一导电件101和第二导电件201通过焊接使第一导电件101和第二导电件201电连接时，在第一导电件101和第二导电件201的连接处具有共晶层4。具体的，本实施例第一导电件101和第二导电件201为能够形成共晶的导电金属时，第一导电件101和第二导电件201可以采用锡和银、锡和金、金和铜、金和铝、以及其他能够形成共晶的导电金属组合。本实施例中，当第一导电件101和第二导电件201可以采用锡和银时，优选采用回流焊焊接，当第一导电件101和第二导电件201可以采用锡和金或者金和铜时，优选采用电压焊焊接，当第一导电件101和第二导电件201可以采用金和铝时，优选采用超声焊焊接，即本实施例中，对于第一导电件101和第二导电件201的材料以及焊接方式并不做进一步限制。
或者，如图2所示，第一导电件101和第二导电件201还可以通过导电胶5连接。具体的，本实施例中，可以通过在第一导电件101的第二端和第二导电件201的第一端之间设置导电胶5，通过导电胶5来实现第一导电件101和第二导电件201的电连接。具体的，本实施例中，可以通过在第一导电件101和第二导电件201之间设置整片的导电胶5来实现第一导电件101和第二导电件201的电连接，也可以通过在第一导电件101的第二端或者第二导电件201的第一端逐个设置单个的导电胶5来实现第一导电件101和第二导电件201的电连接。其中，当第一导电件101和第二导电件201通过导电胶5连接时，第一导电件101和第二导电件201可以为铜、银、锡、金以及铝中的一种或两种。
具体的，本实施例中，当通过在第一导电件101和第二导电件201之间设置整片的导电胶5来实现第一导电件101和第二导电件201的电连接时，第一导电件101和第二导电件201之间整片的导电胶5在实现第一导电件101和第二导电件201电连接的同时，整片的导电胶5还形成了本申请实施例中位于第一芯片1和第二芯片2之间的密封层3。其中，本实施例中整片的导电胶5可以采用具有定向导电功能的定向导电胶，如异方性导电胶膜(Anisotropic Conductive Film，简称：ACF)，通过压合将第一导电件101和第二导电件201之间ACF中的导电颗粒挤压压迫，以实现第一芯片1和第二芯片2的导电互通。
具体的，本实施例中，当通过在第一导电件101的第二端或者第二导电件201的第一端逐个设置单个的导电胶5来实现第一导电件101和第二导电件201的电连接时，第一芯片1和第二芯片2之间的导电胶为单独的导电胶5，其数量与第一导电件101或第二导电件201的数量相对且一一对应。其中，本实施例中单独的导电胶5包括但不仅限于含银颗粒的导电胶，如导电银胶，通过导电银胶实现第一芯片1和第二芯片2的导电互通。
需要说明的是，当第一导电件101的第二端或者第二导电件201的第一端通过逐个设置单个的导电胶5来实现第一导电件101和第二导电件201的电连接时，第一芯片1和第二芯片2之间仍需额外设置本申请实施例中的密封层3。
其中，本实施例中，第一导电件101的第二端与第二导电件201的第一端具有相同的投影形状，该投影形状为第一导电件101在第一芯片1上的投影形状，或者第二导电件201在第二芯片2上的投影形状，该投影形状可以为圆形、椭圆形或者多边形。
实施例三
进一步的，在上述实施例的基础上，本实施例中，如图2所示，第二芯片2的数量为至少两个，第二芯片2均设置在第一芯片1的同一侧，或者第二芯片2设置在第一芯片1的正反两侧。
需要说明的是，本实施例中，如图2所示，当第二芯片2的数量为两个或两个以上时，第二芯片2可以设置在第一芯片1的同一侧，且所有第二芯片2的转接面与第一芯片1的转接面相对设置，通过导电件相接在第一芯片1的焊盘和第二芯片2的焊盘之间；第二芯片2可以设置在第一芯片1的正反两侧，即第二芯片2可以均布在第一芯片1的正反两侧，此时，第一芯片1的正反两侧均设有转接面，且第一芯片1的转接面上均设有焊盘，第一芯片1位于第二芯片2之间，且第一芯片1的转接面与第二芯片2的转接面相对设置，通过相接在第一芯片1的焊盘和第二芯片2的焊盘之间，实现第一芯片1和第二芯片2的互连通信。
实施例四
进一步的，在上述实施例的基础上，如图1所示，本实施例中，第一芯片1包括第一晶圆102，第一晶圆102上设有第一功能层103，第一功能层103上开设有第一焊盘105，可用于第一芯片和其他芯片互连，第一功能层103上还设有与其他外部电路互连的第二焊盘106；第一焊盘105的数量可以根据第一芯片的类型、功能等属性不同而不同，比如可以有多个第一焊盘105。类似的，第二焊盘106的数量也可以是多个。本申请中晶圆可以是硅晶片或者其他半导体晶片。
需要说明的是，本实施例中，为了便于通过第二焊盘106将其他外部电路与第一芯片1互连，因此，第二焊盘106位于第一焊盘105的外侧。其中，第二焊盘106可以通过现有技术中的传统打线方式与其他外部电路连接，也可以通过本申请中导电件的方式与其他外部电路连接，在本实施例中，对于第二焊盘106与其他外部电路连接的方式并不做进一步限定。
其中，本实施例中，第二芯片2包括第二晶圆202，第二晶圆202上设有第二功能层203，第二功能层203上开设有第三焊盘205，导电件相接在第三焊盘205和第一焊盘105之间。
其中，本实施例中，第一功能层103内设有所有能够实现第一芯片1功能的结构，其中，所有能够实现第一芯片1功能的结构包括但不仅限于金属层和有源层，第二功能层203与第一功能层103类同，在本实施例中对第一功能层103和第二功能层203不再做进一步阐述。
其中，本实施例中，第一芯片1的转接面和第二芯片2的转接面相对设置时，第一焊盘105和第三焊盘205相对设置，且数量相等且一一对应，通过导电件相接在第三焊盘205和第一焊盘105之间，以实现第一芯片1和第二芯片2的互连通信。
需要说明的是，本实施例中，第一芯片1上第一导电件101的个数与第一芯片1上第一焊盘105的个数相等且一一对应，相应的，第二芯片2上第二导电件201的个数与第二芯片2上第三焊盘205的个数相等且一一对应，在本实施例中对于第一导电件101和第二导电件201的个数并不做进一步限定。
其中，本实施例中，第一芯片1还包括第一绝缘层104，第一绝缘层104上设有与第一焊盘105相连通的第一开窗结构107，第二芯片2还包括第二绝缘层204，第二绝缘层204上设有与第三焊盘205相连通的第二开窗结构206，导电件位于第一开窗结构107和第二开窗结构206之间。
需要说明的是，本实施例中，第一开窗结构107为在第一芯片1的第一绝缘层104上通过光刻工艺或其他工艺在第一焊盘105和第二焊盘106的表面加工出的第一绝缘层104的开窗结构。相应的，第二开窗结构206为第二芯片2的第二绝缘层204上通过光刻工艺或其他工艺在第三焊盘205的表面加工出的第二绝缘层204的开窗结构。其中，第一开窗结构107和第二开窗结构206可以预先分别形成于第一芯片1所在的晶圆上、以及第二芯片2所在的晶圆上，或者，第一开窗结构107和第二开窗结构206也可以是在后期芯片互连时形成的开窗结构，在本实施例中，对于第一开窗结构107的形成时间并不做进一步限定。
其中，本实施例中，绝缘层用于实现第一芯片1和第二芯片2的表面绝缘，且对第一芯片1和第二芯片2具有一定的保护作用。本实施例中，绝缘层采用的绝缘材料可以为无机绝缘材料，如聚酰亚胺、云母，也可以为有机绝缘材料，本实施例中，只需保证第一绝缘层104和第二绝缘层204能够分别实现第一芯片1和第二芯片2的表面绝缘，且对第一芯片1和第二芯片2具有一定的保护作用即可，本实施例中对于该第一绝缘层104和第二绝缘层204采用的绝缘材料不作进一步限定。
需要说明的是，第一绝缘层104和第二绝缘层204的厚度为微米级，例如5um。
其中，本实施例中，第一芯片1和第二芯片2之间还设有用于密封导电组件的密封层3，通过密封层3对第一芯片1和第二芯片2的互连区域进行密封保护。
其中，本实施例中，密封层3采用的密封材料可以为水胶、也可以为环氧胶或者其他任何能够起到粘合、防腐、隔绝水汽的胶体材料。
实施例五
在上述实施例的基础上，本实施例提供一种芯片，该芯片包括上述任一实施例中的的芯片互连结构，且该本实施例包含芯片互连结构的芯片可以作为一个单独的芯片进行后续的工艺，如采用传统的封装方式进行封装使用，但该芯片同时具备第一芯片1和第二芯片2的功能。
实施例六
图3是本申请实施例六提供的互连方法的流程示意图，图4是本申请实施例六提供的第一晶圆的结构示意图，图5是本申请实施例六提供的第二晶圆的结构示意图，图6是本申请实施例六提供的第一芯片的结构示意图，图7是本申请实施例六提供的第二芯片的结构示意图。
如图3至图7所示，在上述实施例的基础上，本申请提供一种芯片互连方法，应用于第一芯片1和第一芯片1至少一个第二芯片2的相互连接，包括：
步骤101：在第一晶圆102和第二晶圆202的至少一者上形成导电件，其中，第一晶圆102为第一芯片1所在的晶圆，第二晶圆202为第二芯片2所在的晶圆，导电件的位置与焊盘的位置相对应；
步骤102：在第一晶圆102和第二晶圆202上分别获得第一芯片1和第二芯片2；
步骤103：对接第一芯片1和第二芯片2，并利用导电件连接第一芯片1的焊盘与第二芯片2的焊盘。
其中，本实施例中，在第一晶圆102和第二晶圆202的至少一者上形成导电件，即本实施例可以在在第一晶圆102或第二晶圆202上形成导电件，此时，导电件为一个整体式结构，也可以在第一晶圆102和第二晶圆202上分别形成导电件，此时导电件为分体式结构。
其中，本实施例中，在第一晶圆102和第二晶圆202的至少一者上形成导电件，具体包括：
分别在第一晶圆102上和第二晶圆202上形成导电件。
需要说明的是，本实施例中，如图6和图7所示，分别在第一晶圆102上和第二晶圆202上形成导电件，此时，导电件包括第一导电件101和第二导电件201，第一导电件101的第一端和第一晶圆102的焊盘连接，第二导电件201的第二端和第二晶圆202的焊盘连接。
其中，本实施例中，如图6和图7所示，第一导电件101包括填充在第一开窗结构107内的第一导电部分，以及位于第一绝缘层104表面的第二导电部分。为了增大第一导电件101和第二导电件201的接触面积，该第二导电部分在第一芯片1上的投影面积大于第一导电部分在第一芯片1上的投影面积。相应的，第二导电件202也包括填充在第二开窗结构206内的第三导电部分，以及位于第二绝缘层204表面的第四导电部分。同理的，为了增大第一导电件101和第二导电件201的接触面积，该第四导电部分在第二芯片2上的投影面积大于第三导电部分在第二芯片2上的投影面积。
应当理解的是，如图1和图2所示，当第一芯片1和第二芯片2通过第一导电件101和第二导电件201互连时，第一导电件101的第二导电部分和第二导电件202的第四导电部分相接触。
其中，本实施例中，第一导电件101的第二端与第二导电件201的第一端具有相同的投影形状，该投影形状为第一导电件101在第一芯片1上的投影形状，或者第二导电件201在第二芯片2上的投影形状，该投影形状可以为圆形、椭圆形或者多边形。
其中，本实施例中，导电件的形成方式包括以下一种或几种：溅射、蒸镀、电镀、化镀、贴导电膜。
其中，本实施例中，具体的，当采用溅射方式形成导电件时，首先在第一绝缘层104或第二绝缘层204上整面溅射一层Ti、Wu种子层，涂光刻胶并通过光刻工艺加工出导电件所需的凸块凹坑，电镀金填满凹坑，去光刻胶后蚀刻种子层即得到所需结构。需要说明的是，通过溅射、蒸镀、电镀、化镀、贴导电膜的方式在晶圆的绝缘层上形成导电件为现有技术，在本实施例中，不再对其具体的形成过程作进一步阐述。
其中，本实施例中，在第一晶圆102和第二晶圆202上分别获得第一芯片1和第二芯片2，具体包括：
在第一晶圆102上切割出第一芯片1，在第二晶圆202上切割出第二芯片2，其中第一芯片1和第二芯片2均为单颗裸芯片。
其中，本实施例中，在切割之前，首先需对第一晶圆102和第二晶圆202研磨减薄，使其研磨至芯片的指定厚度，然后再将第一晶圆102和第二晶圆202切割出第一芯片1和第二芯片2，因此，本实施例中，第一芯片1和第二芯片2均为单颗裸芯片。
其中，本实施例中，利用导电件连接第一芯片1的焊盘与第二芯片2的焊盘，具体包括：
通过焊接或压合连接第一芯片1上的导电件和/或第二芯片2上的导电件，以使导电件连接第一芯片1的焊盘与第二芯片2的焊盘。
其中，本实施例中，根据导电件所选用的材料不同在将第一芯片1和第二芯片2互连时所采用的工艺也不同，在上述实施例中对导电件的材料以及不同材料对应的连接方式进行说明，在本实施例中不再作进一步阐述。
其中，本实施例中，也可通过在第一导电件101和第二导电件201之间设置导电胶5，通过第二芯片2来实现第一导电件101和第二导电件201的电连接。具体的，本实施例中，可以通过在第一导电件101和第二导电件201之间设置整片的导电胶5来实现第一导电件101和第二导电件201的电连接，也可以通过在第一导电件101的第二端或者第二导电件201的第一端逐个设置单个的导电胶5来实现第一导电件101和第二导电件201的电连接。
其中，本实施例中，如图4和图5所示，在第一晶圆102和第二晶圆202的至少一者上形成导电件的步骤之前，还包括：
判断第一晶圆102和第二晶圆202的表面是否有均有绝缘层；
如第一晶圆102和第二晶圆202的表面上具有绝缘层，则在第一晶圆102的绝缘层上开设与第一晶圆102的焊盘相连通的第一开窗结构107，在第二晶圆202的绝缘层上开设与第二晶圆202的焊盘相连通的第二开窗结构206；
如第一晶圆102和第二晶圆202的表面上没有绝缘层，则在第一晶圆102和第二晶圆202的表面上分别形成绝缘层后，在第一晶圆102的绝缘层上开设与第一晶圆102的焊盘相连通的第一开窗结构107，在第二晶圆202的绝缘层上开设与第二晶圆202的焊盘相连通的第二开窗结构206。
需要说明的是，如图4和图5所示，第一开窗结构107形成于第一芯片1的第一绝缘层104上，第二开窗结构206形成于第二芯片2的第二绝缘层204上。在第一晶圆102和第二晶圆202的表面上形成绝缘层的方式包括匀胶涂布、等离子喷涂、印刷、贴膜等工艺，通过上述工艺形成绝缘层为现有技术，在本实施例中不再对其作进一步阐述。
其中，本实施例中，利用导电件连接第一芯片1的焊盘与第二芯片2的焊盘之后，还包括：
在第一芯片1和第二芯片2之间形成用于密封导电组件的密封层3，通过密封层3对第一芯片1和第二芯片2的互连区域进行密封保护。
需要说明的是，密封层3的形成方式包括点胶、划胶、模封等任何胶体成型工艺，通过上述胶体成型工艺形成密封层为现有技术，在本实施例中不再对其作进一步阐述。
需要说明的是，当通过在第一导电件101和第二导电件201之间设置整片的导电胶5来实现第一导电件101和第二导电件201的电连接时，第一导电件101和第二导电件201之间整片的导电胶5在实现第一导电件101和第二导电件201电连接的同时，整片的导电胶5还形成了本实施例中位于第一芯片1和第二芯片2之间的密封层3。
本申请提供的一种芯片互连结构、芯片及互连方法实现了两个或两个以上芯片互连且能够实现互连芯片的高速通信的目的。
在本申请的描述中，需要理解的是，术语“中心”、“纵向”、“横向”、“长度”、“宽度”、“厚度”、“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
在本申请的描述中，需要理解的是，本文中使用的术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或单元的过程、方法、系统、产品或设备不必限于清楚地列出的那些步骤或单元，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或单元。
除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等应做广义理解，例如可以是固定连接，也可以是可拆卸连接，或成为一体；可以是直接相连，也可以通过中间媒介间接相连，可以使两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本申请中的具体含义。此外，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。
最后应说明的是：以上各实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述各实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分或者全部技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (27)

1.一种芯片互连结构，其特征在于，包括第一芯片和至少一个第二芯片，所述第一芯片的转接面和所述第二芯片的转接面相对设置，所述第二芯片和所述第一芯片之间还设有至少一个导电组件，每个所述导电组件包括至少一个导电件，所述导电件连接在所述第二芯片的焊盘与所述第一芯片的焊盘之间。
2.根据权利要求1所述的芯片互连结构，其中，每个所述导电组件包括至少两个依次相连的导电件。
3.根据权利要求2所述的芯片互连结构，其中，所述至少两个依次相连的导电件层叠设置。
4.根据权利要求1所述的芯片互连结构，其中，每个所述导电组件包括第一导电件和第二导电件，所述第一导电件的第一端和所述第一芯片的焊盘连接，所述第一导电件的第二端和所述第二导电件的第一端相互对接，所述第二导电件的第二端和所述第二芯片的焊盘连接。
5.根据权利要求4所述的芯片互连结构，其中，所述导电件为金属件。
6.根据权利要求4或5所述的芯片互连结构，其中，所述第一导电件和所述第二导电件通过焊接连接，或者，所述第一导电件和所述第二导电件通过导电胶连接。
7.根据权利要求4或5所述的芯片互连结构，其中，所述导电件的材料为铜、银、锡、金以及铝中的一种或两种。
8.根据权利要求5所述的芯片互连结构，其中，所述第一导电件和所述第二导电件为能够形成共晶的导电金属。
9.根据权利要求5所述的芯片互连结构，其中，所述第一导电件和所述第二导电件通过焊接连接时，所述第一导电件和所述第二导电件的连接处具有共晶层。
10.根据权利要求1-9中任一所述的芯片互连结构，其中，所述导电件和所述焊盘为一体式结构。
11.根据权利要求4所述的芯片互连结构，其中，所述第一导电件的第二端与所述第二导电件的第一端具有相同的截面形状。
12.根据权利要求11所述的芯片互连结构，其中，所述导电件垂直设置在所述第二芯片的焊盘与所述第一芯片的焊盘之间。
13.根据权利要求11或12所述的芯片互连结构，其中，所述导电件为圆柱体或棱柱体。
14.根据权利要求1所述的芯片互连结构，其中，所述第二芯片的数量为至少两个，所述第二芯片均设置在所述第一芯片的同一侧，或者所述第二芯片设置在所述第一芯片的正反两侧。
15.根据权利要求1-9中任一所述的芯片互连结构，其中，所述第一芯片和所述第二芯片均为单颗裸芯片。
16.根据权利要求15所述的芯片互连结构，其中，所述第一芯片包括第一晶圆，所述第一晶圆上设有第一功能层，所述第一功能层上开设有第一焊盘，所述第一功能层上还设有与外部电路互连的第二焊盘；
所述第二芯片包括第二晶圆，所述第二晶圆上设有第二功能层，所述第二功能层上开设有第三焊盘，所述导电件相接在所述第三焊盘和所述第一焊盘之间。
17.根据权利要求16所述的芯片互连结构，其中，所述第一芯片还包括第一绝缘层，所述第一绝缘层上设有与所述第一焊盘相连通的第一开窗结构，所述第二芯片还包括第二绝缘层，所述第二绝缘层上设有与所述第三焊盘相连通的第二开窗结构，所述导电件位于所述第一开窗结构和所述第二开窗结构之间。
18.根据权利要求17所述的芯片互连结构，其中，所述第一芯片和所述第二芯片之间还设有用于密封所述导电组件的密封层。
19.根据权利要求1所述的芯片互连结构，其中，所述第一芯片的焊盘设置在所述第一芯片的转接面，所述第二芯片的焊盘设置在所述第二芯片的转接面，所述第一芯片的焊盘与对应的第二芯片的焊盘通过所述一个导电组件互连。
20.一种芯片，其特征在于，包括如上述权利要求1-19中任一所述的芯片互连结构。
21.一种芯片互连方法，应用于第一芯片和至少一个第二芯片的相互连接，其特征在于，包括：
在第一晶圆和第二晶圆的至少一者上形成导电件，其中，所述第一晶圆为所述第一芯片所在的晶圆，所述第二晶圆为所述第二芯片所在的晶圆，所述导电件的位置与焊盘的位置相对应；
在所述第一晶圆和所述第二晶圆上分别获得所述第一芯片和所述第二芯片；
对接所述第一芯片和所述第二芯片，并利用所述导电件连接所述第一芯片的焊盘与所述第二芯片的焊盘。
22.根据权利要求21所述的芯片互连方法，其中，所述在第一晶圆和第二晶圆的至少一者上形成导电件，具体包括：
分别在所述第一晶圆上和所述第二晶圆上形成所述导电件。
23.根据权利要求21或22所述的芯片互连方法，其中，所述导电件的形成方式包括以下一种或几种：溅射、蒸镀、电镀、化镀、贴导电膜。
24.根据权利要求21所述的芯片互连方法，其中，所述在所述第一晶圆和所述第二晶圆上分别获得所述第一芯片和所述第二芯片，具体包括：
在所述第一晶圆上切割出所述第一芯片，在所述第二晶圆上切割出所述第二芯片，其中，所述第一芯片和所述第二芯片均为单颗裸芯片。
25.根据权利要求21所述的芯片互连方法，其中，所述利用所述导电件连接所述第一芯片的焊盘与所述第二芯片的焊盘，具体包括：
通过焊接或压合连接所述第一芯片上的导电件和/或所述第二芯片上的导电件，以使所述导电件连接所述第一芯片的焊盘与所述第二芯片的焊盘。
26.根据权利要求21所述的芯片互连方法，其中，所述在第一晶圆和第二晶圆的至少一者上形成导电件的步骤之前，还包括：
若所述第一晶圆和第二晶圆的表面上具有绝缘层，则在所述第一晶圆的绝缘层上开设与所述第一晶圆的焊盘相连通的第一开窗结构，在所述第二晶圆的绝缘层上开设与所述第二晶圆的焊盘相连通的第二开窗结构；
若所述第一晶圆和第二晶圆的表面上没有所述绝缘层，则在所述第一晶圆和第二晶圆的表面上分别形成所述绝缘层，并在所述第一晶圆的绝缘层上开设与所述第一晶圆的焊盘相连通的第一开窗结构，在所述第二晶圆的绝缘层上开设与所述第二晶圆的焊盘相连通的第二开窗结构。
27.根据权利要求21所述的芯片互连方法，其中，所述利用所述导电件连接所述第一芯片的焊盘与所述第二芯片的焊盘之后，还包括：
在所述第一芯片和所述第二芯片之间形成密封层。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104183508A (zh) * 2013-05-24 2014-12-03 宏启胜精密电子(秦皇岛)有限公司 半导体器件的制作方法
CN104576621A (zh) * 2013-10-16 2015-04-29 三星电子株式会社 芯片堆叠半导体封装件及其制造方法
CN107731759A (zh) * 2016-08-10 2018-02-23 南茂科技股份有限公司 半导体封装
CN108461464A (zh) * 2018-02-07 2018-08-28 睿力集成电路有限公司 半导体封装结构及其制造方法
CN109994443A (zh) * 2018-01-03 2019-07-09 三星电子株式会社 半导体封装

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2104138A1 (de) * 2008-03-18 2009-09-23 EV Group E. Thallner GmbH Verfahren zum Bonden von Chips auf Wafer
EP2414801B1 (en) * 2009-03-30 2021-05-26 QUALCOMM Incorporated Chip package with stacked processor and memory chips
JP5489705B2 (ja) * 2009-12-26 2014-05-14 キヤノン株式会社 固体撮像装置および撮像システム
DE102014107018A1 (de) * 2014-05-19 2015-11-19 Infineon Technologies Ag Halbleitervorrichtung mit lötbaren und bondbaren elektrischen Kontaktplättchen
US9356009B2 (en) * 2014-05-27 2016-05-31 Micron Technology, Inc. Interconnect structure with redundant electrical connectors and associated systems and methods

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104183508A (zh) * 2013-05-24 2014-12-03 宏启胜精密电子(秦皇岛)有限公司 半导体器件的制作方法
CN104576621A (zh) * 2013-10-16 2015-04-29 三星电子株式会社 芯片堆叠半导体封装件及其制造方法
CN107731759A (zh) * 2016-08-10 2018-02-23 南茂科技股份有限公司 半导体封装
CN109994443A (zh) * 2018-01-03 2019-07-09 三星电子株式会社 半导体封装
CN108461464A (zh) * 2018-02-07 2018-08-28 睿力集成电路有限公司 半导体封装结构及其制造方法

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