CN111092059A - 半导体封装件 - Google Patents

半导体封装件 Download PDF

Info

Publication number
CN111092059A
CN111092059A CN201910976753.9A CN201910976753A CN111092059A CN 111092059 A CN111092059 A CN 111092059A CN 201910976753 A CN201910976753 A CN 201910976753A CN 111092059 A CN111092059 A CN 111092059A
Authority
CN
China
Prior art keywords
chip
semiconductor
region
bonding layer
semiconductor package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910976753.9A
Other languages
English (en)
Inventor
金宣澈
金泰勋
黄智焕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of CN111092059A publication Critical patent/CN111092059A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/46—Structure, shape, material or disposition of the wire connectors prior to the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08135—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/08145—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/08146—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bonding area connecting to a via connection in the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
    • H01L2224/081—Disposition
    • H01L2224/0812—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/08151—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/08221—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/08225—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/0823—Disposition the bonding area connecting directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding the bonding area connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bonding area connecting to a pin of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091—Disposition
    • H01L2224/0918—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/09181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13023—Disposition the whole bump connector protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14131—Square or rectangular array being uniform, i.e. having a uniform pitch across the array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1413—Square or rectangular array
    • H01L2224/14134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/14135—Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/80009—Pre-treatment of the bonding area
    • H01L2224/8001—Cleaning the bonding area, e.g. oxide removal step, desmearing
    • H01L2224/80013—Plasma cleaning
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/8034—Bonding interfaces of the bonding area
    • H01L2224/80357—Bonding interfaces of the bonding area being flush with the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80895—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/80001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
    • H01L2224/808—Bonding techniques
    • H01L2224/80894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • H01L2224/80896—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces between electrically insulating surfaces, e.g. oxide or nitride layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/9202—Forming additional connectors after the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

一种半导体封装件包括：第一半导体芯片，所述第一半导体芯片包括位于其一个表面上的第一结合层；以及芯片结构，所述芯片结构堆叠在所述第一半导体芯片上，并且包括位于所述芯片结构的面对所述第一半导体芯片的表面上的第二结合层以及多个第二半导体芯片。所述多个第二半导体芯片分别包括芯片区域和位于所述芯片区域的外部的划片线区域，所述多个第二半导体芯片在所述芯片结构中通过所述划片线区域彼此连接。所述第一结合层包括第一金属焊盘和围绕所述第一金属焊盘的第一结合绝缘层，所述第二结合层包括第二金属焊盘和围绕所述第二金属焊盘的第二结合绝缘层，所述第一金属焊盘和所述第二金属焊盘设置为彼此对应并且彼此结合。

Description

半导体封装件
相关申请的交叉引用
于2018年10月24日在韩国知识产权局提交的名为“Semiconductor Package”(半导体封装件)的韩国专利申请No.10-2018-0127570通过引用的方式全文结合于本申请中。
技术领域
实施例涉及半导体封装件。
背景技术
随着电子工业的不断发展，对电子组件的高性能、高速度和小型化的需求日益增长。特别地，在半导体封装件中，已经进行了各种尝试来减小其厚度。
发明内容
实施例针对一种半导体封装件，其包括：第一半导体芯片，所述第一半导体芯片包括位于其一个表面上的第一结合层；以及芯片结构，所述芯片结构堆叠在所述第一半导体芯片上，并且包括位于所述芯片结构的面对所述第一半导体芯片的表面上的第二结合层以及多个第二半导体芯片。所述多个第二半导体芯片可以分别包括芯片区域和位于所述芯片区域的外部的划片线区域。所述多个第二半导体芯片可以在所述芯片结构中通过所述划片线区域彼此连接。所述第一结合层可以包括第一金属焊盘和围绕所述第一金属焊盘的第一结合绝缘层，所述第二结合层可以包括第二金属焊盘和围绕所述第二金属焊盘的第二结合绝缘层，所述第一金属焊盘和所述第二金属焊盘设置为彼此对应并且彼此结合。
实施例还涉及一种半导体封装件，其包括：第一半导体芯片，所述第一半导体芯片包括位于其一个表面上的第一结合层，并且具有其中设置有半导体器件的器件区域和位于所述器件区域的至少一侧的通路区域，所述通路区域具有设置在其中的贯穿通路；以及芯片结构，所述芯片结构堆叠在所述第一半导体芯片上并且通过所述第一结合层结合到所述第一半导体芯片，并且包括连接到所述第一结合层的第二结合层以及多个第二半导体芯片。所述多个第二半导体芯片可以分别包括芯片区域和位于所述芯片区域的外部的划片线区域。所述多个第二半导体芯片可以在所述芯片结构中通过所述划片线区域彼此连接。
实施例还涉及一种半导体封装件，其包括：第一半导体芯片，所述第一半导体芯片包括位于其表面上的第一金属焊盘；第一再分布部分，所述第一再分布部分位于所述第一半导体芯片上，并且包括电连接到所述第一半导体芯片的第一再分布层和位于所述第一再分布层的下表面上并且结合到所述第一金属焊盘的第二金属焊盘；以及芯片结构，所述芯片结构位于所述第一再分布部分上并且包括多个第二半导体芯片。在平面上，所述第一半导体芯片的尺寸可以与所述芯片结构的尺寸基本相同。
附图说明
通过参考附图详细描述示例实施例，对于本领域技术人员而言，特征将变得显而易见，在附图中：
图1示出了根据示例实施例的半导体封装件的示意性截面图；
图2A和图2B示出了根据示例实施例的半导体封装件的部分放大视图；
图3示出了根据示例实施例的半导体封装件的部分配置的俯视图；
图4A和图4B示出了根据示例实施例的半导体封装件的部分配置的示意性俯视图；
图5示出了根据示例实施例的半导体封装件的示意性截面图；
图6示出了根据示例实施例的半导体封装件的示意性截面图；
图7示出了根据示例实施例的半导体封装件的示意性截面图；
图8A和图8B示出了根据示例实施例的部分放大视图；
图9示出了根据示例实施例的半导体封装件的示意性截面图；
图10示出了根据示例实施例的半导体封装件的示意性截面图；
图11A至图11F示出了根据示例实施例的制造半导体封装件的方法中的各阶段的示意性主要逐步视图；以及
图12A至图12D示出了根据示例实施例的制造半导体封装件的方法中的各阶段的示意性主要逐步视图。
具体实施方式
图1是根据示例实施例的半导体封装件的示意性截面图。
图2A和图2B是根据示例实施例的半导体封装件的部分放大视图。图2A和图2B分别是图1的“A”区域和“B”区域的放大视图。
图3是根据示例实施例的半导体封装件的部分配置的示意性俯视图。在图3中，示出了第一半导体芯片120的俯视图。
参考图1至图3，半导体封装件1000可以包括衬底301、通过凸块190安装在衬底301上的第一半导体芯片120、堆叠并且设置在第一半导体芯片120的上部的第一芯片结构220a和第二芯片结构220b、包封第一半导体芯片120以及第一芯片结构220a和第二芯片结构220b的包封部分340以及位于衬底301的下表面上的连接端子390。
第一半导体芯片120以及第一芯片结构220a和第二芯片结构220b可以安装在衬底301上。衬底301可以包括例如硅(Si)、玻璃、陶瓷或塑料。衬底301可以具有位于其上表面上的衬底焊盘326和位于其下表面上的连接端子390。衬底301可以具有其中包括布线图案的多层结构。
第一半导体芯片120可以包括主体部分121、位于主体部分121的下表面上的连接焊盘122、穿过主体部分121的至少一部分的贯穿通路125以及第一结合层126。第一半导体芯片120可以包括例如逻辑半导体芯片和/或存储半导体芯片。逻辑半导体芯片可以是微处理器，例如中央处理器(CPU)、控制器、专用集成电路(ASIC)等。存储半导体芯片可以是诸如动态随机存取存储器(DRAM)、静态随机存取存储器(SRAM)等的易失性存储器，或者诸如闪存等的非易失性存储器。
第一半导体芯片120可以具有其中设置有半导体器件的器件区域TR和设置在器件区域TR的外围的通路区域VR，通路区域VR具有设置在其中的贯穿通路125。器件区域TR和通路区域VR在俯视图中可以是彼此分离的区域。例如，如图3所示，通路区域VR可以设置为围绕位于中心的器件区域TR。器件区域TR可以是例如其中设置有构成逻辑半导体芯片的晶体管的区域。通路区域VR可以是其中设置有贯穿通路125以将上部的第一芯片结构220a和第二芯片结构220b与下部的衬底301电连接的区域。器件区域TR和通路区域VR是形成在一个衬底上的不同区域，从而器件区域TR和通路区域VR可以一体形成，并且器件区域TR的上表面和下表面分别与通路区域VR的上表面和下表面共面。
例如，如图1所示，主体部分121可以包括第一衬底区域SUB1和位于第一衬底区域SUB1的下表面上的半导体区域AR。第一衬底区域SUB1和半导体区域AR可以是在垂直于第一半导体芯片120的上表面的方向上分离的区域。第一衬底区域SUB1可以跨越器件区域TR和通路区域VR总体上设置在第一半导体芯片120上。第一衬底区域SUB1可以是包括诸如硅(Si)的半导体材料的区域。半导体区域AR可以是基于第一衬底区域SUB1形成有构成半导体芯片的诸如晶体管和/或存储单元的器件的区域。具体地，在平面上，器件可以形成在对应于器件区域TR的区域上。半导体区域AR可以位于第一半导体芯片120的面向衬底301的下部处。因此，第一半导体芯片120的下表面可以是有源表面，并且其上表面可以是无源表面。然而，根据示例实施例，可以改变有源表面的这种设置位置。
贯穿通路125可以完全穿过主体部分121的第一衬底区域SUB1和半导体区域AR。贯穿通路125可以提供衬底301与第一芯片结构220a和第二芯片结构220b之间的电连接。贯穿通路125可以由导电材料制成，并且可以包括例如钨(W)、铝(Al)和铜(Cu)中的至少一种。如图2A所示，贯穿通路125可以通过诸如通路绝缘层125I的环绕绝缘体与第一衬底区域SUB1电隔离。
连接焊盘122可以设置为在第一半导体芯片120的下表面上连接到贯穿通路125。连接焊盘122可以由诸如钨(W)、铝(Al)、铜(Cu)等的导电材料制成。
第一结合层126可以位于第一半导体芯片120的上表面上，并且可以包括第一金属焊盘126P和设置为围绕第一金属焊盘126P的第一结合绝缘层126D。第一结合层126可以是结合到上部的第一芯片结构220a的第二结合层226的层，以将第一芯片结构220a连接到第一半导体芯片120。第一金属焊盘126P可以设置为对应于通路区域VR上的贯穿通路125。例如，第一金属焊盘126P的一部分可以设置在没有形成贯穿通路125的区域中，并且可以不执行电连接功能，但是可以执行结合功能。
凸块190可以位于第一半导体芯片120的下表面上，并且可以将连接焊盘122连接到衬底301上的衬底焊盘326。凸块190可以包括诸如焊料、锡(Sn)、银(Ag)、铜(Cu)和铝(Al)的导电材料中的至少一种。凸块190的形状可以是各种形状，例如球、平台、凸块、柱、销等。凸块190可以是比连接端子390具有更小尺寸的微凸块。
第一芯片结构220a和第二芯片结构220b可以顺序地堆叠在第一半导体芯片120上。在平面上，第一芯片结构220a和第二芯片结构220b可以与第一半导体芯片120具有基本相同的尺寸。第一芯片结构220a可以包括两个第二下半导体芯片221a和222a，第二芯片结构220b可以包括两个第二上半导体芯片221b和222b。第二半导体芯片221a、222a、221b和221b可以包括例如逻辑半导体芯片和/或存储半导体芯片。例如，第一半导体芯片120可以是AP芯片，第二半导体芯片221a、222a、221b和222b可以是存储芯片。
在第一芯片结构220a和第二芯片结构220b中，第二下半导体芯片221a和222a以及第二上半导体芯片221b和222b可以形成为单个结构，而无需锯切两个半导体芯片。因此，第一芯片结构220a和第二芯片结构220b可以由非锯切或非分离状态的第二下半导体芯片221a和222a以及第二上半导体芯片221b和222b形成。在示例实施例中，包括在第一芯片结构220a和第二芯片结构220b中的第二半导体芯片221a、222a、221b和222b的数量可以不同地改变。
第二下半导体芯片221a和222a以及第二上半导体芯片221b和222b可以分别包括芯片区域CH和至少位于芯片区域CH的一侧的划片线区域SC。划片线区域SC可以位于并排设置的第二下半导体芯片221a和222a以及第二上半导体芯片221b和222b两组中的每一组中的芯片区域CH之间。根据示例实施例，划片线区域SC不仅还可以设置在并排设置的第二下半导体芯片221a与222a之间的区域和第二上半导体芯片221b与222b之间的区域中，而且还可以设置在第二半导体芯片221a、222a、221b和222的外部区域中。在第一芯片结构220a和第二芯片结构220b中的每一个中，第二下半导体芯片221a与222a以及第二上半导体芯片221b与222b可以通过划片线区域SC彼此连接。如上所述，由于第二半导体芯片221a、222a、2221b和222b可以彼此连接地安装，所以可以显著地减小整个封装件的尺寸。
第一芯片结构220a还可以包括穿过第二下半导体芯片221a和222a的至少一部分的芯片贯穿通路225以及第二结合层226和第三结合层227。第二芯片结构220b还可以包括第四结合层228。
第二下半导体芯片221a和222a可以包括第二衬底区域SUB2和位于第二衬底区域SUB2的下表面上的上器件区域MR，第二上半导体芯片221b和222b可以包括第三衬底区域SUB3和位于第三衬底区域SUB3的下表面上的上器件区域MR。第二衬底区域SUB2和第三衬底区域SUB3可以是包括诸如硅(Si)的半导体材料的区域。上器件区域MR可以是基于第二衬底区域SUB2和第三衬底区域SUB3形成构成半导体芯片的诸如晶体管和/或存储单元的器件的区域。在上器件区域MR中，构成器件的器件层DL可以如图2A和图2B所示设置。例如，第二半导体芯片221a、222a、221b和222b的下表面可以分别是有源表面。
芯片贯穿通路225可以设置在与第一半导体芯片120的通路区域VR交叠的区域中。根据示例实施例，芯片贯穿通路225可以设置为对应于贯穿通路125，或者可以设置为更少的数量。芯片贯穿通路225可以穿过至少第二下半导体芯片221a和222a的至少第二衬底区域SUB2，并且可以穿过上器件区域MR的至少一部分。芯片贯穿通路225可以提供第二芯片结构220b与第一半导体芯片120之间的电连接。芯片贯穿通路225可以电连接到第一芯片结构220a的器件区域MR的器件。芯片贯穿通路225可以由导电材料制成，并且可以包括例如钨(W)、铝(Al)和铜(Cu)中的至少一种。如图2A和图2B所示，芯片贯穿通路225可以通过绝缘的上通路绝缘层225I与第二衬底区域SUB2电隔离。
第二至第四结合层226、227和228可以包括第二至第四金属焊盘226P、227P和228P以及设置为围绕第二至第四金属焊盘226P、227P和228P的第二至第四结合绝缘层226D、227D和228D。
第二结合层226可以是结合到第一结合层126并且将第一芯片结构220a连接到第一半导体芯片120的层。第二金属焊盘226P可以电连接到第一金属焊盘126P，并且可以电连接到第一芯片结构220a的上器件区域MR的器件以及芯片贯穿通路225。
第三结合层227和第四结合层228可以是彼此结合并且将第二芯片结构220b连接到包括第一芯片结构220a的下部结构的层。第三结合层227可以位于第一芯片结构220a的无源表面上(即，位于第二下半导体芯片221a和222a的无源表面上)，第四结合层228可以位于第二芯片结构220b的有源表面上(即，位于第二上半导体芯片221b和222b的有源表面上)。第三金属焊盘227P可以形成第一芯片结构220a的上表面，并且可以连接到芯片贯穿通路225。第四金属焊盘228P可以电连接到第二芯片结构220b的上器件区域MR的器件。
如图2A和图2B所示，第一金属焊盘126P和第二金属焊盘226P可以设置在彼此对应的位置并且可以直接结合，第三金属焊盘227P和第四金属焊盘228P可以设置在彼此对应的位置并且可以直接结合。第一至第四金属焊盘126P、226P、227P和228P可以包括钨(W)、铝(Al)、铜(Cu)、氮化钨(WN)、氮化钽(TaN)和氮化钛(TiN)中的至少一种。例如，当第一至第四金属焊盘126P、226P、227P和228P由铜(Cu)制成时，它们可以通过铜(Cu)与铜(Cu)的结合而物理地电连接。彼此连接的第一至第四金属焊盘126P、226P、227P和228P可以具有相同或类似的尺寸。
第一结合绝缘层126D和第二结合绝缘层226D以及第三结合绝缘层227D和第四结合绝缘层228D可以分别通过电介质与电介质的结合来结合。第一至第四结合绝缘层126D、226D、227D和228D可以包括诸如SiO、SiN、SiCN、SiOC、SiON和SiOCN的绝缘材料中的至少一种。
在半导体封装件1000中，第一半导体芯片120与第一芯片结构220a以及第一芯片结构220a与第二芯片结构220b可以分别通过混合结合(hybrid bonding)来结合。在这种情况下，可以显著减小结合厚度，使得与通过凸块等连接的情况相比，可以减小半导体封装件1000的厚度。因此，半导体封装件1000在具有包括存储芯片的第一芯片结构220a和第二芯片结构220b堆叠在第一半导体芯片120(例如，AP芯片)上的结构的同时，可以具有减小的厚度。因此，在半导体封装件1000中可以存在能够相对增加半导体芯片120以及第一芯片结构220a和第二芯片结构220b的厚度的裕量，这从散热的角度来看是有利的。此外，半导体封装件1000可以具有减小的厚度，并且可以不包括再分布层，从而可以简化工艺。
包封部分340可以设置为围绕衬底301的上表面、凸块190、第一半导体芯片120以及第一芯片结构220a和第二芯片结构220b，以保护第一半导体芯片120以及第一芯片结构220a和第二芯片结构220b。包封部分340可以由例如硅基材料、热固性材料、热塑性材料、UV处理材料等形成。包封部分340可以由诸如树脂的聚合物形成，并且可以由例如环氧模塑化合物(EMC)形成。根据示例实施例，可以省略包封部分340。
连接端子390可以设置在衬底301的下部。连接端子390可以将半导体封装件1000连接到其上安装有半导体封装件1000的电子器件的主板等。连接端子390可以包括诸如焊料、锡(Sn)、银(Ag)、铜(Cu)和铝(Al)的导电材料中的至少一种。除了球形状之外，连接端子390的形状可以是各种形状，例如平台、凸块、柱、销等。
图4A和图4B是根据示例实施例的半导体封装件的部分配置的示意性俯视图。在图4A和图4B中，示出了对应于图3的区域。
参考图4A，第一半导体芯片120a可以包括其中设置有半导体器件的器件区域TR和沿着器件区域TR的外围彼此分开设置的第一至第四通路区域VR1、VR2、VR3和VR4，第一至第四通路区域VR1、VR2、VR3和VR4设置有设置在其中的贯穿通路125。第一至第四通路区域VR1、VR2、VR3和VR4可以设置为在平面上与器件区域TR的相应表面接触。
参考图4B，第一半导体芯片120b可以具有其中设置有半导体器件的器件区域TR以及沿着器件区域TR的外围彼此分开设置的第一通路区域VR1和第二通路区域VR2，第一通路区域VR1和第二通路区域VR2设置有设置在其中的贯穿通路125。第一通路区域VR1和第二通路区域VR2可以设置为在平面上与器件区域TR的相应的相面向的表面接触，并且可以在第一半导体芯片120b的一个方向上延伸并设置一定宽度。
如上所述，在示例实施例中，对于通路区域VR1和VR2，通路区域可以设置为多个分开设置的区域，并且通路区域VR1和VR2可以以各种形式设置在器件区域TR的外围。
图5是根据示例实施例的半导体封装件的示意性截面图。
参考图5，在半导体封装件1000a中，衬底301可以与第一半导体芯片120以及第一芯片结构220a和第二芯片结构220b具有基本相同的尺寸，并且第一半导体芯片120以及第一芯片结构220a和第二芯片结构220b的侧表面可以暴露于外部。在一个方向上，第一半导体芯片120的宽度W1可以与第一芯片结构220a和第二芯片结构220b的宽度W2基本相同。因此，第一半导体芯片120可以在平面上与第一芯片结构220a和第二芯片结构220b具有基本相同的尺寸，该尺寸可以与半导体封装件1000a的尺寸基本相同。包封部分340a可以被设置成填充在衬底301与凸块190之间。
图6是根据示例实施例的半导体封装件的示意性截面图。
参考图6，半导体封装件1000b还可以包括散热层350和粘合层355。
散热层350可以位于第二芯片结构220b的上表面上。散热层350可以经由粘合层355堆叠在第二芯片结构220b上。散热层350可以由比第一芯片结构220a和第二芯片结构220b具有更高的导热率的材料制成，使得从第一芯片结构220a和第二芯片结构220b产生的热量可以向上消散。例如，散热层350可以是由金属(例如，铜(Cu))制成的金属层。
散热层350可以比第一芯片结构220a和第二芯片结构220b具有更大的尺寸。在示例实施例中，散热层350可以在平面上与半导体封装件1000b具有基本相同的尺寸。根据示例实施例，散热层350可以与第一芯片结构220a和第二芯片结构220b具有相同的尺寸。
图7是根据示例实施例的半导体封装件的示意性截面图。
图8A和图8B是根据示例实施例的半导体封装件的部分放大视图。图8A和8B分别是图7的“C”区域和“D”区域的放大视图。
参考图7、图8A和图8B，半导体封装件1000c可以包括第一半导体芯片120a、设置在第一半导体芯片120a的下部的第一再分布部分110、设置在第一半导体芯片120a的上部的第二再分布部分130、包封第一半导体芯片120a的包封部分340a、穿过包封部分340a的导电柱325、堆叠在第二再分布部分130上的第一芯片结构220a和第二芯片结构220b以及设置在第一再分布部分的下部的连接端子390。半导体封装件1000c可以是扇出型半导体封装件，其中第一再分布部分110延伸到第一半导体芯片120a的外部区域并且再分布。因此，第一再分布部分110可以包括在平面上不与第一半导体芯片120a交叠的区域。在图7至图8B中，与图1中的附图标记相同的附图标记示出了相同或对应的配置，可以等同地应用以上参考图1的描述。
相对于图1的示例实施例，第一半导体芯片120a可以不包括通路区域VR，可以仅包括与图1的器件区域TR对应的区域。第一半导体芯片120a的主体部分121可以包括第一衬底区域SUB1和器件区域AR，并且器件区域AR可以位于第一衬底区域SUB1的上部。
在本示例实施例中，第一半导体芯片120a可以比第一芯片结构220a和第二芯片结构220b具有更小的尺寸。因此，包封部分340a可以设置在第一再分布部分110与第二再分布部分130之间的第一半导体芯片120a的外部，以包封第一半导体芯片120a。可以进一步设置穿过包封部分340a并且连接第一再分布部分110和第二再分布部分130的导电柱325。导电柱325可以在下端具有相对大的宽度的区域。
第一再分布部分110可以设置在第一半导体芯片120a的下部，以再分布第一半导体芯片120a。第一再分布部分110可以包括第一布线绝缘层111、第一再分布层112和第一通路113。在示例实施例中，构成第一再分布部分110的第一布线绝缘层111、第一再分布层112和第一通路113的层数和设置可以不同地改变。
第一布线绝缘层111可以由绝缘材料(例如，可光成像介电(PID)树脂)制成。在这种情况下，第一布线绝缘层111还可以包括无机填料。第一布线绝缘层111可以根据第一再分布层112的层数由多个层制成，并且可以由彼此相同的材料制成，或者由彼此不同的材料制成。第一再分布层112和第一通路113可以用于再分布第一半导体芯片120a的布线。第一通路113可以完全填充有导电材料。导电材料可以具有沿着通孔的壁形成的形状，并且可以具有各种形状，例如圆柱形形状和锥形形状。第一再分布层112和第一通路113可以由诸如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、金(Au)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金的导电材料形成。
第二再分布部分130可以设置在第一半导体芯片120a的上部，并且可以电连接到第一半导体芯片120a和第一再分布部分110。第二再分布部分130可以包括第二布线绝缘层131、第二再分布层132、第二通路133和形成下表面的第二结合层。在示例实施例中，构成第二再分布部分130的第二布线绝缘层131、第二再分布层132和第二通路133的层数和设置可以不同地改变。
第二布线绝缘层131可以由与第一布线绝缘层111相同的绝缘材料(例如，可光成像介电(PID)树脂)制成。第二再分布层132和第二通路133可以包括导电材料，例如铜(Cu)、铝(Al)、银(Ag)、锡(Sn)、镍(Ni)、铅(Pb)、钛(Ti)或它们的合金。
第二结合层136可以包括第二金属焊盘136P和设置为围绕第二金属焊盘136P的第二结合绝缘层136D。第二金属焊盘136P可以通过设置在其上方的第二再分布层132和第二通路133连接到第一芯片结构220a。第二结合层136可以是结合到设置在其下方的第一半导体芯片120a的第一结合层126并且将第一芯片结构220a和第二芯片结构220b连接到设置在其下方的第一半导体芯片120a和第一再分布部分110的层。
第一芯片结构220a和第二芯片结构220b可以在第一半导体芯片120a的上部处顺序地堆叠在第二再分布部分130上。第一芯片结构220a可以包括第二下半导体芯片221a和222a，并且还可以包括穿过第二下半导体芯片221a和222a的至少一部分的芯片贯穿通路225以及第三结合层227。第二芯片结构220b可以包括第二上半导体芯片221b和222b，并且还可以包括第四结合层228。如图8B所示，第二下半导体芯片221a和222a的上表面可以是有源表面，第二上半导体芯片221b和222b的下表面可以是有源表面。因此，第一芯片结构220a和第二芯片结构220b可以堆叠为使得有源表面以面对面的方式彼此面对。
如图8A和图8B所示，第一金属焊盘126P和第二金属焊盘136P可以设置在彼此对应的位置并且可以直接结合，第三金属焊盘227P和第四金属焊盘228P可以设置在彼此对应的位置并且可以直接结合。例如，当第一至第四金属焊盘126P、136P、227P和228P由铜(Cu)制成时，第一至第四金属焊盘126P、136P、227P和228P可以通过铜(Cu)与铜(Cu)的结合物理地电连接。彼此连接的第一至第四金属焊盘126P、136P、227P和228P可以具有相同或类似的尺寸。第一结合绝缘层126D和第二结合绝缘层136D以及第三结合绝缘层227D和第四结合绝缘层228D可以分别通过电介质与电介质的结合来结合。
在半导体封装件1000c中，第一半导体芯片120a和第二再分布部分130以及第一芯片结构220a和第二芯片结构220b可以分别通过混合结合来结合。在这种情况下，可以显著减小结合厚度，使得与通过凸块等连接的情况相比，可以减小半导体封装件1000c的厚度。
图9是根据示例实施例的半导体封装件的示意性截面图。
参考图9，在半导体封装件1000d中，第二半导体芯片221a、222a、221b和222b的下表面都可以是有源表面。因此，第一芯片结构220a和第二芯片结构220b可以以面对后背(face-to-back)的方式堆叠，使得有源表面都面向下。这样，在示例实施例中，第一芯片结构220a和第二芯片结构220b的堆叠方向可以根据制造工艺等不同地确定。类似地，对于第一半导体芯片120a，根据示例实施例，有源表面的方向可以不同地改变。
图10是根据示例实施例的半导体封装件的示意性截面图。
参考图10，半导体封装件1000e还可以包括围绕第一半导体芯片120a的芯层170。
芯层170可以包括穿过其上表面和下表面的通孔CA，从而安装第一半导体芯片120a。通孔CA可以形成在芯层170的中心。此外，在一些示例实施例中，通孔CA可以不完全穿过下表面，而是可以具有腔体形状。类似于第一半导体芯片120a，芯层170可以混合结合到第一再分布部分110。
芯层170可以包括芯绝缘层171、芯布线层172和芯通路174。芯布线层172和芯通路174可以设置为电连接芯层170的上表面和下表面。芯布线层172可以连接到第一再分布部分110的第一再分布层112和第二再分布部分130的第二再分布层132。芯布线层172可以设置在芯绝缘层171的内部。通过芯层170的芯布线层172的下表面暴露的芯布线层172可以嵌入到芯绝缘层171中，并且其可以是根据制造工艺的结构。根据示例实施例，芯层170可以不包括芯布线层172和芯通路174，而是可以仅包括芯绝缘层171。在本示例实施例中，例如，芯通路174被示出为具有宽度向下部增加的锥形形状，并且芯通路174的形状和锥形方向等可以根据工艺顺序而改变。
芯绝缘层171可以包括绝缘材料，例如诸如环氧树脂的热固性树脂或诸如聚酰亚胺的热塑性树脂，并且还可以包括无机填料。在另一个实施方式中，芯绝缘层171可以由浸渍有芯材料(例如，玻璃纤维、玻璃布或玻璃织物)以及无机填料的树脂(例如，预浸料坯、ABF(Ajinomoto Build-up Film)、FR-4或双马来酰亚胺三嗪(BT))形成。芯布线层172和芯通路174可以包括金属材料，例如铜(Cu)等。
包封部分340b可以填充芯层170的通孔CA中的空间以包封通孔CA，并且可以在芯层170的下表面上延伸。取决于制造工艺，包封部分340b可以在芯层170的上表面上延伸。包封部分340b可以填充第一半导体芯片120a与通孔CA的内侧壁之间的空间的至少一部分。因此，包封部分340b也可以用作粘合层。
图11A至图11F示意性地示出了根据示例实施例的制造半导体封装件的方法中的各阶段的主要逐步视图。图11A至图11F示出了图1的半导体封装件的示例制造方法。
参考图11A，第一半导体芯片120可以以晶片级形成。
可以通过在一个半导体衬底上形成包括半导体器件的器件区域TR并且在器件区域TR的外围形成贯穿通路125以形成通路区域VR来提供第一半导体芯片120。器件区域TR和通路区域VR可以具有不同的界面或者可以不被清楚地区分。
贯穿通路125可以例如形成为最后通路结构、中间通路结构或首先通路结构。作为参考，首先通路结构可以指在主体部分121中形成器件区域AR之前首先形成通路的结构；中间通路结构可以指形成器件区域AR的诸如晶体管等的电路并且随后在器件区域AR的上部形成布线之前形成通路的结构；而最后通路结构可以指在形成所有布线之后形成通路的结构。
可以通过在有源表面上形成连接焊盘122以及在无源表面上形成包括第一金属焊盘126P和第一结合绝缘层126D的第一结合层126来制备第一半导体芯片120。
参考图11B，可以将第一芯片结构220a结合在第一半导体芯片120上。
第一芯片结构220a具有形成在一个衬底上的第二下半导体芯片221a和222a，并且可以在没有锯切开芯片221a和222a的情况下来制备第一芯片结构220a。因此，第二下半导体芯片221a和222a可以分别包括芯片区域CH和位于芯片区域CH的至少一侧的划片线区域SC，并且第二下半导体芯片221a和222a中的每一个第二下半导体芯片的划片线区域SC可以彼此连接。可以通过在与第一半导体芯片120的通路区域VR对应或与通路区域VR交叠的区域中形成上贯穿通路225并且分别在下表面和上表面上形成第二结合层226和第三结合层227来制造第一芯片结构220a。
第一芯片结构220a可以通过混合结合第一半导体芯片120的第一结合层126和第一芯片结构220a的第二结合层226连接到第一半导体芯片120。第一半导体芯片120和第一芯片结构220a可以直接结合，而无需布置粘合剂(例如，单独的粘合层)。例如，第一半导体芯片120和第一芯片结构220a可以通过加压工艺以原子级形成耦合。根据示例实施例，可以在结合之前对第一半导体芯片120和第一芯片结构220a的结合表面进一步执行表面处理工艺(例如，氢等离子体处理)，以增强结合力。第一半导体芯片120和第一芯片结构220a可以以晶片级通过晶片与晶片的结合而彼此结合。
参考图11C，可以将第二芯片结构220b结合在第一芯片结构220a上。
类似于第一芯片结构220a，第二芯片结构220b可以在一个衬底上形成第二上半导体芯片221b和222b，并且可以在不锯切的情况下制备。可以通过在下表面上形成第四结合层228来提供第二芯片结构220b。
第二芯片结构220b可以通过混合结合第三结合层227和第四结合层228而结合在第一半导体芯片120和第一芯片结构220a的堆叠结构上。第一芯片结构220a和第二芯片结构220b可以直接结合，而无需布置粘合剂(例如，单独的粘合层)。第一芯片结构220a和第二芯片结构220b可以以晶片级通过晶片与晶片的结合而彼此结合。
参考图11D，可以在第一半导体芯片120的下表面上形成凸块190，并且可以将第一半导体芯片120以及第一芯片结构220a和第二芯片结构220b的堆叠结构锯切成封装单元。
凸块190可以使用沉积或镀覆工艺以及回流工艺形成。
堆叠结构可以被锯切成封装单元，并且可以被切割成使得一个封装件包括一个第一半导体芯片120和四个第二半导体芯片221a、222a、221b和222b。可以在封装单元中沿着第一芯片结构220a和第二芯片结构220b的划片线区域SC的一部分执行切离工艺。因此，在一个封装件中，划片线区域SC可以被去除或部分地保留在芯片区域CH的外部，并且划片线区域SC可以原样保留在芯片区域CH之间。
参考图11E，可以将切割成封装单元的堆叠结构安装在衬底301上。
通过将凸块190连接到衬底301上的衬底焊盘326，可以安装堆叠结构。
参考图11F，可以形成包封堆叠结构的包封部分340。
可以通过诸如层压、涂覆等的方法在堆叠结构上形成构成包封部分340的材料，然后固化该材料，来形成包封部分340。涂覆方法可以是例如丝网印刷方法或喷涂印刷方法。
接下来，通过在衬底301的下表面上形成连接端子390，可以制造图1的半导体封装件1000。
图12A至图12D是示意性示出根据示例实施例的制造半导体封装件的方法的主要逐步视图。在图12A至图12D中，示出了图7的半导体封装件的示例制造方法。在下文中，将不再重复与参考图11A至图11F的描述重叠的描述。
参考图12A，可以将第一芯片结构220a结合在第二芯片结构220b上。
可以如上参考图11B和图11C所述来制造和制备第一芯片结构220a和第二芯片结构220b。第一芯片结构220a和第二芯片结构220b可以通过混合结合第三结合层227和第四结合层228而彼此结合。第一芯片结构220a和第二芯片结构220b可以直接结合，而无需布置粘合剂(例如，单独的粘合层)。第一芯片结构220a和第二芯片结构220b可以以晶片级通过晶片与晶片的结合而彼此结合。
参考图12B，可以在第一芯片结构220a和第二芯片结构220b上形成第二再分布部分130。
可以通过重复执行形成特定厚度的第二布线绝缘层131的工艺、形成穿过第二布线绝缘层131的一部分的通孔的工艺以及使用镀覆工艺等填充通孔以形成第二通路133和位于第二通路133上的第二再分布层132的工艺，来部分地制造第二再分布部分130。
接下来，可以通过在第二再分布部分130的最上部形成图案化的第二结合绝缘层136D，并且使用镀覆工艺等在图案化的区域中形成第二金属焊盘136P来形成第二结合层136。
参考图12C，可以在第二再分布部分130上形成导电柱325，并且可以结合第一半导体芯片120a。
可以通过形成掩模图案并且执行镀覆或沉积工艺来形成导电柱325。
第一半导体芯片120a可以通过混合结合第二再分布部分130的第二结合层136和第一半导体芯片120a的第一结合层126而彼此结合。第一半导体芯片120a和第二再分布部分130可以直接结合，而无需布置粘合剂(例如，单独的粘合层)。
参考图12D，可以形成包封导电柱325和第一半导体芯片120a的包封部分340a，并且可以形成第一再分布部分110。然后，可以形成连接端子390。
可以通过重复执行形成特定厚度的第一布线绝缘层111的工艺、形成穿过第一布线绝缘层111的一部分的通孔的工艺以及使用镀覆工艺等填充通孔以形成第一通路113和位于第一通路113上的第一再分布层112的工艺，来制造第一再分布部分110。
在第一再分布部分110上形成连接端子390之后，通过以单元封装件为单位通过锯切工艺来切割划片线区域SC，可以制造图7的半导体封装件1000c。可以沿着第一芯片结构220a和第二芯片结构220b的划片线区域SC的一部分以单元封装件为单位来执行切割工艺。因此，在一个封装件中，划片线区域SC可以被去除或部分地保留在芯片区域CH的外部，并且划片线区域SC可以保留在芯片区域CH之间。
作为总结和回顾，在功能方面，已经考虑了需要复合(complexation)和多功能化的系统级封装(SIP)，并且在结构方面，已经考虑了多个半导体芯片堆叠并且安装在一个封装衬底上的封装件，或者封装件堆叠在封装件上的堆叠封装(PoP)结构。
如上所述，通过混合结合来连接存储结构和半导体芯片，可以提供具有减小的厚度和高的可靠性的半导体封装件。
这里已经公开了示例实施例，并且尽管采用了特定术语，但是它们仅以一般的和描述性的意义来使用和解释，而不是出于限制的目的。在一些情况下，对于本领域普通技术人员来说，在提交本申请时显而易见的是，结合特定实施例描述的特征、特性和/或元件可以单独使用，或者与结合其它实施例描述的特征、特性和/或元件结合使用，除非另外特别指出。因此，本领域技术人员将会理解，在不脱离所附权利要求中阐述的本发明的精神和范围的情况下，可以进行形式和细节上的各种改变。

Claims (20)

1.一种半导体封装件，所述半导体封装件包括：
第一半导体芯片，所述第一半导体芯片包括位于所述第一半导体芯片的表面上的第一结合层；以及
芯片结构，所述芯片结构堆叠在所述第一半导体芯片上，并且包括位于所述芯片结构的面对所述第一半导体芯片的表面上的第二结合层以及多个第二半导体芯片，其中：
所述多个第二半导体芯片分别包括芯片区域和位于所述芯片区域的外部的划片线区域，所述多个第二半导体芯片在所述芯片结构中通过所述划片线区域彼此连接，并且
所述第一结合层包括第一金属焊盘和围绕所述第一金属焊盘的第一结合绝缘层，所述第二结合层包括第二金属焊盘和围绕所述第二金属焊盘的第二结合绝缘层，所述第一金属焊盘和所述第二金属焊盘设置为彼此对应并且彼此结合。
2.根据权利要求1所述的半导体封装件，其中，所述多个第二半导体芯片在无需彼此锯切开的情况下形成所述芯片结构。
3.根据权利要求1所述的半导体封装件，其中，在平面上，所述芯片结构的尺寸与所述第一半导体芯片的尺寸基本相同。
4.根据权利要求1所述的半导体封装件，其中，所述芯片结构的侧表面暴露于外部。
5.根据权利要求1所述的半导体封装件，其中，所述第一半导体芯片包括其中设置有半导体器件的器件区域和位于所述器件区域的至少一侧的通路区域，所述通路区域具有设置在其中的第一贯穿通路，所述第一贯穿通路电连接所述芯片结构和所述第一半导体芯片。
6.根据权利要求5所述的半导体封装件，其中，所述第一半导体芯片还包括位于整个所述器件区域和所述通路区域上的衬底。
7.根据权利要求5所述的半导体封装件，其中，所述通路区域设置为在平面上围绕所述器件区域。
8.根据权利要求5所述的半导体封装件，其中，所述通路区域包括设置为在平面上沿着所述器件区域的周边彼此间隔开的多个区域。
9.根据权利要求5所述的半导体封装件，其中，所述芯片结构还包括设置在与所述通路区域交叠的区域中的第二贯穿通路。
10.根据权利要求1所述的半导体封装件，其中：
所述芯片结构包括竖直堆叠的第一芯片结构和第二芯片结构，
所述第一芯片结构设置在下部并且包括所述第二结合层和第三结合层，并且所述第二芯片结构设置在上部并且包括连接到所述第三结合层的第四结合层，并且
所述第三结合层包括第三金属焊盘和围绕所述第三金属焊盘的第三结合绝缘层，所述第四结合层包括第四金属焊盘和围绕所述第四金属焊盘的第四结合绝缘层，所述第三金属焊盘和所述第四金属焊盘设置为彼此对应并且彼此结合。
11.根据权利要求10所述的半导体封装件，其中，所述第三结合层位于所述第一芯片结构中的所述第二半导体芯片的有源表面上，所述第四结合层位于所述第二芯片结构中的所述第二半导体芯片的有源表面上。
12.根据权利要求10所述的半导体封装件，其中，所述第三结合层位于所述第一芯片结构中的所述第二半导体芯片的无源表面上，并且所述第四结合层位于所述第二芯片结构中的所述第二半导体芯片的有源表面上。
13.根据权利要求1所述的半导体封装件，其中，所述第一结合层和所述第二结合层直接结合并且彼此接触。
14.根据权利要求1所述的半导体封装件，其中：
所述第一金属焊盘和所述第二金属焊盘包括钨、铝、铜、氮化钨、氮化钽和氮化钛中的至少一种，并且
所述第一结合绝缘层和所述第二结合绝缘层包括SiO、SiN、SiCN、SiOC、SiON和SiOCN中的至少一种。
15.一种半导体封装件，所述半导体封装件包括：
第一半导体芯片，所述第一半导体芯片包括位于所述第一半导体芯片的表面上的第一结合层，并且具有其中设置有半导体器件的器件区域和位于所述器件区域的至少一侧的通路区域，所述通路区域具有设置在其中的贯穿通路；以及
芯片结构，所述芯片结构堆叠在所述第一半导体芯片上并且通过所述第一结合层结合到所述第一半导体芯片，并且包括连接到所述第一结合层的第二结合层以及多个第二半导体芯片，
其中，所述多个第二半导体芯片分别包括芯片区域和位于所述芯片区域的外部的划片线区域，所述多个第二半导体芯片在所述芯片结构中通过所述划片线区域彼此连接。
16.根据权利要求15所述的半导体封装件，其中，所述贯穿通路穿过所述第一半导体芯片并且电连接到所述芯片结构。
17.根据权利要求15所述的半导体封装件，其中，在所述第一半导体芯片中，所述器件区域的上表面和下表面分别与所述通路区域的上表面和下表面共面。
18.一种半导体封装件，所述半导体封装件包括：
第一半导体芯片，所述第一半导体芯片包括位于所述第一半导体芯片的表面上的第一金属焊盘；
第一再分布部分，所述第一再分布部分位于所述第一半导体芯片上，并且包括电连接到所述第一半导体芯片的第一再分布层和位于所述第一再分布层的下表面上并且结合到所述第一金属焊盘的第二金属焊盘；以及
芯片结构，所述芯片结构位于所述第一再分布部分上并且包括多个第二半导体芯片，
其中，在平面上，所述第一半导体芯片的尺寸与所述芯片结构的尺寸基本相同。
19.根据权利要求18所述的半导体封装件，其中：
所述多个第二半导体芯片分别包括芯片区域和位于所述芯片区域的外部的划片线区域，所述多个第二半导体芯片在所述芯片结构中通过所述划片线区域彼此连接，并且
所述芯片区域和所述划片线区域位于一个衬底上。
20.根据权利要求18所述的半导体封装件，所述半导体封装件还包括第二再分布部分，所述第二再分布部分设置在所述第一半导体芯片的下部，并且包括电连接到所述第一半导体芯片的第二再分布层。
CN201910976753.9A 2018-10-24 2019-10-15 半导体封装件 Pending CN111092059A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2018-0127570 2018-10-24
KR1020180127570A KR20200047845A (ko) 2018-10-24 2018-10-24 반도체 패키지

Publications (1)

Publication Number Publication Date
CN111092059A true CN111092059A (zh) 2020-05-01

Family

ID=70325469

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910976753.9A Pending CN111092059A (zh) 2018-10-24 2019-10-15 半导体封装件

Country Status (3)

Country Link
US (1) US20200135684A1 (zh)
KR (1) KR20200047845A (zh)
CN (1) CN111092059A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112968012A (zh) * 2021-02-01 2021-06-15 长江存储科技有限责任公司 扇出型芯片堆叠封装结构及其制造方法

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11562982B2 (en) * 2019-04-29 2023-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit packages and methods of forming the same
US11296053B2 (en) 2019-06-26 2022-04-05 Invensas Bonding Technologies, Inc. Direct bonded stack structures for increased reliability and improved yield in microelectronics
US11114413B2 (en) * 2019-06-27 2021-09-07 Taiwan Semiconductor Manufacturing Company, Ltd. Stacking structure, package structure and method of fabricating the same
US11631647B2 (en) 2020-06-30 2023-04-18 Adeia Semiconductor Bonding Technologies Inc. Integrated device packages with integrated device die and dummy element
US11728273B2 (en) 2020-09-04 2023-08-15 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
US11764177B2 (en) 2020-09-04 2023-09-19 Adeia Semiconductor Bonding Technologies Inc. Bonded structure with interconnect structure
WO2023278605A1 (en) * 2021-06-30 2023-01-05 Invensas Bonding Technologies, Inc. Element with routing structure in bonding layer

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10231385B4 (de) * 2001-07-10 2007-02-22 Samsung Electronics Co., Ltd., Suwon Halbleiterchip mit Bondkontaktstellen und zugehörige Mehrchippackung
KR100905779B1 (ko) * 2007-08-20 2009-07-02 주식회사 하이닉스반도체 반도체 패키지
US7838337B2 (en) * 2008-12-01 2010-11-23 Stats Chippac, Ltd. Semiconductor device and method of forming an interposer package with through silicon vias

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112968012A (zh) * 2021-02-01 2021-06-15 长江存储科技有限责任公司 扇出型芯片堆叠封装结构及其制造方法
CN112968012B (zh) * 2021-02-01 2022-09-09 长江存储科技有限责任公司 扇出型芯片堆叠封装结构及其制造方法

Also Published As

Publication number Publication date
US20200135684A1 (en) 2020-04-30
KR20200047845A (ko) 2020-05-08

Similar Documents

Publication Publication Date Title
KR102127796B1 (ko) 반도체 패키지 및 방법
KR102148909B1 (ko) 이중 측면의 금속 라우팅을 갖는 반도체 패키지
US10541201B2 (en) Semiconductor package, package-on-package device, and method of fabricating the same
CN111092059A (zh) 半导体封装件
KR102492796B1 (ko) 반도체 패키지
US9343333B2 (en) Wafer level semiconductor package and manufacturing methods thereof
EP3093877B1 (en) Semiconductor package
JP6820307B2 (ja) パッケージ構造体及びパッケージ構造体の製造方法
US11545458B2 (en) Semiconductor package
US20190237374A1 (en) Electronic package and method for fabricating the same
TWI739579B (zh) 封裝結構及其形成方法
US10811341B2 (en) Semiconductor device with through-mold via
CN110880457B (zh) 半导体封装件及其形成方法
CN111952274A (zh) 电子封装件及其制法
US20230071812A1 (en) Semiconductor package
CN115910977A (zh) 半导体封装
US20220157757A1 (en) Semiconductor package and method of manufacturing the same
US20230133322A1 (en) Semiconductor package and method of manufacturing the same
US20210257324A1 (en) Semiconductor package
CN219642831U (zh) 一种封装结构
US20240145361A1 (en) Semiconductor package and method for fabricating the same
CN115377074A (zh) 内存装置、封装结构及其制造方法
CN117316884A (zh) 电子封装件及其制法
CN117855152A (zh) 具有接合加强层的半导体封装

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
WD01 Invention patent application deemed withdrawn after publication
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20200501